The VHDL Handbook. David R. Coelho Vantage Analysis Systems, Inc. Kluwer Academic Publishers. KALA llrporation

Transcription

1 The VHDL Handbook

2 The VHDL Handbook by David R. Coelho Vantage Analysis Systems, Inc. ~. " Kluwer Academic Publishers KALA llrporation

3 Distributors for North America: Kluwer Academic Publishers 101 Philip Drive Assinippi Park Norwell, MA 02061, USA Distributors for all other countries: Kluwer Academic Publishers Group Distribution Centre Post Office Box AH Dordrecht, THE NETHERLANDS Consulting Editor: Jonathan Allen, Massachusetts Institute of Technology Library of Congress C a t a l o g i n g ~ l n Data P u b l i c a t l o n Coelho, David R. The VHDL handbook. Bibliography: p. Includes index. 1. VHDL (Computer program language) TK7874.C '2 ISBN-13: DOl: / I. Title e-isbn-13: This reprint edition has been published by KALA CORPORATION under copyright arrangements with KLUWER ACADEMIC PUBLISHERS. Copyright 19X9 by Kluwer Academic Publishers. Third Printing, Softcover reprint of the hardcover 1 st edition 1989 All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, mechanical, photocopying, recording, or otherwise, without the prior written permission of the publisher, Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Massachusetts

4 Contents 1 Introduction Introduction to the VHDL Language History of VHDL DOD Requirements and VHDL VHDL As a Design Tool Multi-Level Design The Model Accuracy Continuum 7 2 Anatomy of a VHDL Model Describing Electronic Hardware in VHDL A VHDL File The Standard Logic Package User Defined Packages VHDL Models and the Accuracy Continuum Value Unit-Delay Approach Value Unit-Delay Approach Fixed-Delay Approach Variable-Delay Approach Generic Variable-Delay Approach Full-Delay Approach Error Checking and Model Structure Handling Timing Using Configurations Using VHDL as a Stimulus Language Standardized VHDL Modelling Conventions Generic Parameters Naming Conventions Constraints Unknown Handling. 54

5 3 Combinational Devices Simple Gates Ioput Positive-Nand Gate Input Positive-Nand with Open-Collector Outputs Input Positive-Nor Gate Inverter Inverter with Open-Collector Outputs Input Positive-And Gate Input Positive-Nand Gate Input Positive-Or Gate Input Positive-Xor Gate Selectors/Multiplexers to 8 Decoder/Multiplexer to 4 Decoder/Multiplexer of 8 Selector/Multiplexer of 4 Selector/Multiplexer of 2 Selector/Multiplexer Switch Level Devices Switch Modelling Utilities Bidirectional Transmission Element Basic Complementary Transmission Gate Basic Transmission Gate Simple ALU's ALU/Function Generator One Shots Mooostable Multivibrator Comparators Bit Magnitude Comparator Parity Generators/Checkers bit Odd/Even Parity Generator/Checker Sequential Devices Flip-Flops D-Type Positive-Edge Triggered Flip-Flop with Preset/Clear JK Pos-Edge Triggered Flip-Flop with Preset/Clear JK Neg-Edge Triggered Flip-Flop with Preset/Clear JK Negative-Edge Triggered Flip-Flop with Preset Registers Bit Parallel-Access Shift Register to 8 Decoder/Demultiplexer with Register to 8 Decoder/Demultiplexer with Latch.. 171

6 Bit Parallel-Out Serial Shift Register Parallel Load 8 Bit Shift Register Parallel Load 8 Bit Shift Register with Clear Counters Synchronous 4 Bit Decade Counter with Asynchronous Clear Synchronous 4 Bit Binary Counter with Asynchronous Clear Synchronous 4 Bit Decade Counter Synchronous 4 Bit Binary Counter Synchronous Up/Down 4-Bit Decade Counter Memory Devices Memory Initialization Read Only Memories bit (256 by 4) ROM ,384 bit (4096 by 4) register PROM Random Access Memories bit RAM PALs, PLDs Calculating Products input, 2 output, 6 I/O PAL input, 2 I/O, 6 clocked output PAL input, 8 clocked output PAL Complex Devices Getting Started Partial versus Full Functional Models Architecture Behavior The Timing Model Device Speeds Min/Max Timing Drive/Loading Dependencies A Uniform Approach to Device Dependent Data Error Handling Unknowns Setup / Hold Time Techniques Waveform Checking Techniques for Modeling Bus Handlers Instruction Decoders.. 300

7 6.4.3 Sequencers Instruction Sets. 6.5 Quality Assurance Developing a Test Plan Validation of the Model 7 The Standard Logic Package 7.1 U sing the Standard Logic Package 7.2 The Logic Value System Technology Rules ECL - Emitter Coupled Logic CMOS - Complementary MOS NMOS - n-channel MOS TTL - Transistor transistor logic TTLOC - Open-collector TTL 7.4 Bus Resolution Logic Manipulation Overloaded Comparison Operators State/Strength Lookup Tables Logic Lookup Tables. 7.6 Timing Utilities Integer Data Utilities. Bibliography Index

8 List of Figures 1.1 DOD/VHDL Documentation Requirements 1.2 Accuracy/Speed/Abstraction Continuum Structure of Design as Schematic Circuit Simulation Results RSFF Structure RSFF Simulation Results Circuit Initialization Problems Circuit Behavior and Timing Simulation of Variable Delay Schematic with Generic Parameter Values Delay Model Input Delays Configurations and Timing VHDL Test Bench RSFF Test Bench Logic Diagram 2-Input Positive-Nand Logic Diagram Open Collector 2-Input Positive Nand Logic Diagram 2-Input Positive-Nor Logic Diagram Inverter Logic Diagram Open-Collector Inverter Logic Diagram 3-Input Positive-And Logic Diagram 3-Input Positive-Nand Logic Diagram 2-Input Positive-Or Logic Diagram 2-Input Positive-Xor Logic Diagram 3 to 8 Decoder/Multiplexer Logic Diagram 2 to 4 Decoder/Multiplexer Logic Diagram 1 of 8 Selector/Multiplexer Logic Diagram 1 of 4 Selector/Multiplexer Logic Diagram 1 of 2 Selector/Multiplexer. 96

9 3.15 Resistor strength drop Capacitor application Logic Diagram ALU /Function Generator Logic Diagram One Shot Logic Diagram 4 Bit Magnitude Comparator Logic Diagram 9 Bit Odd/Even Parity Generator/Checker Logic Diagram D Pos Edge Flip-Flop with Preset/Clear Logic Diagram JK Pos Edge Flip-Flop with Preset/Clear Logic Diagram JK Neg Edge Flip-Flop with Preset/Clear Logic Diagram JK Neg Edge Flip-Flop with Preset Logic Diagram 4 Bit Parallel-Access Shift Register Logic Diagram 3 to 8 Decoder/Demultiplexer Logic Diagram 3 to 8 Decoder/Demultiplexer with Latch Logic Diagram 8 Bit Parallel-Out Serial Shift Register Logic Diagram 8 Bit Parallel Load Shift Register Logic Diagram 8 Bit Parallel Load Shift Register with Clear Logic Diagram 4 Bit Decade Counter with Async Clear Logic Diagram 4 Bit Binary Counter with Async Clear Logic Diagram 4 Bit Decade Counter Logic Diagram 4 Bit Sync Binary Counter Logic Diagram Bit Up/Down Sync Decade Counter Logic Diagram 1024 Bit ROM Logic Diagram Bit PROM 5.3 Logic Diagram 64 Bit RAM 5.4 PAL16L8 Block Diagram 5.5 PAL16R6 Block Diagram 5.6 PAL16R8 Block Diagram 6.1 Bus Functional Model TDC1028 Block Diagram 6.3 Capacitive Loading for Fujitsu MB Model Development Time 6.5 Setup/Hold Time Hardware Model Testing

10 Preface This book is intended to be a working reference for electronic hardware designers who are interested in writing VHDL models. A handbook/cookbook approach is taken, with many complete examples used to illustrate the features of the VHDL language and to provide insight into how particular classes of hardware devices can be modelled in VHDL. It is possible to use these models directly or to adapt them to similar problems with minimal effort. This book is not intended to be a complete reference manual for the VHDL language. It is possible to begin writing VHDL models with little background in VHDL by copying examples from the book and adapting them to particular problems. Some exposure to the VHDL language prior to using this book is recommended. The reader is assumed to have a solid hardware design background, preferably with some simulation experience. For the reader who is interested in getting a complete overview of the VHDL language, the following publications are recommended reading: An Introduction to VHDL: Hardware Description and Design [LIP89] IEEE Standard VHDL Language Reference Manual [IEEE87] Chip-Level Behavioral Modelling [ARMS88] Multi-Level Simulation of VLSI Systems [COEL87] Other references of interest are [USG88], [DOD88] and [CLSI87] Use of the Book If the reader is familiar with VHDL, the models described in chapters 3 through 7 can be applied directly to design problems. A review of chapters 1 and 2 will give a clear overview of the methodology and intended scope of the models described in this book. All other chapters can be used in a reference fashion, reading only those sections which discuss the specific type of device for which a VHDL model is desired. Chapter 1 describes the history and background of the VHDL language and provides recommendations on how to get started quickly with VHDL.

11 Chapter 2 discusses the overall format of a VHDL file and the particular methodology used in models described in this book. Chapter 3 describes the VHDL models for a number of combinational devices. The reader is encouraged to review this chapter before studying other more complex device models. Chapter 4 describes the VHDL models code for a wide variety of sequential devices including registers, flip-flops, counters and others. Chapter 5 discusses memory devices and includes the VHDL source code for devices ranging from RAMs and ROMS to PLAs. Chapter 6 discusses the VHDL modelling of complex devices such as microprocessors. Examples are given to highlight modelling techniques. Recommendations regarding proper methodologies for complex devices are given. Finally, chapter 7 gives the complete VHDL source code for the standard logic package and discusses how to build a logic value system, bus resolution functions, logic modelling utilities and timing utilities. Getting Started Quickly with VHDL All of the examples in this book are written using strictly standard VHDL which adheres to the IEEE standard [IEEE87]. The modelling features and approaches used in the VHDL code in this book have been tested against both the Vantage and Intermetrics tools. Other tools which adhere to the VHDL standard should handle the examples without difficulty (assuming that the required VHDL features are available). Virtually all of the examples in this book rely on the availability of the Standard Logic Package described in chapter 7. The easiest and fastest way to get started writing and simulating with VHDL models discussed in this book is to get a copy of this standard package. This package is in the public domain and is not specific to any particular VHDL environment. Once compiled in your VHDL environment, you can reference this package from your models and begin creating models which follow the conventions and approaches discussed exactly as shown or with your own modifications incorporated. By following this approach it should be possible to begin writing VHDL models which simulate effectively within an afternoon. In order to facilitate this process, all examples including the Standard Logic Package discussed in this book are available on IBM PC floppy format for MS-DOS. If you are interested in getting on-line VHDL source code for the examples in this book send your request to Coelho Publications, Christy Street, Fremont, CA

12 Background on the Writing of this Book All examples cited in this book have been validated using the Vantage Spreadsheet simulation environment [VANU89] [VANT89] developed and marketed by Vantage Analysis Systems, Inc. The text for this book was prepared using the 'lex text formatting system [LAM86] [KNU86] developed by Donald Knuth at Stanford University running on an Apollo workstation with camera ready copy produced on an Apple Laserwriter. Graphics figures were created using the Vantage environment for simulation results, and AutoCAD [AUT88] for schematic and free form graphics. Acknowledgments Bill Billowitch provided insightful input into techniques for modelling complex devices and is largely responsible for the discussions regarding the modelling of microprocessors. Bill also contributed heavily in review of the manuscript. I am greatful for Bill's substantial contribution. I am indebted to Ken Scott, Doug Perry, Andy Tsay and Alec Stanculescu all of whom contributed to the development and evolution of the standard logic package and the switch level modelling techniques. Thanks also goes to others who reviewed the manuscript including Rick Lazansky, Paul Krol, Tom Miller, Al Dewey, John Hines, John Van Tassel, Karen Serafino, John Evans and David Hemmendinger.

13 The VHDL Handbook