Design For Manufacture

Transcription

1 Design For Manufacture Presented by Bill Frank Multek Applications Engineer

2 Discussion Agenda Goals and Objectives DFM Process Flow Board Layout Analysis of Features Board Layout Yield Drivers Electrical Test Issues Stackups and Materials HDI Design

3 DFM Engineering Goals Help Provide Solutions Design PCB Fab DFF DFx How? ƒ Provide a macro review of the board design ƒ Assist in meeting functional performance goals. ƒ Help to eliminate surprises during factory tooling. ƒ Assist with conveying development costs. ƒ Maximize manufacturability of the design. ƒ Help meet critical time to market goals. Assembly DFA

4 DFM Process Flow

5 DFM Process Flow Customer electronic data loaded into Frontline Genesis Data loaded as pre-release (no order) under temporary tool # Pre-CAM DRC run to find gross design errors Review of layout data in Genesis including DRC violations Design analyzed for compatibility with Factory capabilities Stackup generated consideration for customer requirements and Factory capabilities/qualifications. DFM report prepared, includes graphic snapshots from Genesis of specific design issues

6 DFM Process Data and Documentation Formats For DFM Artwork data, ODB ++ (preferred), Gerber 274X or 274D Embedded Aperture information preferred, either ODB++ (best) or Gerber 274X N/C Drill & Route Data Excellon or Plotter Format Drill Tool information, Embedded header or ASCII file Fabrication Drawings, HPGL, AutoCAD, PDF, or Postscript

7 DFM Process Genesis has data output available after DRCs are run, a report is generated in text format Applications Engineer with DRC report in hand conducts a review of the board layout in Genesis. This process will include the disposition of violations identified during DRC process. Will make use of screen captures to highlight problem locations. Customer supplied fabrication data drawings and notes are analyzed All information is consolidated into a DFM document

8 DFM Process Standard DFM Report for all factories Can be used by field or factory personnel

9 DFM Process Section for recording of hole sizes and features Checklist of standard items that effect factory yields

10 DFM Process Section for summarizing design with comments In checklist form signoff on manufacturability

11 DFM Process Stackup included with report factory compatible

12 Board Layout Guidelines

13 Board Layout Analysis and Yield Drivers Analysis of board layout, review of lines, spaces, hole sizes, and related features is the heart of DFM process. Inclusion or omission of certain features can significantly affect manufacturing yields. Substantial amount of time is spent during the DFM analysis to identify and communicate potential layout issues Slides in this section highlight feature types analyzed and typical yield drivers. Excerpted from the Multek Global PCB Fabrication Guide

14 Board Layout Analysis All plated hole sizes and related pads are examined for compliance with factory minimums Hole/pad ratio

15 Board Layout Analysis Signal layers checked for line size and spacing Design must allow for tooling modification for factory processing

16 Board Layout Analysis Non plated holes are reviewed for location and size. A/W features typically removed

17 Board Layout Analysis Internal anti-pad and corresponding hole size is verified for correct ratio Both PTH and NPTH features require same ratio

18 Board Layout - Analysis Inner signal layout allowances for process Before Lamination After Lamination (note Material Shrinkage) Drill.010 Clearance Rules Violation with Non Functional Pads Removed Pad Diameter True Position

19 Board Layout Analysis Outer layer features are checked for compatibility with factory soldermask requirements. Supplied soldermask files can be used for reference

20 Board Layout Analysis Silkscreen examined for character size and location to adjacent signal pads Standard practice is to clip features, not to relocate

21 Board Layout Analysis Mechanical layout is checked for manufacturing compatibility

22 Board Layout - Yield Driver Acid Traps Attached trace - less than 90 degree connect to SMT pad, potential to trap chemistry 45 degree trace.006 min. Potential latent defect Correct layout

23 Board Layout - Yield Driver Non Functional Pads on internal layers Inclusion of non functional pads adds unnecessary spacing, decreases layer yield

24 Board Layout - Yield Driver Non Functional Pads on internal layers After removal many small spaces eliminated increasing layer yield

25 Board Layout - Yield Driver Trace routing is critical to enhancing yields Should be equidistant routing between pads

26 Board Layout - Yield Driver Tear Dropping Typical circuit/pad connect Addition of fillet teardrop feature enhances pad area at circuit junction Snowman technique same enhanced area

27 Board Layout - Yield Driver Low Pressure areas Copper added to open glass areas for more consistent dielectric thickness

28 Board Layout - Yield Driver Open areas on signal layers cause plating/etching issues

29 Board Layout - Yield Driver Typical Thieving Pattern square spacing Thieving pattern added better control of circuit pattern during plating

30 Board Layout - Yield Driver Copper silvers on planes.004 min Suggested minimum copper feature be.004, this example, spacing between anti-pads. Greatly reduces potential of copper to redeposit elsewhere on the layer. Anti pad Drilled hole

31 Board Layout - Yield Driver Maintain.010 min. pad Min. mask stripe SMT Pitch.003 mask clearance Solder Mask Feature Size If SMT pad to pad spacing is less than.010 mask stripe less than.004 may cause manufacturing issues, window mask clearance may be required

32 PCB Electrical Test

33 PCB Testing Issues Need to consider SMT Component pitch to determine board testability. May be necessary to contact the fabrication house for assistance. Typically production level boards will use a fixtured method. Boards with components at less than 16 mil pitch will require a fixtureless or flying probe test method. Flying Probe test well suited for QTA/prototype work. Test points should be a separate, distinct feature size. This allows maximum flexibility during tooling. Good idea to standardize on the test point convention, use the same pad size, soldermask configuration, and side of the board where points are located.

34 PCB Testing Issues Net List Testing is Conducted Using Either Gerber File Extracted Net List Data or IPC-D-356 Net List Standards Compliant Data. Typical Test Methods Include Single Sided Fixtures Which Support Both the Through Hole and Mixed Technology Single Sided Testing Requirements. Dual Axis Test Machines Are Replacing the Old Double Sided Clam Shell Fixturing Methods. Dual Access (Tests Both Sides of a 2 Sided SMT PCB Simultaneously) Fixtures are Used Primarily for Complex Double Sided Boards. They are Used When Boards Have SMT Active and Passive Components on Both Sides, but Some Board Circuits Can Only be Tested If Tests are Conducted on Both Sides of the Board Simultaneously. High Density (an Extremely Dense 2 Sided SMTand / or BGA), May Require Multiple Fixtures (3 or More) to Accomplish the Test.

35 Stackups and Materials

36 Stackups and Materials Stackup details dielectric thickness and copper weights are reviewed for compatibility. Is the dielectric thickness sufficient to fill the copper and give the specified final thickness? Does the minimum hole size (drill) and final board thickness meet aspect ratio minimums? Design should consider Z-axis expansion and ability of factory to plate adequate thickness of copper on the hole wall. Does stackup meet electrical requirements?

37 DFM Materials Improved Speed Signal Integrity Region 5.0 Polyimide Epoxy/ PPO Epoxy Blend APPE Epoxy Blend SI BT High Tg Epoxy Std. Epoxy Epoxy Thermount D 1MHz PTFE/Glass 2.0 Speedboard MHz Source: Nelco

38 DFM Materials Material Types Material Tg CTE E r Tan δ U.L.94 X-Y, ppm/c Z, ppm/c 1 MHz 10 GHz 1 MHz 10 GHz PTFE Arlon CLTE Rogers PTFE/Cer Rogers R Rogers R CHO/Glass Rogers Rogers V-0 Rogers V-0 Thermount Arlon 55NT V-0 Arlon 55RT V-0 Arlon 85NT V-1

39 DFM - Materials Material Types Material Tg CTE E r Tan δ U.L.94 X-Y, Z, ppm/c ppm/c 1 MHz 1 GHz 1 MHz 1 GHz Tetra FR4 Isola FR V-0 Isola FR V-0 Multi FR4 Nelco N % V-0 Isola FR V-0 Nelco N % V-0 Nelco N SI % V-0 Epoxy/PPO GE Getek ML % V-0 Epoxy/BT Nelco N % V-0 Cyanate Ester Nelco N % V-0 Polyimide Nelco N7000-2HT <2.5% V-0

40 DFM - Materials FR- 4 PREPREG (B-STAGE) AND CORE SELECTI ON Here Are Five Basic Styles of Glass Cloth / Prepreg Used in the Manufacture of Printed Wiring Boards, Although Other Styles Are Becoming Popular Due to Cost, Availability Etc STYLE NOMINAL Resin E r * THICKNESS % Pure Resin ~3.1 Dk Fiberglass ~6.3 Dk From the Above Selection, Most Laminate Material Thickness Can Be Manufactured by Using Multiples or Combinations of Any Glass Style Each Combination of Glass Styles Has It s Own Characteristics in Terms of Dimensional Stability, Fill Characteristics, Processability, and E r *Based on test data at 1 GHz

41 HDI Design

42 HDI Design Checks Does customer design reflect factory capability. Design analyzed for: - A/w features for micro vias. - Specified diameter of micro via. - Required dielectric thickness and type of material. - Aspect ratio of micro via to dielectric thickness. - Additional operations required beyond laser drilling.

43 HDI Design Details Current HDI capability One layer build up Two layers build up Min. via Material Min. via Structure & Picture Drill Method Material size Picture Drill Method size RCC 75um Yag laser RCC 85um L1/2 & L2/L3 (staggered) Yag laser FR um Yag laser +CO 2 laser 200um L1/L3 (stacked) Yag laser FR um Yag laser +CO 2 laser FR4 125um L1/2 & L2/L3 (staggered) Yag laser +CO 2 laser FR um Yag laser +CO 2 laser 250um L1/L3 (stacked) Yag laser One layer build up (Laser via over buried via) Stack uvia FR um Yag laser +CO 2 laser RCC or FR4 125um Yag laser +CO 2 laser

44 HDI Design Details

45 HDI Design Details Fabrication Capability Recommendation Reason Min. Microvia Drill (D) RCC Prepreg 106 / 1080 Prepreg Not recommended Good Plating Distribution In Vias Microvia Pad Size Outer Capture Pad (C) Target Pad Size (W) Drill Drill Drill Drill Higher Yield For >1 Layer Of Laser Vias HDI Dielectric Thickness RCC Material Prepreg 106 Prepreg 1080 Prepreg / / / / / / / / /-.001 Not Recommended Value and Tol. For Reference Only. Thickness May Vary Due to Circuit Density

46 DFM Process 7KDQN<RX