FlowCAD Schweiz AG. Tel. +41 (0) Fax +41 (0) OrCAD Professional. Allegro Designer. OrCAD Standard

Transcription

1 Licensing Floating Networked License 12 Months Maintenance Support Included In Purchase Price SCHEMATIC ENTRY + DATA MANAGEMENT Graphical, flat and hierarchical page editor and Picture block hierarchy Marketplace to download apps PSpice AD Lite (up to 75 nodes) Net Groups - Complex bus definition AutoWire 44,000 Schematic symbols Coloured Components / nets Tcl TK scripting support Online design rule check including custom DRC capability and Waive DRC Forward and back-annotation of properties / pin-and-gate swaps Schematic Part and Library editor Cross-probing and cross-placing FPGA design-in / pin import & export Multiple PCB netlist interfaces SI Topology creation Digi-Key (PartLink App) Component Parametric data directly from web Property editor for pins, components, nets SigXplorer SI Analysis PDF creation Updated in 17.2 Updated in 17.2 Updated in Annotation New in 17.2 New in 17.2 New in Compare (detail and Graphical) New in 17.2 New in 17.2 New in Demo designs New in 17.2 New in 17.2 New in Preferences New in 17.2 New in 17.2 New in ISCF (Intel Schematic Connectivity Format) New in 17.2 New in 17.2 New in / Import XML New in 17.2 New in 17.2 New in Importer Schematic (PCB also available) Importer Schematic (PCB also available) Component Information System CIS option CIS option Windows ODBC compatible format CIS option CIS option Interface to relational database and management systems CIS option CIS option Database query for part selection and parametric properties CIS option CIS option Schematic and BOM Variants Manager (Parts not Fitted and more). CIS Database Management Interface (access control and more) Part search DIGIKEY, FARNELL, FUTURE, MOUSER, ARROW CIS option CIS + CIP E CIS + CIP E CIS option CIS + CIP E CIS + CIP E CIP E CIP E PCB Suites Matrix Page 1/6

2 PCB EDITOR Physical, Spacing, Same net, Netclass and Class to Class rules Updated in 17.2 Updated in 17.2 Updated in Pad Entry / Exit Rules Updated in 17.2 Updated in 17.2 Updated in pad suppression / Unused Pad removal Updated in 17.2 Updated in 17.2 Updated in Section Editor Updated in 17.2 Updated in 17.2 Updated in Editor IPC2581 Compliant Updated in 17.2 Updated in 17.2 Updated in Visibility Pane Updated in 17.2 Updated in 17.2 Updated in 17.2 Dynamic Shape Pin Connection By Layer (Global/Shape/Pin/Layer) Updated in 17.2 Updated in 17.2 Updated in Cross Hatch Shapes Updated in 17.2 Updated in 17.2 Updated in 17.2 Interactive Routing using Working Layer (layer selection popup) Multiple placement options, manual, quickplace, auto and Placement directly from schematic, individually or window Dynamic Shapes (dynamic copper pours) Plow and Heal Push, Shove and Hug interactive editing Embedded net names Curve Routing Auto Finish (Route Completion Tool) Through Board Transparency (OpenGL) Multi line routing (Group Routing) Fan out generators Flip Board Excellon NC Drill File export Gerber 274X, 274D artwork Output IPC2581 Import / Export Mentor ODB++ and universal viewer DFM Checks including soldermask, solderpaste and more rat suppression with autoroute adjust (Slide) cleanup, optimization (Glossing) Updated in 17.2 Updated in Calculator Interactive / Automatic Silkscreen generation Blind Buried Single Click multiple via instantiation Manual Design For Test (DFT) / Test Prep Component Height DRC Aligment x and y for components and modules Associative Dimensioning View Routing for Hex pattern ICs Altium PCB (schematic also available) EAGLE PCB (schematic also available) Import PADS & PCAD IFF RF Shapes Export DXF MCAD/ECAD Incremental design data exchange (IDX) Export IDF Crossprobing Updated in 17.2 Updated in 17.2 Updated in D Clash Detect Updated in 17.2 Updated in 17.2 Updated in D viewer for selected item or complete PCB. Updated in 17.2 Updated in 17.2 Updated in D In/Out Updated in 17.2 Updated in 17.2 Updated in 17.2 PCB Suites Matrix Page 2/6

3 Mode (General, Etch, Placement) Mode (shape) Sketch Routing Skill Support route Bus Route and via patterns New in Fattening New in 17.2 New in Pair Static Phase Control rules New in 17.2 Differential Pairs Physical rules and routing New in delay rules (Relative) for nets or groups delay rules (Min/Max) for nets or groups Heads up Display for critical rules Contour routing (Flex) Shape based curve fillet support, tapered traces Placement replication, template based design reuse Constraint Regions, region based rules (Rigid Flex; BGA Total Etch Length - Max/Min Length Tuning Design For Test (DFT) / Test Prep Single Ended Worksheet Scheduling, T Point rules (pin to T point), T Point array / Shielding - Shape and Trace based Extended (X)net rules Pin Pair rules over void detection New in lines between voids New in Cross Section support for Rigid Flexi New in 17.2 New in Flexi Zone Management New in 17.2 New in Zone Placement New in 17.2 New in Layer Checks for Rigid Flexi New in 17.2 New in set rules New in Phase Control rules Pin Delay (for die 2 die delay) rules Axis delay feedback CAD Translators - Import Mentor Boardstation Max Via Count rules Dynamic DFA rules based interactive placement Offset Routing Design planning Create hierarchical Bundles Design planning Create, Edit Flows Design planning Assign Flows to Layers Dynamic Shape based curve fillet support, tapered traces Plan Spatial Feasibility analysis & feedback Generate Topological Plan Convert Topological plan to traces (CLINES) Auto Connect (Breakout, Connect, Compress, Spread, Nudge, Push) Interactive Break-out (AiBT) PCB Suites Matrix Page 3/6

4 Automatic Delay Tune (AiDT) Automatic Phase Tune (AiPT) Tuning Timing Vision (Coloured tracks based on constraint adherence) Speed Via Structures Voiding Differential Pairs Tabbed Routing net Return Paths Vias Electrical Constraint rule set (ECSets) / Topology Apply Electrical rules (Reflection, Timing, Crosstalk) Advanced Constraints (formulas, relational) Weave Effect Zig Zag Auto Interactive Pair Return Path Vias Manager: HDI rule set Micro-via and associated spacing, stacking and via-in-pad rules driven HDI design flow micro-via stack editing rule support for embedding components components on inner layers for Cavities on inner layers for Vertically placed components on inner layers Soldermask for embedded components Support for copy and swap embedded components Side Contact Embedded Components Concurrent Team Design Layer by Layer Concurrent Team Design Functional block partitioning New in 17.2 Mini New in 17.2 Mini PCB Suites Matrix Page 4/6

5 Concurrent Team Design Team design dashboard Concurrent Team Design Soft boundaries Concurrent Team Design - Constraint Editing and Netclasses per Partition Harmony Team Design New in Swap pins on a FPGA (based on FPGA rules) in PCB Editor Reoptimize pins on a FPGA (using FPGA rules) Parameterized RF etch elements Asymmetrical Clearances RF Etch elements editing Bi Directional interface with Agilent ADS ADS schematics Import Agilent into DE HDL Layout driven RF design creation Flexible Shape Editor Harmony Team Design FPGA System Planner FPGA System Planner PSpice SIMULATION Bias Point, DC sweep, AC sweep & transient analysis (with PSpice AD PSpice AD PSpice AD Parametric Analysis PSpice AD PSpice AD PSpice AD Learning PSpice Free Templates PSpice AD PSpice AD PSpice AD Analog behavioural modelling PSpice AD PSpice AD PSpice AD Stimulus editor PSpice AD PSpice AD PSpice AD Model Editor for device characterization PSpice AD PSpice AD PSpice AD Interactive waveform viewer & analyzer PSpice AD PSpice AD PSpice AD IBIS / DML model support PSpice AD PSpice AD PSpice AD Monte Carlo: Statistical circuit behaviour and yield (Worst Case) PSpice AD PSpice AD PSpice AD Bias point voltages, currents and power display on schematic PSpice AD PSpice AD PSpice AD Sensitivity: Identifies critical circuit components Advanced Analysis Advanced Analysis Advanced Analysis Optimizer: Optimizes key circuit components Advanced Analysis Advanced Analysis Advanced Analysis Monte Carlo: Statistical circuit behaviour and yield multiple measurements Advanced Analysis Advanced Analysis Advanced Analysis Smoke: Detects component stress Advanced Analysis Advanced Analysis Advanced Analysis Parametric Plotter: Examine solution through nested sweeps Advanced Analysis Advanced Analysis Advanced Analysis Optimize Circuits through Curve or Parameter Fit Advanced Analysis Advanced Analysis Advanced Analysis Example Design Simple Circuit 1 Example Design Simple Circuit 2 Example Design Simple Circuit 3 Example Design Simple Circuit 4 PCB Suites Matrix Page 5/6

6 Example Design Simple Circuit 5 Example Design Simple Circuit 6 Example Design Simple Circuit 7 SIGNAL INTEGRITY & Post-route signal integrity analysis Graphical topology definition and exploration Interactive waveform viewer Macro modelling support (DML) IBIS 5.0 support IBIS ICM model support Spectre-to-DML HSPICE-to-IBIS Lossy transmission lines Coupled (3 net) simulation Differential pair exploration and simulation AUTOROUTER 6 Signal Layers at a time (no board layer limit or pin limit) Shape-based or Gridded routing SMD Fanout Physical Trace Width by Net and Net Classes 45-degree / Memory Pattern Routing Interactive Routing with Shoving and Plowing Interactive Floorplanning Online Design Rule Checking Flip, Rotate, Align, Push, and Move Components Placement Density Analysis Min/Max, matched length rules based autorouting Pin-pair rules, Area rules based autorouting Crosstalk controls, parallelism rules based autorouting Differential Pair Autorouting, Automatic net shielding High-speed rules-based autorouting 256 signal layer limit AI DFM rules-based autorouting automatic trace spreading, via reduction and mitering Spacing Net Class - Class Rules Via Rules by Net and Net Class Mircovia features including Plural and Stacked microvias Auto Test Point Generation and Clearance Rules Layer-specific rules-based autorouting PCB Suites Matrix Page 6/6