LD7832A 4/17/2013. High Power Factor LED Controller with HV Start-up. General Description. Features. Applications. Typical Application REV: 00

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1 4/17/2013 High Power Facor LED Conroller wih HV Sar-up REV: 00 General Descripion The is a buck soluion wih high PFC conrol for LED lighing. I feaures HV sar-up, easy o design wih minimum cos and PCB size. The device operaes in ransiion(tm) mode and inegraes wih complee safey requiremen proecions. Wih HV sar-up echnology, high power facor and TM conrol, he sysem is enabled o achieve high PF and high efficiency o mee mos of he inernaional sandard. The also feaures LED open proecion (OVP), LED shor proecion ( UVP), over curren proecion (OCP), CS shor proecion (CSSP), open feedback proecion and over emperaure proecion (OTP). I makes he circui designers easily o mee mos safey requiremens in eiher normal or abnormal es. Feaures Buil-in 600V HV sarup High power facor conroller inegraed High efficiency ransiion mode operaion Accurae curren regulaion Wide range of UVLO (17.5 V ON and 8 V OFF) VCC OVP (VCC over Volage Proecion) UVP ( under volage proecion) OCP (Cycle by cycle curren limi) CSSP (CS shor proecion) Open feedback proecion OTP (Over Temperaure Proecion) 250/-500mA Driving Capabiliy Applicaions LED Lamp LED bulb Applicaion Typical Applicaion R 1 6 VCC 2 COMP GND 4 8 HV CS 3 AC Inpu EMI Filer GATE 5 Rs Fig. 1 Applicaion Circui -DS-00 April

2 Pin Configuraion SOP-7 SOP-8, DIP TOP MARK YYWWPP COMP CS GND HV VCC OUT 6 HV NC VCC OUT TOP MARK YYWWPP COMP CS GND YY: WW: PP: Year code Week code Producion code Ordering Informaion Par number Package Top Mark Shipping GR SOP-7 GR 2500 /ape & reel GS SOP-8 GS 2500 /ape & reel GN DIP-8 GN 3600 /ube /Caron The is ROHS complian/ green packaged. Pin Descripions Pin NAME FUNCTION 1 Quasi resonance deecor 2 COMP Compensaion pin for inernal error amplifier 3 CS Curren sense pin, connec o sense he MOSFET curren for FB and OCP. 4 GND Ground 5 OUT Gae signal oupu 6 VCC Power supply o VCC 7 NC No connecion 8 HV Connec his pin o he posiive of main bulk cap o provide he sarup curren for conroller. When VCC is UVLO on, he HV loop will open and urn off inernal curren source o minimize he power loss. -DS-00 April

3 Block Diagram VCC HV Regulaor HV UVLO On/Off UVLO Comparaor inernal bias & Vref Vref OK All Block VOVP /28V VCC OVP VCC OK PG 6.5V PDR VCC OVP S Q Driver Sage OUT PG R CSSP/ Oupu SCP 1V/1.3V Fmax Limi PWM Comparaor Time Ou S Q Max On Limi R Vref GM Ramp Generaor OCP Comparaor 1V LEB CS FB Comp CSSP/ Oupu SCP Q PDR S CSSP Delay Couner 0.08V R Couner PG Oupu SCP Delay Couner VUVP GND -DS-00 April

4 Absolue Maximum Raings VCC CS I HV COMP OUT Maximum Juncion Temperaure Sorage Temperaure Range Package Thermal Resisance (SOP-7/SOP-8, JA) Package Thermal Resisance (DIP-8, JA) Power Dissipaion (SOP-7/SOP-8) Power Dissipaion (DIP-8, a Ambien Temperaure = 85 C) Lead emperaure (Soldering, 10sec) ESD Volage Proecion, Human Body Model (excep HV pin) ESD Volage Proecion, Machine Model -0.3 ~ 30V -3 ~ 6V -0.3 ~ 6V -4 ~ 2mA -0.3 ~ 600V -0.3 ~ 6V -0.3 ~ 30V 150 C -65 C o 150 C 160 C/W 100 C/W 250mW 400mW 260 C 2.5KV 250 V Cauion: Sress exceeding Maximum Raings may damage he device. Maximum Raings are sress raings only. Funcional operaion above he Recommended Operaing Condiions is no implied. Exended exposure o sress above Recommended Operaing Condiions may affec device reliabiliy. Recommended Operaing Condiions Iem Min. Max. Uni Vcc V Vcc pin capacior F Comp pin capacior F Operaing Juncion Temperaure Range C Operaing Ambien Temperaure Range C -DS-00 April

5 Elecrical Characerisics (V CC =14.0V, T A = 25 C unless oherwise specified.) PARAMETER CONDITIONS MIN TYP MAX UNITS High volage Supply(HV Pin) High-volage Curren Source V CC<6V, HV=80V ma 6V<V CC<UVLO (ON) ma Off-sae Leakage Curren V CC>UVLO(ON), HV=600V A Supply Volage (VCC Pin) Sarup Curren V CC<UVLO CC=14V A Operaing Curren (wih 1nF Load on OUT pin) COMP pin open, =12V ma V CC OVP ripped ma UVLO (OFF) V UVLO (ON) V VCC OVP Level V HV Self Bias (Linear Regulaor) V De-lach V CC Volage PDR V Compensaion (COMP Pin) Open Loop Volage COMP pin open V On Time V COMP=2V s Curren Sensing (SOURCE Pin) Reference Volage(V REF) V OCP Threshold (cycle-by-cycle) V LEB Time (1) ns The rip level for Rs Shor proecion V Delay Couner for RsSP ms Zero Curren Deecor ( Pin) Upper Clamp Volage IN=12V V Lower Clamp Volage IN=0V V Inpu Volage Threshold (1) V Hyseresis V The rip level for UVP (1) V Delay Couner of UVP ms -DS-00 April

6 PARAMETER CONDITIONS MIN TYP MAX UNITS Minimum (ON+OFF)-Time, F SW,MAX ( Pin) F SW,MAX (1) Minimum (ON+OFF)-Time KHz Gae Drive Oupu (OUT Pin) Oupu Low Level V CC=15V, I O=20mA V Oupu High Level V CC=15V, I O=20mA 8 - VCC V Oupu High Clamp Level V CC=16V V Rising Time (1) V CC =15V, C L=1nF ns Falling Time (1) V CC =15V, C L=1nF ns Sarer Sar Timer Period s OTP (Over Temp. Proecion) OTP Trip Level (1) C OTP Hyseresis (1) C Noe: (1) Guaraneed by design -DS-00 April

7 HV Curren Source (ma) De-lach Vcc Volage (V) HV Slef Bias (V) HV Curren Source (ma) UVLO (on) (V) UVLO (off) (V) Typical Performance Characerisics Fig. 1 UVLO (on) vs. Temperaure 7.5 Fig. 2 UVLO (off ) vs. Temperaure Fig. 3 HV Slef Bias vs. Temperaure 0.75 Fig. 4 HV Curren source(vcc=1v) vs. Temperaure Fig. 5 HV Curren source(vcc=14v) vs. Temperaure 6.5 Fig. 6 De-lach Vcc Volage vs. Temperaure -DS-00 April

8 VCC OVP (V) Sandby Curren (ma) On Time (us) Reference Volage (V) Fig. 7 On Time(Comp=2V) vs. Temperaure 0.17 Fig. 8 Reference Volage vs. Temperaure VCS (off) (V) Fig. 9 V CS (off) vs. Temperaure 0.20 Fig. 10 Sandby Curren vs. Temperaure VCOMP (V) Fig. 11 VCC OVP vs. Temperaure 5.2 Fig. 12 V COMP open loop volage vs. Temperaure -DS-00 April

9 Applicaion Informaion Operaion Overview is an LED conroller for lighing applicaion. The ransiion mode (TM) echnique mees he requiremen of high power facor in high efficiency. I minimizes he exernal componen couns and he PCB size for compac applicaion. is also designed o operae in volage-mode TM mode. The swich urn-on ime is fixed while he urn-off ime varies in seady sae. Therefore, he swich frequency changes in response o he differen volages. The affeced frequency reduces EMI noise. also feaures LED open proecion, LED shor proecion, over curren proecion, CS shor proecion, open feedback proecion, and over emperaure proecion. No exra mains volage sensing is required as wha he radiional curren mode PFC conrollers behaves for power saving. increase o 3mA once VCC rises above PDR volage hreshold during sar-up. Meanwhile, he VCC supply curren is as low as 280 A ha mos of he HV curren is reserved o charge he VCC capacior. By using such configuraion, he urn-on delay ime will be almos same no maer under low-line or high-line condiions. As he VCC volage rises higher han UVLO(on) o power he and furher o deliver he gae drive signal, he high-volage curren source will be disabled and he supply curren is provided from he inducor. Therefore, i would reduce he power loss on he sarup circui and perform highly power saving. An UVLO comparaor is embedded o deec he volage on he VCC pin o ensure he supply volage enough o power on he conroller and in addiion o drive he power MOSFET. As shown in Fig. 2, a hyseresis is provided o preven he shudown from he volage dip during sarup. Inernal High-Volage Sarup Circui and Vcc Under Volage Lockou (UVLO) UVLO(on) The radiional circui provides he sarup curren hrough a resisor o power up he PWM conroller. UVLO(off) PDR However, i consumes oo significan power o mee he curren power saving requiremen. In mos cases, larger resisor carries larger resisance; i wases more ime o HV Curren sarup. 1mA 3mA To achieve he opimized opology, as shown in Fig.1, is implemened wih a high-volage sarup circui on HV pin for i. During sarup, a high-volage curren source sinks curren from he oupu of Vcc curren Sarup Curren ~ 0mA (off) Operaing Curren (Supply from Inducor) full-bridge recifier o provide he sarup curren and charge he VCC capacior. Once VCC drops below PDR, he charge curren will remain a 1mA o proec he circui from being damaged, even in case VCC pin is Fig. 2 shored o ground. In conras, he charge curren will -DS-00 April

10 Ramp Generaor Block and Zero Curren OUT Deecion () Fig. 3 shows ypical ramp generaor block and RAMP IPEAK VCOMP block. The COMP pin volage and he oupu of he ramp generaor block are compared o deermine he Inducor Curren TON TDIS VOUT 0A MOSFET On-ime, as shown in Fig. 4. The feaures ransiion mode operaion. The Inducor Volage VOUT-VIN 0V zero curren deecion block circui deecs he Delay Time 5.3V signal o urn on he MOSFET soon afer he volage Volage 1V across falls o 1V and also he curren hrough he inducor reaches zero. Insead, if here s no signal VIN 0.3V deeced wihin 70 s, he ime-ou will generae a signal o urn on MOSFET o ensure he sysem operae properly. VDS Fig. 4 Minimum Volage Turn-on 0V Time 1V/1.3V Ou Fmax S Q Limi PWM Comparaor Max On Limi R Ramp OCP Comparaor Vref Generaor GM 1V FB Comp Fig. 3 During he delay ime as shown in Fig. 4, he juncion capacior of he MOSFET resonaes wih he inducor and he drain-source volage (VDS) decreases accordingly. So, he MOSFET consumes less volage and he power dissipaion will be minimized. LED Shor Proecion ( UVP) Auo Recovery To proec he circui from damage due o LED shor condiion, an auo-recovery ype of UVP proecion is implemened for i. Fig. 5 shows he waveforms of he UVP operaion. In LED shor condiion, he refleced oupu volage of inducor will cause volage drop. If he volage sinks below 4.3V for more han he delay ime of UVP, he proecion will be acivaed o urn off he gae unil he 4h cycle of Vcc hiccup is ripped. The UVP delay ime is o preven he false-riggering. As recommended in Fig. 1, only one resisor (R) is required o connec pin in series wih he inducor o deec he inducor signal and proec pin from damage. I makes he circui simple and easy o design wih. Fig. 4 shows he relaed waveforms beween he changing inducor volage and volage. pin is clamped a 5.3V or 0.3V in accordance wih various inducor volages. -DS-00 April

11 UVLO(on) UVLO(off) Vcc 4 imes Hiccup Vcc UVLO(on) UVLO(off) 4 imes Hiccup Inducor Volage Vou LED Shored VRS GND -Vin VRS_PEAK CSSP Level RS Shored CSSP Tripped Upper Clamp UVP Level UVP Tripped OUT CSSP Delay Time CSSP Blacking Time CSSP Delay Time Lower Clamp OUT Swiching VD+VRS UVP Delay Time Non-Swiching Fig. 5 CSSP Blacking Time Over Curren Proecion (OCP) UVP Delay Time Swiching The deecs he MOSFET curren from he CS pin, which is for he pulse-by-pulse curren limi and oupu curren feedback. The maximum volage hreshold of he CS pin is se a 1.0V. From above, he MOSFET peak curren can be obained from below. 1.0V IPEAK (MAX) RS CS Shor Proecion (CSSP) Recovery Auo In order o preven he LED driver from damage due o he shored sense resisor (Rs), CS pin is buil in wih CSSP proecion. See Fig. 6. Once he faul condiion occurs, he CS volage will drop o GND level insananeously and i will enable he proecion wih CSSP delay ime o avoid he false-rigger. When VCC achieves he UVLO(on), he will sar he CSSP blanking ime o ignore CSSP funcion o pass he sar-up ransien. Swiching Swiching Non-Swiching Fig. 6 Over Volage Proecion (VCC OVP) The maximum raing of he VCC pin is limied below 30V. To preven VCC from damage due o faul condiion, he is implemened wih OVP funcion on VCC pin. As soon as he VCC volage is over OVP hreshold volage, he oupu gae drive circui will be shudown simulaneously hus o sop he swiching of he power MOSFET unil he nex UVLO(on) arrives. The VCC OVP funcion of he is an auo-recovery proecion. The Fig. 7 shows is operaion. Upon removal of he OVP condiion will resume he VCC level and he oupu operaion VCC OVP Tripped OVP Level UVLO(on) UVLO(off) OUT Swiching Non-Swiching Swiching Fig. 7 -DS-00 April

12 Oupu Drive Sage An oupu sage of a CMOS buffer, wih ypical 250mA/-500mA driving capabiliy, is incorporaed o drive he power MOSFET direcly. The oupu volage is clamped a 13V o proec he MOSFET gae even when he VCC volage rises over 13V. -DS-00 April

13 Package Informaion SOP-7 Symbols Dimensions in Millimeers Dimensions in Inch MIN MAX MIN MAX A B C D F H I J M θ DS-00 April

14 Package Informaion SOP-8 Symbols Dimensions in Millimeers Dimensions in Inch MIN MAX MIN MAX A B C D F H I J M θ DS-00 April

15 Package Informaion DIP-8 Symbol Dimension in Millimeers Dimensions in Inches Min Max Min Max A B C D E F I J L Imporan Noice Leadrend Technology Corp. reserves he righ o make changes or correcions o is producs a any ime wihou noice. Cusomers should verify he daashees are curren and complee before placing order. -DS-00 April

16 Revision Hisory Rev. Dae Change Noice /04/17 Original Specificaion. -DS-00 April