Implementation of a Timestamping Service for SunSPOT Sensors

Size: px
Start display at page:

Download "Implementation of a Timestamping Service for SunSPOT Sensors"

Transcription

1 Available olie at Procedia Techology 7 ( 2013 ) 4 10 The 2013 Iberoamerica Coferece o Electroics Egieerig ad Computer Sciece Implemetatio of a Timestampig Service for SuSPOT Sesors Jua A García Reyes a, Roberto Solís Robles a *, Blaca E Solís Recédez a, José G Arceo Olague a a Uiversidad Autóoma de Zacatecas, Ave. Ramó López Velarde 801, Zacatecas, 98000, México Abstract Recet techological advaces have eabled the developmet of sesig platforms that iclude differet types of sesors, ad itegrate several compoets such as memory, processor, ad radio. Time sychroizatio is a critical service for a wide rage of applicatios i wireless sesor etworks. Through this service, the sesors i the etwork are able to coordiate ad carry out sesig processes i a way that permits the correct orderig of the global evets, ad save eergy. The protocols that provide better accuracy rely o a timestampig mechaism which allows them to elimiate several sources of error i the time sychroizatio process. However, i ewer platforms, such as SuSPOT, o timestampig mechaism is provided. I this paper, we preset a implemetatio of a microsecod accuracy timestampig service i the SuSPOT platform, which provides the foudatio for the implemetatio of accurate time sychroizatio protocols i a wireless SuSPOT sesor etwork The 2012 Authors. Published Published by Elsevier by Elsevier Ltd. Ltd. Selectio Ope access ad/or uder peer-review CC BY-NC-ND uder resposibility licese. of Global Sciece ad Selectio Techology ad peer-review Forum uder Pte resposibility Ltd of CIIECC 2013 Keywords: Wireless, Sesor, Network, Time Sychroizatio, Protocol 1. Itroductio Recet techological advaces have eabled the developmet of sesig platforms that iclude differet types of sesors, ad itegrate several compoets such as memory, processor, ad radio. A wireless sesor etwork cosists of two or more of these devices that commuicate wirelessly i short distaces usig geerally a low power cosumptio protocol. These sesor etworks are ideal for applicatios such as atural habitat ad ifrastructure moitorig, data acquisitio i iaccessible areas, etc. [1, 2] Time sychroizatio is a critical service for a wide rage of applicatios i wireless sesor etworks. Through this service, the sesors i the etwork are able to coordiate ad carry out sesig processes i a way that permits the correct orderig of the global evets, ad save eergy. Several algorithms have bee proposed to provide this time sychroizatio service [3, 4, 5, 6, 7, 8]. Although a few of them have bee implemeted i wireless sesors platforms such as MICAz or * Correspodig author. Tel.: Ext addresses: garciar.ja@gmail.com, rsolis@uaz.edu.mx, bsolre@yahoo.com.mx, arceoljg@yahoo.com.mx The Authors. Published by Elsevier Ltd. Ope access uder CC BY-NC-ND licese. Selectio ad peer-review uder resposibility of CIIECC 2013 doi: /j.protcy

2 Jua A. García Reyes et al. / Procedia Techology 7 ( 2013 ) TelosB [9], the eed for a better performace, ad the appearace of better hardware features such as faster processors or more available memory, make it essetial to use ewer devices such as the SuSPOT [10]. The SuSPOT platform is programmed usig Java, which meas, that as i all devices that use Java, it has a Java Virtual Machie (JVM) that i this case acts as operatig system. The SuSPOT platform icorporates the Java 2 Micro Editio (J2ME) ad the Coected Limited Device Cofiguratio (CLDC) 1.1. Several APIs are provided for the platform, which allow the easy developmet of applicatios to be ru i the SuSPOT. However, there is o API available to provide a timestampig service at the MAC (Medium Access Cotrol) level, which is ecessary for several of the time sychroizatio protocols that have bee proposed, such as FTSP [6] or DMTSP [8]. Give the eed we have to use a time sychroizatio protocol that requires the existece of this kid of timestampig mechaism, we decided to implemet the timestampig service. This paper presets the issues ecoutered i the developmet of a software module to provide a timestampig service with a microsecod precisio ad which is trasparet to the user. The module is tested usig the Floodig Time Sychroizatio Protocol [6], maybe the more widespread sychroizatio protocol give its capability to support etwork scalability ad chages i the etwork topology as well as its simplicity, low overhead, fault tolerace ad low average sychroizatio error. 2. Related Work As already metioed, several time sychroizatio protocols have bee proposed, but two of them stad out sice they provide a better accuracy that the rest. This is due to their use of a MAC layer timestampig mechaism. This timestampig mechaism allows a protocol to elimiate several sources of error i the time sychroizatio process, ad therefore provide better sychroizatio accuracy. The first protocol that uses a MAC timestampig mechaism is FTSP, Floodig Time Sychroizatio Protocol ad its details ca be foud i [6], where we ca also fid the results obtaied for its implemetatio i the MICA2, which is a obsolete sesor platform. The protocol was tested i a 60-ode multihop etwork, with a maximum of 6 hops betwee ay ode ad the root ode. The average sychroizatio error obtaied was 16 microsecods. The secod protocol that uses the MAC timestampig mechaism is DMTSP, Distributed Multihop Time Sychroizatio Protocol [8], which also works i a multihop eviromet, but does ot eed to establish a topology before the sychroizatio ca take place. It was also implemeted i the MICA2 platform, ad the average sychroizatio error was 20 microsecods for a 9-hop etwork. As metioed, both of these protocols sychroize a etwork of odes usig sychroizatio messages which are timestamped at trasmissio ad at receptio. Although these timestamps elimiate some sources of error, there is a eed to compesate for the drift i the odes clocks. This drift is caused because the quartz crystals that feed the timers geerate light frequecy chages which i the log term accumulate. Therefore, a liear regressio ca be performed to estimate the value of the global time. This liear regressio is performed i each ode to estimate its skew ad offset with respect to the global clock i a give time. It is worth metioig that ulike i other platforms where there is a wide rage of documetatio regardig the features of the operatig systems they use, such as TiyOS [11]; for the SuSPOT there is practically o documetatio available for several of the features, icludig the way the MAC layer is programmed. We could oly fid a icomplete report regardig the implemetatio of a microsecod clock [12] ad a couple of otes o the cofiguratio of the timers [13, 14], which we use as a departure poit for our implemetatio. 3. System Descriptio Time sychroizatio usig FTSP ivolves three mai stages, which are treated as idepedet software modules i this implemetatio, ad are later liked together to form a complete time sychroizatio system. The modular divisio simplifies its implemetatio give the features of the object orieted programmig laguage used (Java) ad the properties of the protocol. It also provides a easier way to measure the sychroizatio errors itroduced i each stage ad compare such errors with the oes obtaied i other implemetatios. Each module offers its services to other layers. The aforemetioed stages are: 1. Timestampig. This module iteracts with the lower protocol layers. It specifies the time sychroizatio packet ad offers a iterface to allow the other modules to sed ad receive sychroizatio messages. It also provides a MAC layer timestamp whe a packet is received or trasmitted, ad i the case of trasmissio, it puts the timestamp i the packet that is beig set.

3 6 Jua A. García Reyes et al. / Procedia Techology 7 ( 2013 ) Clock drift maagemet. This module maages the liear regressio table, formed by the sychroizatio poits (global time, local time) ad used to calculate the offset ad skew required to estimate the global time. 3. Multihop etwork sychroizatio. This module decides which ode will act as the root, what will be doe i case of ode failures ad aalyzes the data obtaied from the sychroizatio messages received, filterig every message that does ot meet the protocol criteria ad stores every valid message i the liear regressio table. Fially, each module offers its services at some stage of the sychroizatio process (e.g., receptio or trasmissio) ad otifies its state to other modules if ecessary. Fig. 1 shows how each module, from the receptio to the trasmissio of a message, takes part i the time sychroizatio process i a multihop etwork. Fig. 1. Model for the time sychroizatio process i a multihop etwork usig FTSP 4. Implemetatio Details 4.1. SuSPOT The SuSPOT devices developed by Oracle Labs [10] icorporate a hardware module with light, ad temperature sesors, a 3D accelerometer, a A/D coverter ad a data acquisitio board that allows the iput ad output of sigals from/to exteral devices. It has a 400MHz processor, with 1MB RAM, 8MB of flash memory ad a IEEE radio which trasmits i the 2.4GHz bad to provide wireless commuicatios with a 80 meter rage. A rechargeable 3.7 V, 770mAh lithium-io battery is used as eergy supply, which lasts up to 909 days i deep sleep state [15]. With the objective of obtaiig a microsecod precisio i the sychroizatio achieved, we require a microsecod precisio clock. However, the available API oly provides millisecod accuracy through the use of System.curretMillis(). Therefore we eed to cofigure a clock to achieve the microsecod precisio required. The hardware module i the SuSPOT icorporates two timers, each with three chaels that ca be cofigured programmatically to implemet a clock capable of updatig its local time with a microsecod precisio. I the ext subsectio we will discuss how this is doe. To be able to provide a MAC layer timestampig service, we ca wire the SFD pi from the CC2420 radio i the SuSPOT with the timer i the microprocessor ad capture the pulse geerated from the SFD pi [16] Logical Clock Cofiguratio The hardware module i the SuSPOT s microprocessor icorporates two AT91 timers. Each of these timers icludes three idetical chaels, each with a 16-bits couter. Two of these chaels are reserved for the system ad oly four are available for applicatio use. A chael ca operate i two differet modes: capture mode ad sigal geerator mode [13]. The basic idea, as show i Fig. 2, is to cofigure oe of these chaels, say Chael 0, as a pulse geerator at a 1 MHz frequecy, ad coect this chael to aother oe, say Chael 1, eabled i capture mode. This way, the geerator i Chael 0 will sed the couter i Chael 1 a pulse every microsecod, ad the Chael 1 couter will icremet the value i its register util it reaches its maximum value. Oce this maximum value is reached a 64-bit variable will be updated by addig to it the maximum value. By havig this 64-bit variable we ca keep a much larger clock cout that the oe kept with the 16-bit couter i the timer.

4 Jua A. García Reyes et al. / Procedia Techology 7 ( 2013 ) Fig. 2. Block diagram of the timer cofiguratio used to costruct a logical clock with microsecod precisio. With the help of the iformatio obtaied from [13] ad [14] we were able to cofigure the clock. First we describe the particular cofiguratio for chael 0 i our pulse geerator. This chael has three importat registers for our implemetatio: the first oe is the couter value (TC_CV) register which is a 16-bit register which icremets its value with each positive trasitio from the selected clock iput, ad the other two (TC_RA ad TC_RC) are used as compariso registers. I order to obtai a higher precisio we feed this chael with the MCK/2 sigal (Master Clock divided by 2) which is the fastest available speed i the processor board with a MHz frequecy. Usig this frequecy, the couter i the 16-bit register TC_CV icremets its value approximately every 15 aosecods. Whe the value of the couter reaches the value set i the 16-bit register TC_RA, the output i the multipurpose iput/output TIOA0 pi chages to iactive. Whe the value of the couter reaches the value set i the 16-bit register TC_RC, the output i the TIOA pi chages to active. This way, the geerated pulse will be equal to TC_RC -TC_RA. To cofigure the sigal geeratio to be active every 1 microsecod, we eed to set the value of the registers as follows: TC_RA =22 ad TC_RC=67. Chael 1 is cofigured i capture mode. This chael allows us to update the local time periodically. The logic i this timer is similar to the oe described for chael 0, the icomig sigal i TCLK1 that comes from the pulse geerator icremets the value of TC_CV. If we cofigure the iterrupt i a correct way, whe the couter reaches its maximum value, a TC_COVFS iterrupt is geerated, the global variable used to keep the time is updated ad TC_CV is reset to zero. Sice TC_CV is 16 bit log, its maximum value is 0xFFFF, ad therefore the value is added to the global variable. To get the local curret time, we access the TC_CV register ad add it to the value i the global variable. I our implemetatio, a iterface was added to the API so a applicatio ca make use of the method getcurrettime(), which performs the steps we just describe to obtai the curret local time Timestampig Accordig to the FTSP protocol descriptio, whe a sychroizatio message is set, the trasmittig ode timestamps the message beig set. Also, whe the receivig ode receives a message it geerates a receptio timestamp. This two timestamps form a sychroizatio data poit that allows the calculatio of a skew ad a offset with respect to the global time (which for the basic setup betwee oly two odes, would be the time at the seder). I the implemetatio of FTSP uder TiyOS i the Mica2 platform, the messages were timestamped multiple times to provide a better sychroizatio. Ufortuately, i the CC2420 radio trasceiver of the SuSPOT, we caot perform this multiple timestampig. This limits the precisio i our implemetatio, give that the use of multiple timestamps allows a 90% reductio i the sychroizatio error betwee two odes, accordig to the descriptio foud i [6].

5 8 Jua A. García Reyes et al. / Procedia Techology 7 ( 2013 ) 4 10 Fig. 3. State of the SFD pi i the CC2420 radio trasceiver at trasmissio ad receptio [16] I our implemetatio, the messages are timestamped oly oce, by detectig the Start of Frame Delimiter (SFD), which idicates the begiig of the trasmissio (or receptio) of a message, as show i Fig. 3. I trasmissio mode, oce the SFD is detected the trasmissio of the iformatio (packet) cotaied i the TXFIFO buffer foud i the CC2420 radio chip has begu, ad therefore we eed to obtai the local clock described i Sectio 4.2 to place it i the packet beig set as soo as possible. Curretly, the APIs icluded i the SuSPOT Developmet kit v6.0 allow us to register our ow protocols easily by usig the ILowPa iterface. Through this registratio, a user ca establish a 8-bit umber which acts as a idetifier for the protocol i the otificatios set to the upper layers whe packets are received. The structure ad format of the packet used i the time sychroizatio protocol is show i Fig 4. We ca observe that the timestamp is to be placed at the last possible positio so we have time to obtai the curret local clock ad place it i the packet before the packet is completely set. Fig. 4. Time sychroizatio packet format i the layers, based o [17] I receptio mode, the SFD is detected oce the Start of Frame Delimiter field has bee stored i the RXFIFO buffer i the CC2420 radio chip, ad the value of the local clock is obtaied as a result of this detectio Clock Drift Maagemet As i [8], we assume that the behavior of a clock through time follows the liear form: T i = t+o where T i is the local time, ad O are respectively the relative speed of the clock (skew) ad the offset with respect to some other ode, ad t is the real time. The liear regressio method is used so each ode i the etwork is able to estimate the global time (e.g., the time at some root ode). With two or more sychroizatio poits (each formed by the trasmissio ad receptio time of a give message), the global time (G) ca be estimated usig liear regressio i the followig way: G= L+O, where L is the local time ad both ad O are calculated as follows: i 1 i 1 RT i R i 2 i R T i i i 1 i 1 2 Ri i 1 O T T ad R are the average trasmissio ad receptio timestamps respectively, ad is the umber of sychroizatio poits cotaied i the liear regressio table. For our implemetatio, the clock drift maagemet software module maitais the liear regressio table with a maximum capacity of 15 sychroizatio poits but ad O are calculated oce five sychroizatio poits are available. Oce these calculatios are made, the software module otifies the module that updates the local time so it has the iformatio required to estimate the global time. I this way, ay class ca obtai the global time at ay time. R

6 Jua A. García Reyes et al. / Procedia Techology 7 ( 2013 ) Results Oce we fiished our implemetatio of the timestampig service, we implemeted FTSP for a two-ode sychroizatio havig oe of the odes sed a sychroizatio message every 15 secods. Oce the receivig ode has received five sychroizatio messages, as metioed before, it is able to estimate the skew ad offset with respect to the trasmittig ode usig liear regressio. For each message received we obtaied the curret local time at receptio ad based o the trasmissio timestamp icluded i each message ad the skew ad offset estimated, we observe a sychroizatio error of 45 microsecods. The sychroizatio error is larger tha the oe obtaied by the TiyOS implemetatio of FTSP [6] because we were ot able to timestamp a message multiple times at trasmissio ad receptio, ad because the Garbage Collectio service at the Java Virtual Machie (JVM) of the SuSPOT geerates delays for the iterrupt hadlers. Nevertheless, the sychroizatio is ow much fier that the oe provided by the APIs i the SuSPOT which is i the order of millisecods. Fig. 5. Average sychroizatio error obtaied whe sychroizatio messages are set every 15 secods. 6. Coclusios I this paper we have preseted a implemetatio of a timestampig service with microsecod precisio for the SuSPOT sesor platform, which is required for the use of time sychroizatio protocols such as FTSP or DMTSP. Although the sychroizatio error we have obtaied i this implemetatio is larger tha the oe obtaied with other platforms, it provides a much better precisio that the oe provided by the APIs icluded i the SuSPOT platform. The ext step is to try ad reduce the sychroizatio error by lookig ito ways to elimiate the egative impact the JVM s garbage collectio ad thread maagemet create i the iterrupt hadlers. Further experimetatio is also required to verify that the covergece ad fault tolerace properties that FTSP [6] exhibits i the previously existig implemetatios are also preset i our implemetatio whe ode failures are ijected. Refereces [1] Sudararama B, Buy U, Kshemkalyai AD. Clock sychroizatio for wireless sesor etworks: a survey. Ad Hoc Networks, 2005, Vol. 3, p [2] Va Voorst B. Time sychroizatio i wireless sesor etworks. 4th Twete Studet Coferece o IT Available olie: &rep=rep1&type=pdf [3] Elso J, Girod L, Estri D. Fie-graied etwork time sychroizatio usig referece broadcasts. Proceedigs of the 5th ACM Symposium o Operatig System Desig ad Implemetatio (OSDI-02), 2002, p [4] Sichitiu M, Veerarittipha C. Simple, accurate time sychroizatio for wireless sesor etworks. Proceedigs of the IEEE Wireless Commuicatios ad Networkig Coferece (WCNC), p.16. [5] Gaeriwal S, Kumar R, Srivastava MB. Timig-syc protocol for sesor etworks. Proceedigs of the first iteratioal coferece o Embedded etworked sesor systems (SeSys-03), 2003, p.138. [6] Maroti M, Simo G, Kusy B, Ledeczi A. The floodig time sychroizatio protocol. Proceedigs of the 2d iteratioal coferece o Embedded etworked sesor systems, 2004, p. 39. [7] Shahzad K, Ali A, Gohar ND, ETSP: A eergy-efficiet time sychroizatio protocol for wireless sesor etworks. Proceedigs of the 22 th Advaced Iformatio Networkig ad Applicatios - Workshop, p [8] Solis R, Borkar VS, Kumar PR. A New Distributed Time Sychroizatio Protocol for Multihop Wireless Networks. Proceedigs of the 45th IEEE Coferece o Decisio ad Cotrol, 2006, p [9] MEMSIC, Ic, Wireless Modules. Available olie: html. [10] Su Labs, Project SuSPOT, Available olie: [11] Levis P, Gay D. TiyOS Programmig. New York: Cambridge Uiversity Press, 2009.

7 10 Jua A. García Reyes et al. / Procedia Techology 7 ( 2013 ) 4 10 [12] Sycspot - Google Code, Time Sychroizatio o SuSPOT. Available olie: [13] Atmel. AT91SAM9G20 ARM Datasheet, Available olie: [14] Ro Goldma. Usig the AT91 Timer/Couter, 2010, A SuSPOT Applicatio Note. Available olie: /TimerCouterAppNote.pdf [15] Su Labs, SuSPOT Mai Board Techical Datasheet Rev 8.0, 2010, Available olie: html. [16] Chipco. CC2420 Datasheet, Available olie: [17] IEEE Computer Society. Wireless Medium Access Cotrol (MAC) ad Physical Layer (PHY) specificatios for Low Rate Wireless Persoal Area Networks (LR-WPANs), 2003, Available olie:

Adaptive Resource Allocation for Electric Environmental Pollution through the Control Network

Adaptive Resource Allocation for Electric Environmental Pollution through the Control Network Available olie at www.sciecedirect.com Eergy Procedia 6 (202) 60 64 202 Iteratioal Coferece o Future Eergy, Eviromet, ad Materials Adaptive Resource Allocatio for Electric Evirometal Pollutio through the

More information

3D Model Retrieval Method Based on Sample Prediction

3D Model Retrieval Method Based on Sample Prediction 20 Iteratioal Coferece o Computer Commuicatio ad Maagemet Proc.of CSIT vol.5 (20) (20) IACSIT Press, Sigapore 3D Model Retrieval Method Based o Sample Predictio Qigche Zhag, Ya Tag* School of Computer

More information

Improvement of the Orthogonal Code Convolution Capabilities Using FPGA Implementation

Improvement of the Orthogonal Code Convolution Capabilities Using FPGA Implementation Improvemet of the Orthogoal Code Covolutio Capabilities Usig FPGA Implemetatio Naima Kaabouch, Member, IEEE, Apara Dhirde, Member, IEEE, Saleh Faruque, Member, IEEE Departmet of Electrical Egieerig, Uiversity

More information

CMSC Computer Architecture Lecture 12: Virtual Memory. Prof. Yanjing Li University of Chicago

CMSC Computer Architecture Lecture 12: Virtual Memory. Prof. Yanjing Li University of Chicago CMSC 22200 Computer Architecture Lecture 12: Virtual Memory Prof. Yajig Li Uiversity of Chicago A System with Physical Memory Oly Examples: most Cray machies early PCs Memory early all embedded systems

More information

K-NET bus. When several turrets are connected to the K-Bus, the structure of the system is as showns

K-NET bus. When several turrets are connected to the K-Bus, the structure of the system is as showns K-NET bus The K-Net bus is based o the SPI bus but it allows to addressig may differet turrets like the I 2 C bus. The K-Net is 6 a wires bus (4 for SPI wires ad 2 additioal wires for request ad ackowledge

More information

Morgan Kaufmann Publishers 26 February, COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface. Chapter 5.

Morgan Kaufmann Publishers 26 February, COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface. Chapter 5. Morga Kaufma Publishers 26 February, 208 COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Iterface 5 th Editio Chapter 5 Virtual Memory Review: The Memory Hierarchy Take advatage of the priciple

More information

A SOFTWARE MODEL FOR THE MULTILAYER PERCEPTRON

A SOFTWARE MODEL FOR THE MULTILAYER PERCEPTRON A SOFTWARE MODEL FOR THE MULTILAYER PERCEPTRON Roberto Lopez ad Eugeio Oñate Iteratioal Ceter for Numerical Methods i Egieerig (CIMNE) Edificio C1, Gra Capitá s/, 08034 Barceloa, Spai ABSTRACT I this work

More information

Lecture 28: Data Link Layer

Lecture 28: Data Link Layer Automatic Repeat Request (ARQ) 2. Go ack N ARQ Although the Stop ad Wait ARQ is very simple, you ca easily show that it has very the low efficiecy. The low efficiecy comes from the fact that the trasmittig

More information

CSC 220: Computer Organization Unit 11 Basic Computer Organization and Design

CSC 220: Computer Organization Unit 11 Basic Computer Organization and Design College of Computer ad Iformatio Scieces Departmet of Computer Sciece CSC 220: Computer Orgaizatio Uit 11 Basic Computer Orgaizatio ad Desig 1 For the rest of the semester, we ll focus o computer architecture:

More information

Data diverse software fault tolerance techniques

Data diverse software fault tolerance techniques Data diverse software fault tolerace techiques Complemets desig diversity by compesatig for desig diversity s s limitatios Ivolves obtaiig a related set of poits i the program data space, executig the

More information

CAEN Tools for Discovery

CAEN Tools for Discovery Applicatio Note AN2086 Sychroizatio of CAEN Digitizers i Multiple Board Acquisitio Systems Viareggio 9 May 2013 Itroductio High speed digitizers fid applicatios i several fields ragig from the idustry

More information

Software development of components for complex signal analysis on the example of adaptive recursive estimation methods.

Software development of components for complex signal analysis on the example of adaptive recursive estimation methods. Software developmet of compoets for complex sigal aalysis o the example of adaptive recursive estimatio methods. SIMON BOYMANN, RALPH MASCHOTTA, SILKE LEHMANN, DUNJA STEUER Istitute of Biomedical Egieerig

More information

Politecnico di Milano Advanced Network Technologies Laboratory. Internet of Things. Projects

Politecnico di Milano Advanced Network Technologies Laboratory. Internet of Things. Projects Politecico di Milao Advaced Network Techologies Laboratory Iteret of Thigs Projects 2016-2017 Politecico di Milao Advaced Network Techologies Laboratory Geeral Rules Geeral Rules o Gradig 26/30 are assiged

More information

A QoS Provisioning mechanism of Real-time Wireless USB Transfers for Smart HDTV Multimedia Services

A QoS Provisioning mechanism of Real-time Wireless USB Transfers for Smart HDTV Multimedia Services A QoS Provisioig mechaism of Real-time Wireless USB Trasfers for Smart HDTV Multimedia Services Ji-Woo im 1, yeog Hur 2, Jog-Geu Jeog 3, Dog Hoo Lee 4, Moo Sog Yeu 5, Yeowoo Lee 6 ad Seog Ro Lee 7 1 Istitute

More information

TELETERM M2 Series Programmable RTU s

TELETERM M2 Series Programmable RTU s Model C6xC ad C6xC Teleterm MR Radio RTU s DATASHEET Cofigurable Iputs ad Outputs 868MHz or 900MHz radio port 0/00 Etheret port o C6Cx ISaGRAF 6 Programmable microsd Card Loggig Low power operatio Two

More information

UNIVERSITY OF MORATUWA

UNIVERSITY OF MORATUWA UNIVERSITY OF MORATUWA FACULTY OF ENGINEERING DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING B.Sc. Egieerig 2014 Itake Semester 2 Examiatio CS2052 COMPUTER ARCHITECTURE Time allowed: 2 Hours Jauary 2016

More information

Chapter 1. Introduction to Computers and C++ Programming. Copyright 2015 Pearson Education, Ltd.. All rights reserved.

Chapter 1. Introduction to Computers and C++ Programming. Copyright 2015 Pearson Education, Ltd.. All rights reserved. Chapter 1 Itroductio to Computers ad C++ Programmig Copyright 2015 Pearso Educatio, Ltd.. All rights reserved. Overview 1.1 Computer Systems 1.2 Programmig ad Problem Solvig 1.3 Itroductio to C++ 1.4 Testig

More information

Chapter 4 Threads. Operating Systems: Internals and Design Principles. Ninth Edition By William Stallings

Chapter 4 Threads. Operating Systems: Internals and Design Principles. Ninth Edition By William Stallings Operatig Systems: Iterals ad Desig Priciples Chapter 4 Threads Nith Editio By William Stalligs Processes ad Threads Resource Owership Process icludes a virtual address space to hold the process image The

More information

Elementary Educational Computer

Elementary Educational Computer Chapter 5 Elemetary Educatioal Computer. Geeral structure of the Elemetary Educatioal Computer (EEC) The EEC coforms to the 5 uits structure defied by vo Neuma's model (.) All uits are preseted i a simplified

More information

Lecture Notes 6 Introduction to algorithm analysis CSS 501 Data Structures and Object-Oriented Programming

Lecture Notes 6 Introduction to algorithm analysis CSS 501 Data Structures and Object-Oriented Programming Lecture Notes 6 Itroductio to algorithm aalysis CSS 501 Data Structures ad Object-Orieted Programmig Readig for this lecture: Carrao, Chapter 10 To be covered i this lecture: Itroductio to algorithm aalysis

More information

Evaluation scheme for Tracking in AMI

Evaluation scheme for Tracking in AMI A M I C o m m u i c a t i o A U G M E N T E D M U L T I - P A R T Y I N T E R A C T I O N http://www.amiproject.org/ Evaluatio scheme for Trackig i AMI S. Schreiber a D. Gatica-Perez b AMI WP4 Trackig:

More information

Definitions. Error. A wrong decision made during software development

Definitions. Error. A wrong decision made during software development Debuggig Defiitios Error A wrog decisio made durig software developmet Defiitios 2 Error A wrog decisio made durig software developmet Defect bug sometimes meas this The term Fault is also used Property

More information

TELETERM M2 Series Programmable RTU s

TELETERM M2 Series Programmable RTU s DATASHEET Cofigurable Iputs ad Outputs 868, 900 or 58MHz radio port operatig i licesefree bads 0/00 Etheret port o C6Cx ISaGRAF 6 Programmable microsd Card Loggig Low power operatio Two serial ports (icl.

More information

Ontology-based Decision Support System with Analytic Hierarchy Process for Tour Package Selection

Ontology-based Decision Support System with Analytic Hierarchy Process for Tour Package Selection 2017 Asia-Pacific Egieerig ad Techology Coferece (APETC 2017) ISBN: 978-1-60595-443-1 Otology-based Decisio Support System with Aalytic Hierarchy Process for Tour Pacage Selectio Tie-We Sug, Chia-Jug Lee,

More information

Multi-Threading. Hyper-, Multi-, and Simultaneous Thread Execution

Multi-Threading. Hyper-, Multi-, and Simultaneous Thread Execution Multi-Threadig Hyper-, Multi-, ad Simultaeous Thread Executio 1 Performace To Date Icreasig processor performace Pipeliig. Brach predictio. Super-scalar executio. Out-of-order executio. Caches. Hyper-Threadig

More information

MOTIF XF Extension Owner s Manual

MOTIF XF Extension Owner s Manual MOTIF XF Extesio Ower s Maual Table of Cotets About MOTIF XF Extesio...2 What Extesio ca do...2 Auto settig of Audio Driver... 2 Auto settigs of Remote Device... 2 Project templates with Iput/ Output Bus

More information

IS-IS in Detail. ISP Workshops

IS-IS in Detail. ISP Workshops IS-IS i Detail ISP Workshops These materials are licesed uder the Creative Commos Attributio-NoCommercial 4.0 Iteratioal licese (http://creativecommos.org/liceses/by-c/4.0/) Last updated 27 th November

More information

Security of Bluetooth: An overview of Bluetooth Security

Security of Bluetooth: An overview of Bluetooth Security Versio 2 Security of Bluetooth: A overview of Bluetooth Security Marjaaa Träskbäck Departmet of Electrical ad Commuicatios Egieerig mtraskba@cc.hut.fi 52655H ABSTRACT The purpose of this paper is to give

More information

JavaFX. JavaFX 2.2 Installation Guide Release 2.2 E August 2012 Installation instructions by operating system for JavaFX 2.

JavaFX. JavaFX 2.2 Installation Guide Release 2.2 E August 2012 Installation instructions by operating system for JavaFX 2. JavaFX JavaFX 2.2 Istallatio Guide Release 2.2 E20474-06 August 2012 Istallatio istructios by operatig system for JavaFX 2.2 JavaFX/JavaFX 2.2 Istallatio Guide E20474-06 Copyright 2008, 2012, Oracle ad/or

More information

. Written in factored form it is easy to see that the roots are 2, 2, i,

. Written in factored form it is easy to see that the roots are 2, 2, i, CMPS A Itroductio to Programmig Programmig Assigmet 4 I this assigmet you will write a java program that determies the real roots of a polyomial that lie withi a specified rage. Recall that the roots (or

More information

Security and Communication. Ultimate. Because Intercom doesn t stop at the hardware level. Software Intercom Server for virtualised IT platforms

Security and Communication. Ultimate. Because Intercom doesn t stop at the hardware level. Software Intercom Server for virtualised IT platforms Because Itercom does t stop at the hardware level by Commed Software Itercom Server for virtualised IT platforms Ready for VMware Ready for Hyper-V VoIP Ultimate availability Itercom Server as a app The

More information

Empirical Validate C&K Suite for Predict Fault-Proneness of Object-Oriented Classes Developed Using Fuzzy Logic.

Empirical Validate C&K Suite for Predict Fault-Proneness of Object-Oriented Classes Developed Using Fuzzy Logic. Empirical Validate C&K Suite for Predict Fault-Proeess of Object-Orieted Classes Developed Usig Fuzzy Logic. Mohammad Amro 1, Moataz Ahmed 1, Kaaa Faisal 2 1 Iformatio ad Computer Sciece Departmet, Kig

More information

BOOLEAN DIFFERENTIATION EQUATIONS APPLICABLE IN RECONFIGURABLE COMPUTATIONAL MEDIUM

BOOLEAN DIFFERENTIATION EQUATIONS APPLICABLE IN RECONFIGURABLE COMPUTATIONAL MEDIUM MATEC Web of Cofereces 79, 01014 (016) DOI: 10.1051/ mateccof/0167901014 T 016 BOOLEAN DIFFERENTIATION EQUATIONS APPLICABLE IN RECONFIGURABLE COMPUTATIONAL MEDIUM Staislav Shidlovskiy 1, 1 Natioal Research

More information

Introduction to OSPF. ISP Training Workshops

Introduction to OSPF. ISP Training Workshops Itroductio to OSPF ISP Traiig Workshops 1 OSPF p Ope Shortest Path First p Lik state or SPF techology p Developed by OSPF workig group of IETF (RFC 1247) p OSPFv2 stadard described i RFC2328 p Desiged

More information

Course Site: Copyright 2012, Elsevier Inc. All rights reserved.

Course Site:   Copyright 2012, Elsevier Inc. All rights reserved. Course Site: http://cc.sjtu.edu.c/g2s/site/aca.html 1 Computer Architecture A Quatitative Approach, Fifth Editio Chapter 2 Memory Hierarchy Desig 2 Outlie Memory Hierarchy Cache Desig Basic Cache Optimizatios

More information

Prevention of Black Hole Attack in Mobile Ad-hoc Networks using MN-ID Broadcasting

Prevention of Black Hole Attack in Mobile Ad-hoc Networks using MN-ID Broadcasting Vol.2, Issue.3, May-Jue 2012 pp-1017-1021 ISSN: 2249-6645 Prevetio of Black Hole Attack i Mobile Ad-hoc Networks usig MN-ID Broadcastig Atoy Devassy 1, K. Jayathi 2 *(PG scholar, ME commuicatio Systems,

More information

Using the Keyboard. Using the Wireless Keyboard. > Using the Keyboard

Using the Keyboard. Using the Wireless Keyboard. > Using the Keyboard 1 A wireless keyboard is supplied with your computer. The wireless keyboard uses a stadard key arragemet with additioal keys that perform specific fuctios. Usig the Wireless Keyboard Two AA alkalie batteries

More information

APPLICATION NOTE. Automated Gain Flattening. 1. Experimental Setup. Scope and Overview

APPLICATION NOTE. Automated Gain Flattening. 1. Experimental Setup. Scope and Overview APPLICATION NOTE Automated Gai Flatteig Scope ad Overview A flat optical power spectrum is essetial for optical telecommuicatio sigals. This stems from a eed to balace the chael powers across large distaces.

More information

SCI Reflective Memory

SCI Reflective Memory Embedded SCI Solutios SCI Reflective Memory (Experimetal) Atle Vesterkjær Dolphi Itercoect Solutios AS Olaf Helsets vei 6, N-0621 Oslo, Norway Phoe: (47) 23 16 71 42 Fax: (47) 23 16 71 80 Mail: atleve@dolphiics.o

More information

SERIAL COMMUNICATION INTERFACE FOR ESA ESTRO

SERIAL COMMUNICATION INTERFACE FOR ESA ESTRO Bulleti E708 rev0 7/06/0 SERIAL COMMUNICATION INTERFACE FOR - SERIES FEATURES Supply voltage: 90 40vac Supply frequecy: 40 70 Hz Max. absorbtio: 40W Operatig temperature: 0 50 C Storage temperature: -0

More information

An Algorithm of Mobile Robot Node Location Based on Wireless Sensor Network

An Algorithm of Mobile Robot Node Location Based on Wireless Sensor Network A Algorithm of Mobile Robot Node Locatio Based o Wireless Sesor Network https://doi.org/0.399/ijoe.v3i05.7044 Peg A Nigbo Uiversity of Techology, Zhejiag, Chia eirxvrp2269@26.com Abstract I the wireless

More information

Introduction to Wireless & Mobile Systems. Chapter 6. Multiple Radio Access Cengage Learning Engineering. All Rights Reserved.

Introduction to Wireless & Mobile Systems. Chapter 6. Multiple Radio Access Cengage Learning Engineering. All Rights Reserved. Itroductio to Wireless & Mobile Systems Chapter 6 Multiple Radio Access 1 Outlie Itroductio Multiple Radio Access Protocols Cotetio-based Protocols Pure ALOHA Slotted ALOHA CSMA (Carrier Sese Multiple

More information

Avid Interplay Bundle

Avid Interplay Bundle Avid Iterplay Budle Versio 2.5 Cofigurator ReadMe Overview This documet provides a overview of Iterplay Budle v2.5 ad describes how to ru the Iterplay Budle cofiguratio tool. Iterplay Budle v2.5 refers

More information

Parallel Polygon Approximation Algorithm Targeted at Reconfigurable Multi-Ring Hardware

Parallel Polygon Approximation Algorithm Targeted at Reconfigurable Multi-Ring Hardware Parallel Polygo Approximatio Algorithm Targeted at Recofigurable Multi-Rig Hardware M. Arif Wai* ad Hamid R. Arabia** *Califoria State Uiversity Bakersfield, Califoria, USA **Uiversity of Georgia, Georgia,

More information

Lower Bounds for Sorting

Lower Bounds for Sorting Liear Sortig Topics Covered: Lower Bouds for Sortig Coutig Sort Radix Sort Bucket Sort Lower Bouds for Sortig Compariso vs. o-compariso sortig Decisio tree model Worst case lower boud Compariso Sortig

More information

SRx. HD/SD Dual Input Diversity COFDM Receiver. Features. Options

SRx. HD/SD Dual Input Diversity COFDM Receiver. Features. Options HD/SD Dual Iput Diversity COFDM Receiver Features Dual iput maximum ratio combiig diversity receiver Umatched adjacet chael performace Superior broadcast grade video MPEG4 Part-10/H.264 2 moo audio chaels

More information

Python Programming: An Introduction to Computer Science

Python Programming: An Introduction to Computer Science Pytho Programmig: A Itroductio to Computer Sciece Chapter 1 Computers ad Programs 1 Objectives To uderstad the respective roles of hardware ad software i a computig system. To lear what computer scietists

More information

Morgan Kaufmann Publishers 26 February, COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface. Chapter 5

Morgan Kaufmann Publishers 26 February, COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface. Chapter 5 Morga Kaufma Publishers 26 February, 28 COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Iterface 5 th Editio Chapter 5 Set-Associative Cache Architecture Performace Summary Whe CPU performace icreases:

More information

WYSE Academic Challenge Sectional Computer Science 2005 SOLUTION SET

WYSE Academic Challenge Sectional Computer Science 2005 SOLUTION SET WYSE Academic Challege Sectioal Computer Sciece 2005 SOLUTION SET 1. Correct aswer: a. Hz = cycle / secod. CPI = 2, therefore, CPI*I = 2 * 28 X 10 8 istructios = 56 X 10 8 cycles. The clock rate is 56

More information

1. SWITCHING FUNDAMENTALS

1. SWITCHING FUNDAMENTALS . SWITCING FUNDMENTLS Switchig is the provisio of a o-demad coectio betwee two ed poits. Two distict switchig techiques are employed i commuicatio etwors-- circuit switchig ad pacet switchig. Circuit switchig

More information

Out the box. dataloggers. easy to configure easy data streaming easy choice. connect, simply configure and go

Out the box. dataloggers. easy to configure easy data streaming easy choice. connect, simply configure and go Out the box dataloggers easy data collectio easily prove easy to cofigure easy data streamig easy choice coect, simply cofigure ad go Rebel Data Loggers - A complete solutio The Rebel rage offers a complete

More information

Euclidean Distance Based Feature Selection for Fault Detection Prediction Model in Semiconductor Manufacturing Process

Euclidean Distance Based Feature Selection for Fault Detection Prediction Model in Semiconductor Manufacturing Process Vol.133 (Iformatio Techology ad Computer Sciece 016), pp.85-89 http://dx.doi.org/10.1457/astl.016. Euclidea Distace Based Feature Selectio for Fault Detectio Predictio Model i Semicoductor Maufacturig

More information

ELEG 5173L Digital Signal Processing Introduction to TMS320C6713 DSK

ELEG 5173L Digital Signal Processing Introduction to TMS320C6713 DSK Departmet of Electrical Egieerig Uiversity of Arasas ELEG 5173L Digital Sigal Processig Itroductio to TMS320C6713 DSK Dr. Jigia Wu wuj@uar.edu ANALOG V.S DIGITAL 2 Aalog sigal processig ASP Aalog sigal

More information

NVP-903 Series. Multi-Stream Network Video Encoder REFERENCE GUIDE

NVP-903 Series. Multi-Stream Network Video Encoder REFERENCE GUIDE NVP-903 Series Multi-Stream Network Video Ecoder REFERENCE GUIDE NVP-903 Series User Maual Table of Cotets 1 Itroductio... 4 1.1 Product Overview... 4 1.2 Product Features... 4 2 Pael Desig... 5 2.1 Frot

More information

CS 683: Advanced Design and Analysis of Algorithms

CS 683: Advanced Design and Analysis of Algorithms CS 683: Advaced Desig ad Aalysis of Algorithms Lecture 6, February 1, 2008 Lecturer: Joh Hopcroft Scribes: Shaomei Wu, Etha Feldma February 7, 2008 1 Threshold for k CNF Satisfiability I the previous lecture,

More information

Term Project Report. This component works to detect gesture from the patient as a sign of emergency message and send it to the emergency manager.

Term Project Report. This component works to detect gesture from the patient as a sign of emergency message and send it to the emergency manager. CS2310 Fial Project Loghao Li Term Project Report Itroductio I this project, I worked o expadig exercise 4. What I focused o is makig the real gesture recogizig sesor ad desig proper gestures ad recogizig

More information

vbonline Pro Condition Monitoring System Product Datasheet Bently Nevada* Asset Condition Monitoring

vbonline Pro Condition Monitoring System Product Datasheet Bently Nevada* Asset Condition Monitoring GE Measuremet & Cotrol vbolie Pro Coditio Moitorig System Product Datasheet Betly Nevada* Asset Coditio Moitorig Descriptio The vbolie Pro Coditio Moitorig System uses sophisticated sigal processig algorithms

More information

Web OS Switch Software

Web OS Switch Software Web OS Switch Software BBI Quick Guide Nortel Networks Part Number: 213164, Revisio A, July 2000 50 Great Oaks Boulevard Sa Jose, Califoria 95119 408-360-5500 Mai 408-360-5501 Fax www.orteletworks.com

More information

CTx / CTx-II. Ultra Compact SD COFDM Concealment Transmitters. Features: Options: Accessories: Applications:

CTx / CTx-II. Ultra Compact SD COFDM Concealment Transmitters. Features: Options: Accessories: Applications: Ultra Compact SD COFDM Cocealmet Trasmitters Features: Optimized for size Broadcast quality video H.264 Part 10 2 moo audio chaels Very low power cosumptio Remote cotrol via micro USB Bluetooth * Adroid

More information

APPLICATION NOTE PACE1750AE BUILT-IN FUNCTIONS

APPLICATION NOTE PACE1750AE BUILT-IN FUNCTIONS APPLICATION NOTE PACE175AE BUILT-IN UNCTIONS About This Note This applicatio brief is iteded to explai ad demostrate the use of the special fuctios that are built ito the PACE175AE processor. These powerful

More information

A New Morphological 3D Shape Decomposition: Grayscale Interframe Interpolation Method

A New Morphological 3D Shape Decomposition: Grayscale Interframe Interpolation Method A ew Morphological 3D Shape Decompositio: Grayscale Iterframe Iterpolatio Method D.. Vizireau Politehica Uiversity Bucharest, Romaia ae@comm.pub.ro R. M. Udrea Politehica Uiversity Bucharest, Romaia mihea@comm.pub.ro

More information

Service Oriented Enterprise Architecture and Service Oriented Enterprise

Service Oriented Enterprise Architecture and Service Oriented Enterprise Approved for Public Release Distributio Ulimited Case Number: 09-2786 The 23 rd Ope Group Eterprise Practitioers Coferece Service Orieted Eterprise ad Service Orieted Eterprise Ya Zhao, PhD Pricipal, MITRE

More information

System Overview. Hardware Concept. s Introduction to the Features of MicroAutoBox t

System Overview. Hardware Concept. s Introduction to the Features of MicroAutoBox t s Itroductio to the Features of MicroAutoBox t System Overview Objective Where to go from here dspace provides the MicroAutoBox i differet variats. This sectio gives you a overview o the MicroAutoBox's

More information

IMP: Superposer Integrated Morphometrics Package Superposition Tool

IMP: Superposer Integrated Morphometrics Package Superposition Tool IMP: Superposer Itegrated Morphometrics Package Superpositio Tool Programmig by: David Lieber ( 03) Caisius College 200 Mai St. Buffalo, NY 4208 Cocept by: H. David Sheets, Dept. of Physics, Caisius College

More information

Performance Plus Software Parameter Definitions

Performance Plus Software Parameter Definitions Performace Plus+ Software Parameter Defiitios/ Performace Plus Software Parameter Defiitios Chapma Techical Note-TG-5 paramete.doc ev-0-03 Performace Plus+ Software Parameter Defiitios/2 Backgroud ad Defiitios

More information

Appendix D. Controller Implementation

Appendix D. Controller Implementation COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Iterface 5 th Editio Appedix D Cotroller Implemetatio Cotroller Implemetatios Combiatioal logic (sigle-cycle); Fiite state machie (multi-cycle, pipelied);

More information

CAEN Tools for Discovery

CAEN Tools for Discovery BF2535 - Trasitio from Sy1527/Sy2527 Maiframes To Sy4527/Sy5527 Maiframes rev. 3-12 April 2012 CAEN Electroic Istrumetatio TRANSITION FROM SY1527/SY2527 MAINFRAMES TO SY4527/SY5527 MAINFRAMES Viareggio,

More information

Pruning and Summarizing the Discovered Time Series Association Rules from Mechanical Sensor Data Qing YANG1,a,*, Shao-Yu WANG1,b, Ting-Ting ZHANG2,c

Pruning and Summarizing the Discovered Time Series Association Rules from Mechanical Sensor Data Qing YANG1,a,*, Shao-Yu WANG1,b, Ting-Ting ZHANG2,c Advaces i Egieerig Research (AER), volume 131 3rd Aual Iteratioal Coferece o Electroics, Electrical Egieerig ad Iformatio Sciece (EEEIS 2017) Pruig ad Summarizig the Discovered Time Series Associatio Rules

More information

Ajao A. Lukman, Agajo J., Kolo J. Gana, Inalegwu C. Ogbole, and Edem E. Ataimo

Ajao A. Lukman, Agajo J., Kolo J. Gana, Inalegwu C. Ogbole, and Edem E. Ataimo DEVELOPMENT OF A LOW POWER CONSUMPTION SMART EMBEDDED WIRELESS SENSOR NETWORK FOR THE UBIQUITOUS ENVIRONMENTAL MONITORING USING ZIGBEE MODULE By Ajao A. Lukma, Agajo J., Kolo J. Gaa, Ialegwu C. Ogbole,

More information

AN EFFICIENT GROUP KEY MANAGEMENT USING CODE FOR KEY CALCULATION FOR SIMULTANEOUS JOIN/LEAVE: CKCS

AN EFFICIENT GROUP KEY MANAGEMENT USING CODE FOR KEY CALCULATION FOR SIMULTANEOUS JOIN/LEAVE: CKCS Iteratioal Joural of Computer Networks & Commuicatios (IJCNC) Vol.4, No.4, July 01 AN EFFICIENT GROUP KEY MANAGEMENT USING CODE FOR KEY CALCULATION FOR SIMULTANEOUS JOIN/LEAVE: CKCS Melisa Hajyvahabzadeh

More information

Basic allocator mechanisms The course that gives CMU its Zip! Memory Management II: Dynamic Storage Allocation Mar 6, 2000.

Basic allocator mechanisms The course that gives CMU its Zip! Memory Management II: Dynamic Storage Allocation Mar 6, 2000. 5-23 The course that gives CM its Zip Memory Maagemet II: Dyamic Storage Allocatio Mar 6, 2000 Topics Segregated lists Buddy system Garbage collectio Mark ad Sweep Copyig eferece coutig Basic allocator

More information

ICS Regent. Communications Modules. Module Operation. RS-232, RS-422 and RS-485 (T3150A) PD-6002

ICS Regent. Communications Modules. Module Operation. RS-232, RS-422 and RS-485 (T3150A) PD-6002 ICS Reget Commuicatios Modules RS-232, RS-422 ad RS-485 (T3150A) Issue 1, March, 06 Commuicatios modules provide a serial commuicatios iterface betwee the cotroller ad exteral equipmet. Commuicatios modules

More information

ANN WHICH COVERS MLP AND RBF

ANN WHICH COVERS MLP AND RBF ANN WHICH COVERS MLP AND RBF Josef Boští, Jaromír Kual Faculty of Nuclear Scieces ad Physical Egieerig, CTU i Prague Departmet of Software Egieerig Abstract Two basic types of artificial eural etwors Multi

More information

Keywords Software Architecture, Object-oriented metrics, Reliability, Reusability, Coupling evaluator, Cohesion, efficiency

Keywords Software Architecture, Object-oriented metrics, Reliability, Reusability, Coupling evaluator, Cohesion, efficiency Volume 3, Issue 9, September 2013 ISSN: 2277 128X Iteratioal Joural of Advaced Research i Computer Sciece ad Software Egieerig Research Paper Available olie at: www.ijarcsse.com Couplig Evaluator to Ehace

More information

Fundamentals of. Chapter 1. Microprocessor and Microcontroller. Dr. Farid Farahmand. Updated: Tuesday, January 16, 2018

Fundamentals of. Chapter 1. Microprocessor and Microcontroller. Dr. Farid Farahmand. Updated: Tuesday, January 16, 2018 Fudametals of Chapter 1 Microprocessor ad Microcotroller Dr. Farid Farahmad Updated: Tuesday, Jauary 16, 2018 Evolutio First came trasistors Itegrated circuits SSI (Small-Scale Itegratio) to ULSI Very

More information

performance to the performance they can experience when they use the services from a xed location.

performance to the performance they can experience when they use the services from a xed location. I the Proceedigs of The First Aual Iteratioal Coferece o Mobile Computig ad Networkig (MobiCom 9) November -, 99, Berkeley, Califoria USA Performace Compariso of Mobile Support Strategies Rieko Kadobayashi

More information

Chapter 4 The Datapath

Chapter 4 The Datapath The Ageda Chapter 4 The Datapath Based o slides McGraw-Hill Additioal material 24/25/26 Lewis/Marti Additioal material 28 Roth Additioal material 2 Taylor Additioal material 2 Farmer Tae the elemets that

More information

Transitioning to BGP

Transitioning to BGP Trasitioig to BGP ISP Workshops These materials are licesed uder the Creative Commos Attributio-NoCommercial 4.0 Iteratioal licese (http://creativecommos.org/liceses/by-c/4.0/) Last updated 24 th April

More information

Out the box. dataloggers. easy to configure easy data streaming easy choice. connect, simply configure and go

Out the box. dataloggers. easy to configure easy data streaming easy choice. connect, simply configure and go Out the box dataloggers easy data collectio easily prove easy to cofigure easy data streamig easy choice coect, simply cofigure ad go The stadard Rebel Compact (CT) is a small robust data logger ideal

More information

BGP Attributes and Path Selection. ISP Training Workshops

BGP Attributes and Path Selection. ISP Training Workshops BGP Attributes ad Path Selectio ISP Traiig Workshops 1 BGP Attributes The tools available for the job 2 What Is a Attribute?... Next Hop AS Path MED...... p Part of a BGP Update p Describes the characteristics

More information

Evaluation of Distributed and Replicated HLR for Location Management in PCS Network

Evaluation of Distributed and Replicated HLR for Location Management in PCS Network JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 9, 85-0 (2003) Evaluatio of Distributed ad Replicated HLR for Locatio Maagemet i PCS Network Departmet of Computer Sciece ad Iformatio Egieerig Natioal Chiao

More information

COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface. Chapter 4. The Processor. Part A Datapath Design

COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface. Chapter 4. The Processor. Part A Datapath Design COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Iterface 5 th Editio Chapter The Processor Part A path Desig Itroductio CPU performace factors Istructio cout Determied by ISA ad compiler. CPI ad

More information

The Magma Database file formats

The Magma Database file formats The Magma Database file formats Adrew Gaylard, Bret Pikey, ad Mart-Mari Breedt Johaesburg, South Africa 15th May 2006 1 Summary Magma is a ope-source object database created by Chris Muller, of Kasas City,

More information

Introduction to Network Technologies & Layered Architecture BUPT/QMUL

Introduction to Network Technologies & Layered Architecture BUPT/QMUL Itroductio to Network Techologies & Layered Architecture BUPT/QMUL 2018-3-12 Review What is the Iteret? How does it work? Whe & how did it come about? Who cotrols it? Where is it goig? 2 Ageda Basic Network

More information

Analysis of Server Resource Consumption of Meteorological Satellite Application System Based on Contour Curve

Analysis of Server Resource Consumption of Meteorological Satellite Application System Based on Contour Curve Advaces i Computer, Sigals ad Systems (2018) 2: 19-25 Clausius Scietific Press, Caada Aalysis of Server Resource Cosumptio of Meteorological Satellite Applicatio System Based o Cotour Curve Xiagag Zhao

More information

FREQUENCY ESTIMATION OF INTERNET PACKET STREAMS WITH LIMITED SPACE: UPPER AND LOWER BOUNDS

FREQUENCY ESTIMATION OF INTERNET PACKET STREAMS WITH LIMITED SPACE: UPPER AND LOWER BOUNDS FREQUENCY ESTIMATION OF INTERNET PACKET STREAMS WITH LIMITED SPACE: UPPER AND LOWER BOUNDS Prosejit Bose Evagelos Kraakis Pat Mori Yihui Tag School of Computer Sciece, Carleto Uiversity {jit,kraakis,mori,y

More information

Chapter 3 Classification of FFT Processor Algorithms

Chapter 3 Classification of FFT Processor Algorithms Chapter Classificatio of FFT Processor Algorithms The computatioal complexity of the Discrete Fourier trasform (DFT) is very high. It requires () 2 complex multiplicatios ad () complex additios [5]. As

More information

State-space feedback 6 challenges of pole placement

State-space feedback 6 challenges of pole placement State-space feedbac 6 challeges of pole placemet J Rossiter Itroductio The earlier videos itroduced the cocept of state feedbac ad demostrated that it moves the poles. x u x Kx Bu It was show that whe

More information

System and Software Architecture Description (SSAD)

System and Software Architecture Description (SSAD) System ad Software Architecture Descriptio (SSAD) Diabetes Health Platform Team #6 Jasmie Berry (Cliet) Veerav Naidu (Project Maager) Mukai Nog (Architect) Steve South (IV&V) Vijaya Prabhakara (Quality

More information

GTS Scheduling Scheme for Real-Time Communication in IEEE Industrial Wireless Sensor Networks

GTS Scheduling Scheme for Real-Time Communication in IEEE Industrial Wireless Sensor Networks Idia Joural of Sciece ad Techology, Vol 9(7), DOI:.7485/ijst/6/v9i7/87734, February 6 ISSN (Prit) : 974-6846 ISSN (Olie) : 974-5645 GTS Schedulig Scheme for Real-Time Commuicatio i IEEE8.5.4 Idustrial

More information

6.854J / J Advanced Algorithms Fall 2008

6.854J / J Advanced Algorithms Fall 2008 MIT OpeCourseWare http://ocw.mit.edu 6.854J / 18.415J Advaced Algorithms Fall 2008 For iformatio about citig these materials or our Terms of Use, visit: http://ocw.mit.edu/terms. 18.415/6.854 Advaced Algorithms

More information

Lecture 5. Counting Sort / Radix Sort

Lecture 5. Counting Sort / Radix Sort Lecture 5. Coutig Sort / Radix Sort T. H. Corme, C. E. Leiserso ad R. L. Rivest Itroductio to Algorithms, 3rd Editio, MIT Press, 2009 Sugkyukwa Uiversity Hyuseug Choo choo@skku.edu Copyright 2000-2018

More information

Computer Systems - HS

Computer Systems - HS What have we leared so far? Computer Systems High Level ENGG1203 2d Semester, 2017-18 Applicatios Sigals Systems & Cotrol Systems Computer & Embedded Systems Digital Logic Combiatioal Logic Sequetial Logic

More information

Network Time Protocol (NTP)

Network Time Protocol (NTP) Network Time Protocol (NTP) Quick ad Dirty for AfNOG 2018 (Michuki Mwagi) Origial slides by Ayitey Bulley About NTP Network Time Protocol project http://tp.org NTP is a protocol desiged to sychroize the

More information

Identification of the Swiss Z24 Highway Bridge by Frequency Domain Decomposition Brincker, Rune; Andersen, P.

Identification of the Swiss Z24 Highway Bridge by Frequency Domain Decomposition Brincker, Rune; Andersen, P. Aalborg Uiversitet Idetificatio of the Swiss Z24 Highway Bridge by Frequecy Domai Decompositio Bricker, Rue; Aderse, P. Published i: Proceedigs of IMAC 2 Publicatio date: 22 Documet Versio Publisher's

More information

G2 T. Specification Sheet G2T-001 G2T Touchscreen Mainframes Accepts G2 Plug-in Modules Four Sizes: 2RU, 3RU, 6RU and 8RU

G2 T. Specification Sheet G2T-001 G2T Touchscreen Mainframes Accepts G2 Plug-in Modules Four Sizes: 2RU, 3RU, 6RU and 8RU G2 T Geeral The G2T Maiframes are part of our field-prove G2 family of products ad replaces the G2S maiframes. The mai differece is the all ew frot pael touchscree desig which replaces the older VF display

More information

Pattern Recognition Systems Lab 1 Least Mean Squares

Pattern Recognition Systems Lab 1 Least Mean Squares Patter Recogitio Systems Lab 1 Least Mea Squares 1. Objectives This laboratory work itroduces the OpeCV-based framework used throughout the course. I this assigmet a lie is fitted to a set of poits usig

More information

Floristic Quality Assessment (FQA) Calculator for Colorado User s Guide

Floristic Quality Assessment (FQA) Calculator for Colorado User s Guide Floristic Quality Assessmet (FQA) Calculator for Colorado User s Guide Created by the Colorado atural Heritage Program Last Updated April 2012 The FQA Calculator was created by Michelle Fik ad Joaa Lemly

More information

n Explore virtualization concepts n Become familiar with cloud concepts

n Explore virtualization concepts n Become familiar with cloud concepts Chapter Objectives Explore virtualizatio cocepts Become familiar with cloud cocepts Chapter #15: Architecture ad Desig 2 Hypervisor Virtualizatio ad cloud services are becomig commo eterprise tools to

More information

Improving Template Based Spike Detection

Improving Template Based Spike Detection Improvig Template Based Spike Detectio Kirk Smith, Member - IEEE Portlad State Uiversity petra@ee.pdx.edu Abstract Template matchig algorithms like SSE, Covolutio ad Maximum Likelihood are well kow for

More information