Programming Multicore Systems

Transcription

1 Programming Multicore Systems Enabling real time applications for multicore with the XMOS development tools 5 th September 2011 Matt Fyles

2 XMOS Company Overview Established Fabless Semiconductor Company New class of programmable device Event Driven Processor Offices in Bristol, Chennai, Singapore, San Jose Production partner TSMC XMOS Vision XMOS programmable chips bring together the capabilities of processors, DSPs, ASICs and FPGAs, but are programmed via a unified design flow in C, XC and C++

3 XMOS Processors Used in embedded real-time systems to provide hardware interfaces and data processing capability Number of cores used depends on the application complexity and are easily scalable Hardware interconnect mechanism provides ability to transfer data efficiently between cores Programmed in high level languages with a standard software tool chain for application development

4 Input Output Ports XMOS Architecture - Processor How is XMOS different? Hardware multi-threaded Hard real time threads Each thread executes at least every 20ns Event driven execution Instant response without interrupts XCore 8KB OTP JTAG TAP 64KB SRAM Thread 0 Thread 1 Thread 2 Thread 3 Thread 4 Thread 5 Thread 6 Real Time Resources Channel Ends Software tasks #include BinarySearch.h int BinarySearch(unsigned index, unsigned table[]) { // First entry is size int start = 1; int end = table[0] + 1; int middle; int x; int found = 0; } do { middle = start + ((end - start) >>1); x = table[middle] & 0xFFFF; if (x == index) found = 1; else if (middle == start) found = -1; else if (index < x) end = middle; else start = middle; } while (found == 0); if (found == 1) return middle; else return -1; Intelligent ports Tightly coupled Channel communications Compose systems from multiple threads Thread 7 Hardware interfaces TX-CLK TX-EN Preamble SFD D AT A ETXD[3:0] CRC Signal processing capability x(n) z -1 z -1 z -1 a0 a1 a2 a3 TX-ER CRS COL

5 XMOS Architecture Real Time Support Interrupt Traditional CPU Interrupt Task A Internal operation Task B Save all registers Fetch ISR vector Execute Task B Clear request Restore registers Save all registers Fetch ISR vector etc. Event XMOS CPU Event Task A Task B Execute Task B Task B paused Execute Task B XMOS is hard real time Timing closure easily achieved and kept after design changes Tools to help guarantee timing

6 Input Output Ports Input Output Ports XMOS Architecture Channels Deterministic communications interconnect Connects threads, cores & devices at up to 1Gbps+ Synchronised, transactional and streaming modes Non blocking Compose systems from multiple threads Link Thread 0 Thread 0 Thread 1 Thread 2 Thread 3 Thread 4 Thread 5 Thread 6 Channel Ends Switch Channel Ends Thread 1 Thread 2 Thread 3 Thread 4 Thread 5 Thread 6 Threads on same core Threads on different core Threads on different chip Thread 7 Thread 7

7 MultiCore XMOS Platforms Development tools need to scale across systems with multiple numbers of processor cores and distribute application code Ipod Dock Platform Single Xcore Processor 8 HW Threads 64KB SRAM Motor Control Platform 3 Xcore processors 24 HW Threads 192KB SRAM XMP-64 Dev Platform 64 Xcore processors 512 HW Threads 4MB SRAM

8 Example Application Structure Multi-Channel USB Audio 2.0 Interface Dual XCore device Multiple parallel hardware threads 1 st core provides USB interface and buffering 2 nd core provides audio interface and processing

9 XMOS Development Tools XMOS DEVELOPMENT ENVIRONMENT.C.CPP.XC Embedded Software Flow Use XC, C and C++ Unified flow for control, signal processing and interfaces Supports multiple threads and cores SIMULATOR COMPILER COLLECTION DEBUGGER BINARY BOARD UTILS HARDWARE TIMING Built on industry standard platforms Eclipse (IDE) GCC/LLVM (C compiler) ELF (Object Format) GDB (Debugger) Complete set of tools in one package Includes board level tools (FLASH etc.) Unique static timing tool (XTA) Choose your own flow Windows, Linux or MAC Command line or eclipse Zero cost download

10 The XC Language #include <platform.h> #include <xs1.h> void functiona(chanend A){} void functionb(chanend A, chanend B){} void functionc(chanend B){} int main (void) { chan channela, channelb; par { on stdcore[0] : functiona(channela); on stdcore[0] : functionb(channela, channelb); on stdcore[1] : functionc(channelb); } } return 0;

11 Compilation Tools Allows user to target XMOS platforms using C / C++ / XC, built around industry standard LLVM platform XC exposes multi-core nature of XMOS architecture to users via simple built-in types and constructs Easy to set up communication paths between software tasks to allow for synchronisation and data transfer Uses the standard ELF file format wrapped in a multicore XMOS format to provide a single binary for multiple processors

12 Mapping Tools Allows users to easily manage system configuration for target platform and board configuration Sets up device routing for channel communication without required user input regarding mapping Provides feedback to user on resource usage across all the devices in an application Automatically manages setup code for using multiple threads and cores and distributes code

13 XMOS Multicore Binary File Multicore binary (.xe) file Binary per core for device network setup and XMOS link configuration and connection Binary per core for user application code containing program data and debug info Platform configuration files for target device containing information for board settings Configuration files for creating simulated device to mirror hardware in XMOS simulator

14 Debugging Multicore Systems Multiple processors in system, in embedded systems there can be a complex JTAG chain to manage Separate distributed address spaces for code execution and data storage in application One program binary and symbol table per processor core, user has to manage multiple binaries Standard debugging features such as breakpoints and watchpoints need to work across multiple processors

15 XMOS Debugger Based on an extended GNU debugger (XGDB) Automatically configures to support multiple processors in JTAG chain at runtime Provides combined processor and thread view for any number of XCore devices in a system Manages the executables required for multi-core development without user interaction Extends standard GDB commands to work across multiple processor address spaces

16 XMOS IDE - Debugging Extended Eclipse CDT built on top of GNU debugger Provides enhanced thread / core view to support XMOS GNU debugger extensions

17 Profiling Multicore Systems In multicore systems it is difficult to synchronise events from different processors due to lack of a global time reference Trace data has to be collected from multiple cores in parallel and stored back on a host machine Without an accurate system level view of when each processor is active it is very hard to tune performance Must allow the real time nature of applications to continue to function correctly at runtime

18 Profiling XMOS Platforms XScope Multicore hardware profiling tool Post mortem analysis Tradition style software profiler Displays code execution information across processor cores Visualise application data values post execution Shows both timeline and graphical data views Runtime analysis Software logic analyser Displays application specific data values at runtime Can be set to trigger on specific event conditions HW oscilloscope style view of application execution

19 Profiling XMOS Data Collection Development tools interface board uses and XMOS device for the USB to host bridge Allows development adapter to become part of application device network at runtime Uses the XMOS link network of the application to transmit trace messages to the host system

20 XScope Post Mortem

21 XScope Runtime Visualisation

22 Conclusion XMOS development tools seamlessly scale from single to multiple processors The XMOS architecture allows complex multi-core systems to be built to fit the application need Extended debug and profiling capabilities built upon standard tools provide a familiar user experience Platforms designed around XMOS technology can be augmented with addition processor cores after the initial design is complete

23 To Finish Questions?