Combining Arm & RISC-V in Heterogeneous Designs

Transcription

1 Combining Arm & RISC-V in Heterogeneous Designs Gajinder Panesar, CTO, UltraSoC RISC-V Summit 3 5 December 2018 Santa Clara, USA

2 Problem statement Deterministic multi-core Example scenarios In-field analysis/ml Summary 2

3 Problem statements It is not about the ISA(s) It is not about the core(s) Compute is largely solved The challenge today is systemic complexity, for example: Ad-hoc programming paradigms -processor interactions HW/SW interactions Interconnect, & deadlock System not architected 3

4 Advanced Debug/itoring for the Whole SoC Interconnect (AXI, ACE, ACE-lite, OCP, ) xtensa DSP DRAM controller GPU Custom Logic Bus Trace Receiver PAM PAM Trace Encoder PAM Static Instrumentation DMA Status itor Portfolio of Analytic Modules Message Engine Message Engine Message Engine Message Engine Flexible & Scalable Message Fabric System Block UltraSoC IP AXI Comm JTAG Comm USB Comm Universal Streaming Comm System Memory Buffer Family of Communicators 4

5 UltraSoC A coherent architecture to debug, monitor and provide rich data for run-time analytics Silicon IP is highly parameterizable - allows customers to trade hardware resources and thus silicon area Hardware resources are configurable at runtime Allows reuse of hardware resources for different scenarios and different algorithms Help with security and safety of systems Hardware provides data so CPU load is small 5

6 Problem statement Deterministic multi-core Example scenarios In-field analysis/ml Summary 6

7 Deterministic multi-core system I P P + P P P P P P I P P P P P P P P P P P P P + P P + P P P P P I P P P P P P P P I I picoarray concept, circa

8 Deterministic multi-die, multi-core system + + X + X + X + X X picoarray concept, circa December 2018 Commercial in Confidence UL PT 8

9 Hardware accelerator flow Arm Host processor Peripherals 9

10 Problem statement Deterministic multi-core Example scenarios In-field analysis/ml Summary 10

11 Requirements on tools There is a need for heterogeneous architectural and modelling exploration systems Be able to feed in run-time system data to close the loop There is a need for true heterogeneous core tool chain This is especially true for debugging tools Open source tools such as GDB and OpenOCD need to handle this in an efficient manner Strangely, not everyone likes or wants open source tools it is True! Need one cockpit for the different cores in a system Need to have tools that help with run-time visibility These need to have open APIs As complexity continues to increase, need means of autonomous analysis 11

12 Typical SoC with network on chip Multiple processors with fully coherent caches I/O coherent accelerator Shared memory controller could be ring, mesh or crossbar RISC-V Bridge Accelerator CHI SN-F Memory Controller CHI SN-I Peripherals 12

13 Unified run-control with UltraSoC interconnect Separate from system interconnect Message-based Used for both configuration (in) and diagnostic reporting (out) PAM RISC-V Bridge Accelerator Integrated real-time event broadcast for cross-triggering UltraSoC message + cross-triggering infrastructure CHI SN-F Memory Controller Communicator PHY CHI SN-I Peripherals 13

14 Heterogeneous run-control 14

15 boundary monitoring UltraSoC monitors on connections to the itors are fully transaction aware RISC-V Bridge Accelerator CHI SN-F Memory Controller CHI SN-I Peripherals 15

16 Example: deadlock detection Automatically detect deadlock on the Trace all traffic into circular buffer within monitor Trigger trace if transaction duration exceeds threshold (e.g. 5k cycles) Stop tracing and output full details of deadlocked transaction and those immediately preceding it Nothing sent off-chip until deadlock occurs CHI SN-F Memory Controller RISC-V Bridge CHI SN-I Peripherals Accelerator 16

17 # transactions Example: where have my MIPs gone? CPU spent cycles [PERCEN 8% TAGE] [PERCEN TAGE] Compute Stall 1 outstanding Stall 2 outstanding RISC-V Bridge Accelerator Cache-miss duration Max cycles Avg Duration histogram CHI SN-F Memory Controller CHI SN-I Peripherals cycles 17

18 Example: how effectively is data shared? Reads vs snoops Snoop 2 CPU 0 Snoop reads 0 200lines RISC-V Bridge Accelerator Snoop 0 CPU 1 Snoop 2 reads lines CPU 2 Snoop 1 Snoop 0 reads 2 CHI SN-F Memory Controller CHI SN-I Peripherals lines 18

19 Internal monitoring Example shows ring topology Intra-router monitors are typically not transaction aware itor individual channels only Simpler Router Router CHI SN-F Memory Controller RISC-V Bridge Accelerator Accelerator Router Router Router Router CHI SN-I Peripherals 19

20 Independent, orthogonal UltraSoC interconnect Separate from system interconnect Message-based Used for both configuration (in) and diagnostic reporting (out) Integrated real-time event broadcast for cross-triggering PAM RISC-V Bridge UltraSoC message + cross-triggering infrastructure Accelerator CHI SN-F Memory Controller Communicator PHY CHI SN-I Peripherals 20

21 Example: is the oversubscribed or unbalanced? NM5 NM4 NM0 Cycles with no link credit SRSP CRSP RDAT WDAT SNP REQ % Router Router Router Router Router RISC-V Bridge Router Accelerator NM5 Cycles not idle SRSP CRSP NM4 NM0 RDAT WDAT SNP REQ % CHI SN-F Memory Controller CHI SN-I Peripherals 21

22 Example: deadlock with cross-triggering Trace Receiver module Captures processor trace (e.g. from ARM ETM) into circular buffer RISC-V trace captured in circular buffer Trace RX Trace Enc RISC-V Bridge Accelerator monitor trace trigger also cross-triggers Trace Receiver and RISC-V Trace Encoder UltraSoC message + cross-triggering infrastructure CHI SN-F Memory Controller Communicator PHY CHI SN-I Peripherals 22

23 Software tools for data-driven insights RISC-V CPU Eclipse based UltraDevelop IDE Single step & breakpoint CPU code & decoded trace Script based Multiple other CPUs SW & HW in one tool Real-time HW Data RISC-V instruction packets 23

24 Problem Statement Deterministic multi-core Example scenarios In-field analysis/ml Summary 24

25 Non intrusive anomaly detection Three CPU plots below show CPU cache-like traffic for 3 CPUs configured with different miss rates Excessive (anomalous) latencies are shown in red 25

26 Non-intrusive profiling with anomaly detection Traditional profilers are inadequate: Sampling = miss subtle or fast events (Nyquist) Performance impact/intrusive Heisenbugs UltraSoC is non-intrusive UltraSoC is wirespeed (100% coverage) Analytics and automated anomaly detection to make engineer more efficient 5 December 2018 Commercial in Confidence UL PT 26

27 Problem Statement Deterministic multi-core Example scenarios In-field analysis/ml Summary 27

28 Summary The challenge today is systemic complexity Architectural and modelling is needed but not enough Need tools that support true heterogenous systems Both open source and commercial In addition to run-control, need non-intrusive monitoring More complex systems will require autonomous analytics and causality detection UltraSoC provides all or is working on all these 28