Cover sheet. Interrupt communication via the LBU interface ERTEC 200. FAQ November Service & Support. Answers for industry.

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1 Cover sheet Interrupt communication via the LBU interface ERTEC 200 FAQ November 2009 Service & Support Answers for industry.

2 Question This entry originates from the Service&Support Portal of Siemens AG, Sector Industry, Industry Automation and Drive Technologies. The conditions of use specified there apply ( Go to the following link to download this document. Question How can the ERTEC 200 communicate with an external host processor via the LBU interface? Answer Follow the instructions and notes listed in this document for a detailed answer to the above question. 2 V1.1, Entry ID:

3 Contents Contents 1 Introduction... 4 Communication via the LBU bus interface with interrupts Interrupt Controller Interrupt Controller Host Interrupt Handling Communication Host Processor ARM Processor History V1.1, Entry ID:

4 1 Introduction 1 Introduction The ERTEC 200 can also communicate with an external host processor. The LBU bus interface is available for this purpose. Communication via the LBU bus interface with interrupts The external host processor wants to send data to the ARM processor (ARM946E- S) via a memory area to be self-defined. It writes its data and then an arbitrary value to the Activate_SP_Interrupt register, which creates an interrupt on the ARM processor. This can then read out the data. The ARM processor wants to send data to the external host processor via a memory area to be self-defined. It writes its data and then an arbitrary value to the Activate_HP_Interrupt register, which creates an interrupt on the LBU side. However, the following parameters must be set for this: Mode Interrupt mask Interrupt signal Interrupt number When an interrupt occurs, the data can be read out and then the host processor has to write it to the EOI register. Please refer to the ERTEC 200 manual for information on activating, assigning registers and timing for the LBU. 4 V1.1, Entry ID:

5 2 Interrupt Controller 2 Interrupt Controller 2.1 Interrupt Controller The IRTE switch controller must be able to work together with two different processors: An ARM processor integrated in the ERTEC 200 A host processor connected via an LBU interface However, the distribution of tasks between the two processors is not defined. This is why the assignment of the separate interrupt sources to the interrupt inputs concerned is done universally. There is an integrated interrupt controller in the IRTE switch controller. The interrupt events, which occur in the interrupt switch controller for the ARM and external host processors, are conducted to two group interrupts of each processor (see Figure 2-1). Figure 2-1 Interrupt diagram Interrupt - Events IRTE-Switch-Controller 3 1 Interrupt - Controller for ARM - Processor Interrupt - Controller for Host -Processor XIRQ0_SP XIRQ1_SP XIRQ0_HP XIRQ1_HP Interrupt - Controller of ARM - Processor Interrupt-Controller of Host - Processor Other interrupt events of the IRTE switch controller are conducted directly to the interrupt controllers of the ARM processor (3) and host processor (1). The two interrupt controllers in the IRTE switch controller are identical. For this reason, we will only describe one in the following. Furthermore, both interrupt events are split over two words. The interrupt controller described can conduct each interrupt event to each group interrupt XIRQ0_SP or XIRQ1_SP and XIRQ0_HP or XIRQ1_HP respectively. However, the practical model used assumes that all interrupt events that have to do with NRT communication and other (error) processing are conducted to the interrupt input. The result is that only ever one interrupt word has to be processed in the relevant analysis section of the assigned ISR routine. Figure 2-2 gives an overview of the basic structure of an interrupt controller. The split over two interrupt words is not shown explicitly here. All the registers within the dashed line are available in duplicate (for SP and HP). V1.1, Entry ID:

6 2 Interrupt Controller Figure 2-2 Structure of an interrupt controller for two interrupt words all Interrupt- Events IRR IMR 0 IMR 1 IR 0 EOI 0 I-Formation I-Mode I-Formation XIRQ0 XIRQ1 legend: IRR: Interrupt Request Register IAR: Interrupt Acknowledge Register IMR0/1 : Interrupt Mask Register IR0/1: Interrupt Register EOI0/1: End of Interrupt Register I-Mode : Interrupt-Mode Register IAR IR 1 EOI 1 Table 2-1 shows the structure of the NRT interrupt word. It is universally valid for all the registers described below. Table 2-1 Bit Description INT_HPActivate Write access has been made to the Activate_HP_Interrupt register. 13 INT_SPActivate Write access has been made to the Activate_SP_Interrupt register Note All register addresses are to be seen relative to the base address of the IRTE switch controller. When an interrupt occurs, it sets Bit 12 or Bit 13 in the NRT interrupt word of the Interrupt_Request_Register_NRT (IRR) register. Writing to this register can only set bits to 1. Table 2-2 Structure of NRT interrupt word Bit 0-11 Bit 12 Bit 13 Bit Register: Interrupt_Request_Register_NRT 1741C (hex) IRR SC bus (r/w) 0 = No interrupt 1 = Interrupt 0 = No interrupt 1 = Interrupt The bits in the IRR can only be reset to 0 by writing to the "virtual" register Interrupt_Acknowledgement_Register_NRT (IAR). 6 V1.1, Entry ID:

7 2 Interrupt Controller Table 2-3 Register: Interrupt_Acknowledgement_Register_NRT Structure of NRT interrupt word Bit 0-11 Bit 12 Bit 13 Bit (hex) SC bus (-/w) 0 = Interrupt is not deleted 1 = Interrupt is deleted 0 = Interrupt is not deleted 1 = Interrupt is deleted The IAR corresponds to the reset inputs of the IRR. The interrupt events assigned to the interrupt input 0 (XIRQ0) are created with the IRM0_Mask_Register_NRT (IMR0) register. Table 2-4 Structure of NRT interrupt word Bit 0-11 Bit 12 Bit 13 Bit Register: IRM0_Mask_Register_NRT (hex) IRM (hex) SC bus (r/w) 0 = Interrupt is not for XIRQ0 1 = Interrupt is for XIRQ0 0 = Interrupt is not for XIRQ0 1 = Interrupt is for XIRQ0 The interrupt events assigned to the interrupt input 1 (XIRQ1) are created with the IRM1_Mask_Register_NRT (IMR1) register. Table 2-5 Structure of NRT interrupt word Bit 0-11 Bit 12 Bit 13 Bit Register: IRM1_Mask_Register_NRT (hex) IRM (hex) SC bus (r/w) 0 = Interrupt is not for XIRQ1 1 = Interrupt is for XIRQ1 0 = Interrupt is not for XIRQ1 1 = Interrupt is for XIRQ1 V1.1, Entry ID:

8 2 Interrupt Controller The assigned interrupt events can be read via the IR0_Register_NRT or IR1_Register_NRT register. Table 2-6 Register: IR0_Register_NRT (hex) IR (hex) SC bus (d_r/-) 1 Structure of NRT interrupt word Bit 0-11 Bit 12 Bit 13 Bit = No XIRQ0 interrupt 1 = XIRQ0 interrupt 0 = No XIRQ0 interrupt 1 = XIRQ0 interrupt Table 2-7 Register: IR1_Register_NRT 1740C (hex) IR (hex) SC bus (d_r/-) 2 Structure of NRT interrupt word Bit 0-11 Bit 12 0 = No XIRQ1 interrupt 1 = XIRQ1 interrupt Bit 13 0 = No XIRQ1 interrupt 1 = XIRQ1 interrupt Bit At the end of each interrupt routine, the interrupt signal (XIRQ0 or XIRQ1) is deactivated by a write access to the IR0_EOI_Register or IR1_EOI_Register register. If there is still a source present upon expiry of the "Inactive_Time + 1" in the IR register, then the interrupt signal is activated again in a number of clocks. CPU interrupt controllers that work with edge triggering are retriggered in this case. Table 2-8 Bit 0-3 Register: IR0_EOI_Register (hex) Bit 0-3: inactive Bit 4-31: not implemented (hex) SC bus (-/w) Inactive_Time 1 d_r = destructive read in the Read-Only mode (the IR register is deleted when read) 2 d_r = destructive read in the Read-Only mode (the IR register is deleted when read) 8 V1.1, Entry ID:

9 2 Interrupt Controller Table 2-9 Bit 0-15 Register: IR0_EOI_Register Defines as a number of 50MHz clocks the duration of the deactivation of the interrupt output when writing to this EOI register. Must be written to deactivate each interrupt. Inactive time = (Inactive_Time +1)*T CLK ns Register: IR0_EOI_Register 1724C (hex) Bit 0-15: inactive Bit 16-31: not implemented (hex) SC bus (-/w) Inactive_Time Defines as a number of 50MHz clocks the duration of the deactivation of the interrupt output when writing to this EOI register. Must be written to deactivate each interrupt. Inactive time = (Inactive_Time +1)*T CLK ns Two different modes are implemented to handle the interrupt controller: Read-Modify-Write mode Read-Only mode You can set these modes via the Interrupt_Mode_Register register. Table 2-10 Bit 0 (R0) Bit 1 (R1) Bit 1 (L0) Bit 2 (L1) Register: Interrupt_Mode_Register (hex) Bit 0: R0 Bit 1: R1 Bit 2: L0 Bit 3: L1 Bit 4-31: not implemented (hex) SC bus (r/w) 0 = Interrupts are not deleted when the IR0 is read 1 = Interrupts are deleted when the IR0 is read 0 = Interrupts are not deleted when the IR1 is read 1 = Interrupts are deleted when the IR1 is read 0 = Level of the active interrupt in XIRQ0 is zero active 1 = Level of the active interrupt in XIRQ0 is one active 0 = Level of the active interrupt in XIRQ1 is zero active 1 = Level of the active interrupt in XIRQ1 is one active V1.1, Entry ID:

10 2 Interrupt Controller In the Read-Modify-Write mode, the processor reads out the IR concerned after recognizing an interrupt at its interrupt inputs (XIRQ0 or XIRQ1) and decides for the interrupt input set with the highest priority. Once the associated interrupt routine has been processed, the interrupt input is reset by a write access to the corresponding bit position of the IAR in the IRR and thus in the IR. This reset takes effect immediately. However, the interrupt output remains active until the EOI register is written to. If there are then still other interrupt inputs in the IR, these continue to be signaled at the interrupt input after the EOI time. Processing of each separate interrupt bit in the IR requires a read cycle to the IR and a write cycle to the IAR. In the Read-Only mode, the processor likewise reads out the IR concerned after an interrupt. However, with the read cycle to the IR, all the bits set there are reset completely in one cycle in the IRR and thus in the IR. Likewise, the interrupt output remains active until the EOI register is written to. The processor itself internally stores all the IR bits set and thus all the interrupt events, and processes them software controlled via the interrupt routines according to an order of priority. It is not possible to process the IR bits bit-by-bit and thus use the interrupt controller as "buffer memory". However, only one read cycle to the IR is required to process all the currently present interrupt bits in the IR. 2.2 Host Interrupt Handling The ERTEC 200 generates the following two interrupt signals to the external host processor. LBU_IRQ0_N LBU_IRQ1_N Both interrupt signals are generated in the IRT switch interrupt controller. Both signals are set by default to "Low Active". However, they can also be without parameters in the IRT switch interrupt controller. Mailbox handling between the ARM946E-S and an external host processor is possible via the IRT switch interrupt controller. An interrupt request from the ARM946E-S to the host processor is triggered by writing to the Activate_HP_Interrupt register. An interrupt request from the host processor to the ARM946E-S is triggered by writing to the Activate_SP_Interrupt register. Both processors can inform each other by writing to the assigned register Activate_HP_Interrupt or Activate_SP_Interrupt. These two registers are write-only. The value to be written is arbitrary. Table 2-11 Description Activate_HP_Interrupt (hex) SC bus (-/w) A write procedure to this register triggers the interrupt INT_HPActivate in the ARM register and in the host-interrupt-request register. 10 V1.1, Entry ID:

11 2 Interrupt Controller Table 2-12 Activate_SP_Interrupt hex SC bus (-/w) A write procedure to this register triggers the interrupt INT_SPActivate in the ARM register and in the host-interrupt-request register. V1.1, Entry ID:

12 3 Communication 3 Communication 3.1 Host Processor Implement the interrupt controller via the LBU interface as described in chapter 2. The interrupt controller of the host processor must be initialized. Then, for example, an interrupt request from the host processor to the ARM946E-S can be triggered by writing to the Activate_SP_Interrupt register. An interrupt request from the ARM946E-S to the host processor is triggered by writing to the Activate_HP_Interrupt register. Whether LBU_IRQ0_N or LBU_IRQ1_N is activated depends on the register assignments. 3.2 ARM Processor In the sample application, both interrupts are activated on the ARM processor side. This means that writing to the Activate_SP_Interrupt or Activate_HP_Interrupt register triggers processing of the interrupt routine in the ARM. For processing, you can insert a callback function (ertec_int_doactivate_sp()) for Activate_SP_Interrupt in ebx00_irt_lib.c file. Table 3-1 File: ertec_int.c static REGISTER_CBF RegCbf_Activate_Sp; void ertec_int_doactivate_sp (void) { if (RegCbf_Activate_Sp.Active == PNIO_TRUE) { // call user defined Activate_SP CBF (RegCbf_Activate_Sp.pCbf) (); } } OsMemSet (&RegCbf_Activate_Sp, 0, sizeof (RegCbf_Activate_Sp)); Case PNIO_CP_CBE_ACTIVATE_SP_IND: if (pcbf) { RegCbf_Activate_Sp.pCbf=pCbf; // first set cbf RegCbf_Activate_Sp.Activate = PNIO_TRUE; // and set activation flag } Else { RegCbf_Activate_Sp.pCbf=pCbf // then clear cbf; RegCbf_Activate_Sp.Active = PNIO_FALSE; // and clear activation flag } break; Add to the ebx00_irt_lib.c file as follows. 12 V1.1, Entry ID:

13 3 Communication Table 3-2 File: ebx00_irt_lib.c #define SYS_ISR_NRT_RCV_LOW_MASK (IRQ_CHB1_RCV_DONE IRQ_CHA0_RCV_DONE IRQ_SP) void ertec_int_doactivate_sp (void); {ertec_int_doactivate_sp, IRQ_SP, SYS_ISR_CBF_ID_SP, &SYS_ISR_db[SYS_ISR_ENUM_RQB_NRT_RCV_LOW].access, &SYS_ISR_db[SYS_ISR_ENUM_RQB_NRT_RCV_LOW].nrtMask, IRQ_MASK_NRT}, Add to the enum PNIO_CP_CBE_TYPE in the pniousrd.h file as follows. Table 3-3 File: pniousrd.h typedef enum { PNIO_CP_CBE_ACTIVATE_SP_IND = 6 } PNIO_CP_CBE_TYPE; You must enter the callback function and the necessary registration in the application. Table 3-4 void PNIO_cbf_activate_sp (void) { // to do } void MainAppl (void) { PNIO_CP_register_cbf (PNIO_CP_CBE_ACTIVATE_SP_IND, // activate SP callback (PNIO_CP_CBF) PNIO_cbf_activate_sp); V1.1, Entry ID:

14 4 History 4 History Table 4-1 Version Date Amendments V First edition V Change to version V3.1 of the ERTEC DK 14 V1.1, Entry ID:

4) In response to the the 8259A sets the highest priority ISR, bit and reset the corresponding IRR bit. The 8259A also places

4) In response to the the 8259A sets the highest priority ISR, bit and reset the corresponding IRR bit. The 8259A also places Lecture-52 Interrupt sequence: The powerful features of the 8259A in a system are its programmability and the interrupt routine address capability. It allows direct or indirect jumping to the specific