Lecture-61 Initialization Control Word 2 (ICW2):

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Jeremy Goodwin
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1 Lecture-61 Initialization Control Word 2 (ICW2): After issuing ICW1 on even address, the PIC is ready to accept initialization Control Word 2. It is issued to an address having A 0 =1, i.e., on odd address. The format for ICW2 is shown below: A 15 /T 2 A 14 /T 6 A 13 /T 5 A 12 /T 4 A 11 /T 3 A 10 A 9 A 8 A 15 -A 8 specify the higher byte address of the interrupt for 8080/85 system only. For 8086, T 7 -T 3 are used to specify the interrupt vector type. These bits are inserted in the five most significant bits of the vectoring byte and the 8259A sets the three least significant bits according to the interrupt level as below: A 2 A 1 A 0 Interrupt IR O IR IR IR IR IR IR IR 7 Thus, an 8085A system using a single 8259A could be programmed with only two ICWs; ICW1 & ICW2. For example, let ICW1 = and ICW2 = With these initialization command words, the interrupt request inputs are programmed for edge triggered mode. In addition, the 8259A s

2 priority instruction would be operating in the fully rested mode i.e. IR 0 having the highest priority. Initialization Control Word 3 (ICW3): This word is required only when there is more than one 8259A in the system and one cascading is used in which case SNGL=0. In master slave configuration mode, the slaves outputs are connected to master interrupt request inputs by the user. Therefore, both the master and the slave must be informed about this interconnection. It is done by issuing ICW3 to 8259A. It will load the 8-bit slave register. The functions of this register are: a) The format of ICW3 to be issued to master 8259A is, S 7 S 6 S 5 S 4 S 3 S 2 S 1 S 0 If S i =1, IR input has a slave and if S i =0, IR input does not have a slave. If the interrupt controller is set to work as master (either through software or hardware) a 1 is set for each slave in the system. The master will then release byte 1 of the CALL sequence, i.e., CDH (80/85 system only) and will enable the corresponding slave to release bytes 2 and 3 through the address lines. In 86/88 system, the selected slave will release the 2 nd byte). b) If the interrupt controller is used in slave mode, bits D 2 -D 0 identify the slave. The format of control word fir ICW3 issued to slave 8259A is as below:

3 ID 2 ID 1 ID 0 Slave Device The three identification bits ID 2, ID 1, and ID 0 tells the slave 8259A to which master input, slave is connected as shown above. The master 8259A releases the 3-bit identification code on local CAS 2 -CAS 0 bus during interrupt acknowledge machine cycle. The slave compares its cascade input with these bits and if they are equal bytes 2 & 3 of the CALL sequence are released by the selected slave on the data bus. Initialization Control Word 4 (ICW4): ICW4 is issued to 8259A only if ICW4 bit in ICW1 is set to 1, otherwise the contents of ICW4 are cleared. The format of ICW4 is given below: SFNM BUF MS AEOI μpm Bits D 7 -D 5 are always set to zero.

4 Bit D 4 (SFNM): If set to 1, the special fully nested mode is used. This mode is utilized in system having more than one 8259A. If set to 0, it is not specific fully nested mode. Bit D 3 (BUF): If BUF is set to 1, the buffered mode is programmed, otherwise non buffered mode. In this mode SP/EN becomes an enable output and the master/slave determination is by M/S. Bit D 2 (M/S): If buffered mode is selected SP/EN is programmed as input. Therefore, master slave configuration is set using M/S bit. M/S=1 means the 8259A is programmed to be a master. M/S =0 means the 8259A is programmed to be a slave. If BUF = 0, M/S has no function. Bit D 1 (AEOI): If AEOI =1, the interrupt controller is programmed automatic end of interrupt mode is programmed. Bit D 0 (μpm): This bit is used to set the microprocessor mode. By default the chip is programmed for 8-bit system. If μpm =1, it sets the 8259A for 8086 system operation. However, to programme other features by ICW4 for 8-bit system μpm is made 0 which sets 8259A for 8085 system operation.

5 The sequence of issuing the Initialization Control Words is shown in flowchart: Issue ICW1 Issue ICW2 No SNGL=1 Is Cascade Mode? Yes Issue ICW3 Yes No IC4=0 Is Cascade Mode? Issue ICW4 Ready to Accept OCWs Fig.11.4 Flowchart of Issuing ICWS Operation command words (OCWs): After 8259A has been initialized, it is ready to accept interrupt requests at its input lines. During operation the 8259A can be commanded to operate in different modes using operation control words (OCWs). There are three operation control words (OCWS)- OCW1, OCW2 and OCW3. These command words can be issued at any time during the operation.

6 Operation Control Word 1 (OCW1): OCW1 sets and cleans the mask bits in the interrupt mask register (IMR). The format of OCW1 is given below: M 7 M 6 M 5 M 4 M 3 M 2 M 1 M 0 M 7 M 0 represents the eight mask bits. If M i = 1 corresponding Interrupt Mask is Set or the interrupt request is masked (inhibited). If M i = 0 corresponding Interrupt Mask is Reset or the interrupt request is unmasked or enabled. The OCW1 control word is issued to odd address, i.e., address with A 0 = 1. There is no ambiguity in ICW2, ICW3, ICW4 and OCW1 all using the odd address because the initialization words must always follow ICW1 as detected by the initialization sequence and an output to OCW1 cannot occur in the middle of this sequence. In between ICWs, OCW1 will not be accepted. Masking an IR channel does not affect the other channel operation. OCW2 and OCW3 :( Operation Control Word 2 and 3) Both the operation control words, OCW2 & OCW3, are used for controlling the mode of the 8259A and receiving end of interrupt (EOI) command. These control words are sent to even address, i.e., address with A 0 = 0. There is no ambiguity in OCW2, OCW3 and ICW1 as all are issued to even address. OCW2 is distinguished from OCW3 by the content of bit D 3 of the control words. If bit D 3 is 0, the data byte is considered as OCW2, and if it is 1, it is considered as OCW3. Both OCW2 &CCW3 are

7 distinguished from ICW1, which also uses the even address by the content of bit D4 of the control word. If bit D 4 is 1, it is considered as ICW1. If bit D 4 is 0, then the byte is considered as OCW2 or OCW3 according to bit D 3.

sequence is not needed. (ROM space). Another application is to use the poll mode to expand the number of priority levels to more than 64.

sequence is not needed. (ROM space). Another application is to use the poll mode to expand the number of priority levels to more than 64. Lecture-55 Poll Command: In this mode the INT output is not used for the microprocessor internal interrupt enable F/F is reset, disabling its interrupt input, service to device is achieved by software