Course Catalog - All Courses

Size: px
Start display at page:

Download "Course Catalog - All Courses"

Transcription

1 Course Catalog - All Courses Library Part Creation in the Xpedition Flow Categories: DxDesigner/xDX Designer, Expedition/Xpedition Products: Component Creation and Library Management The xdm Library Tools course will give you the skills necessary to create, protect, add to, and change the different data types in your Central Library. Longmont, Colorado, Dates: Oct to Nov , Cost: 3500 USD Singapore, Singapore, Dates: Nov to Nov , Cost: 2500 USD Munich, Germany, Dates: Dec to Dec , Cost: 2600 EUR Shanghai, China, Dates: Oct to Oct , Cost: CNY Beijing, China, Dates: Jan to Jan , Cost: CNY Artist Link Quick Start for Eldo and Questa ADMS Categories: Eldo, Questa ADMS This course is for verification engineers who are using UVM to code complex testbenches and stimulus for digital designs including registers. And have had some experience or training, but now need to know more about the Register Model Layer. After completing this course, engineers will be able to create and integrate the register model layer into their verification environment, use the register model to write reusable and maintainable sequences writing to the DUT, and gather functional coverage information about register accesses. C++ for Hardware Design Categories: HDL & Other Languages This course teaches you key C++ syntax and concepts with a focus on preparing you to be able to use C++ for high-level hardware synthesis. This course is meant as a prerequisite for the C++ Coding Guidelines for Catapult C Synthesis course. CAD Embedded CFD On-Demand Training Library Categories: FloEFD Products: FloEFD for Solid Edge The CAD Embedded CFD On-Demand Training Library offers a portfolio of learning paths for the FloEFD family of products. Calibre Advanced Topics: Mastering Calibre eqdrc Products: Calibre nmdrc Calibre eqdrc represents an important breakthrough in physical verification, making it possible for anyone performing design rule and LVS checks to truly do more with less. Beijing, China, Dates: Oct to Oct , Cost: 6444 CNY Hsinchu City, Taiwan, China, Dates: Oct to Nov , Cost: 900 USD Hsinchu City, Taiwan, China, Dates: Dec to Dec , Cost: 900 USD Calibre Advanced Topics: nmlvs Debug Case Studies Products: Calibre nmlvs Layout Versus Schematic (LVS) verification has always played a critical role in the IC design process. Calibre nmlvs continues to be the pre-eminent tool for this task. Recent Calibre enhancements have significantly extended the tool s capabilities and have helped to streamline the LVS debugging task. This course will introduce you to all of these new features through a series of LVS case studies. Hsinchu City, Taiwan, China, Dates: Nov to Nov , Cost: 300 USD

2 Calibre Advanced Topics: Writing PERC Rules Products: Calibre PERC Reliability Verification Solution, Calibre RVE This course will help you understand the wide breadth of problem areas addressed by Calibre PERC, including ESD, advanced ERC, multiple power domains, point-to-point resistance, and current density. Shanghai, China, Dates: Oct to Oct , Cost: 6444 CNY Tokyo, Japan, Dates: Dec to Dec , Cost: JPY Hsinchu City, Taiwan, China, Dates: Nov to Nov , Cost: 900 USD Calibre DESIGNrev Scripting Products: Calibre DESIGNrev This class teaches students how to create custom Calibre DRV scripts and batch files that can be used to analyze and manipulate layout data. This class also teaches students how to extend the Calibre DRV GUI to obtain user input, display results from running DRV scripts, and add menus and menu items to invoke the scripts they write in class. The course presents a number of practical examples that demonstrate how DRV scripting can be leveraged to improve the chip design process. Hsinchu City, Taiwan, China, Dates: Nov to Nov , Cost: 300 USD Calibre Fundamentals: DESIGNrev Products: Calibre nmlvs, Calibre DESIGNrev, Calibre nmdrc This course will teach you to analyze, compare, and manipulate layout data using Calibre DESIGNrev, Calibre s state-of-the-art layout viewer. Hsinchu City, Taiwan, China, Dates: Nov to Nov , Cost: 300 USD Calibre Fundamentals: Performing DRC/LVS Products: Calibre LFD, Calibre DESIGNrev Learn how to leverage the full power of Calibre nmdrc and Calibre nmlvs by attending the Calibre Fundamentals: Performing DRC/LVS course. This course will teach you to effectively use Mentor Graphics Calibre nmdrdc and Calibre LVS software in your layout verification flow and will empower you to analyze DRC and LVS results successfully in coordination with a layout editor. The lecture modules will guide you through the various concepts underlying state-of-the-art layout verification techniques and specific aspects of the Calibre nmdrc and Calibre nmlvs toolset. Tokyo, Japan, Dates: Nov to Nov , Cost: JPY Osaka, Japan, Dates: Dec to Dec , Cost: JPY Shanghai, China, Dates: Dec to Dec , Cost: 8592 CNY Hsinchu City, Taiwan, China, Dates: Dec to Dec , Cost: 600 USD Tokyo, Japan, Dates: Oct to Oct , Cost: JPY Calibre Fundamentals: Performing DRC/LVS with Virtuoso Products: Calibre nmlvs, Calibre nmdrc This course will teach you to effectively use Calibre nmdrc and Calibre nmlvs software in your layout verification flow and will empower you to analyze DRC and LVS results successfully in coordination with a layout editor. Calibre Fundamentals: Writing DRC/LVS Rules Products: Calibre LFD, Calibre DESIGNrev This course will teach you to effectively write and maintain Calibre nmdrc and nmlvs rule decks for your semiconductor processes. In this class, you will extensively study the Standard Verification Rule Format (SVRF) language used in Calibre rule decks. The lecture modules will guide you through the various concepts underlying state-of-the-art layout verification techniques and specific aspects of the Calibre toolset. Hands-on lab exercises will reinforce lecture topics and provide you with rule writing experience under the guidance of our industry expert instructors. Shanghai, China, Dates: Nov to Nov , Cost: 8592 CNY Hsinchu City, Taiwan, China, Dates: Nov to Nov , Cost: 900 USD Seoul, Korea, Dates: Oct to Oct , Cost: KRW

3 Seoul, Korea, Dates: Nov to Nov , Cost: KRW Munich, Germany, Dates: Oct to Oct , Cost: 2600 EUR Calibre RET/OPC Basics Products: Calibre nmopc, Calibre OPCverify The Calibre RET/OPC Basics course will help you understand and maintain Calibre rule decks for RET/OPC applications using Calibre s Standard Verification Rule Format (SVRF) language and the Tcl programming language. Calibre Training Library The Calibre library contains a collection of learning paths that will help you master using the tools and the development of application-specific code. Calibre TVF Products: Calibre LFD, Calibre DESIGNrev This course will help you unleash the powers of TVF to make your SVRF files more compact, easier to maintain, and more powerful. Using several examples, you will learn how to incorporate TVF functionality into your rule files to make writing SVRF rules easier. Hsinchu City, Taiwan, China, Dates: Nov to Nov , Cost: 300 USD Live online, Dates: Nov to Nov , Cost: 650 EUR Seoul, Korea, Dates: Oct to Oct , Cost: KRW Calibre xrc Parasitic Extraction Products: Calibre xrc This course presents the most in-depth coverage of these topics available, extending your knowledge base far beyond existing documentation. Attendees should see immediate ROI in terms of both ramp-up time with the Calibre xrc tools and effectiveness. Hsinchu City, Taiwan, China, Dates: Jan to Jan , Cost: 300 USD Shanghai, China, Dates: Oct to Oct , Cost: 4296 CNY Calibre Calibre Advanced Topics: Writing PERC Rules (Virtual Instructor-Led Training Series) Products: Calibre PERC Reliability Verification Solution [if gte mso 9]><xml><o:OfficeDocumentSettings> <o:relyonvml/> <o:allowpng/> </o:officedocumentsettings></xml><![endif]offered as two-hour segments once a week, spread over four weeks, this course will help you understand the wide breadth of problem areas addressed by Calibre PERC, including ESD, advanced ERC, multiple power domains, point-to-point resistance, and current density[if gte mso 9]><xml><w:WordDocument> <w:view>normal</w:view> <w:zoom>0</w:zoom> <w:trackmoves/> <w:trackformatting/> <w:punctuationkerning/> <w:validateagainstschemas/> <w:saveifxmlinvalid>false</w:saveifxmlinvalid> <w:ignoremixedcontent>false</w:ignoremixedcontent> <w:alwaysshowplaceholdertext>false</w:alwaysshowplaceholdertext> <w:donotpromoteqf/> <w:lidthemeother>en-us</w:lidthemeother> <w:lidthemeasian>x-none</w:lidthemeasian> <w:lidthemecomplexscript>x-none</w:lidthemecomplexscript> <w:compatibility> <w:breakwrappedtables/> <w:snaptogridincell/> <w:wraptextwithpunct/> <w:useasianbreakrules/> <w:dontgrowautofit/> <w:splitpgbreakandparamark/> <w:enableopentypekerning/> <w:dontflipmirrorindents/> <w:overridetablestylehps/> </w:compatibility> <m:mathpr> <m:mathfont m:val="cambria Math"/> <m:brkbin m:val="before"/> <m:brkbinsub m:val="--"/> <m:smallfrac m:val="off"/> <m:dispdef/> <m:lmargin m:val="0"/> <m:rmargin m:val="0"/> <m:defjc m:val="centergroup"/> <m:wrapindent m:val="1440"/> <m:intlim m:val="subsup"/> <m:narylim m:val="undovr"/> </m:mathpr></w:worddocument></xml><![endif][if gte mso 9]><xml><w:LatentStyles DefLockedState="false" DefUnhideWhenUsed="true" DefSemiHidden="true" DefQFormat="false" DefPriority="99" LatentStyleCount="267"> <w:lsdexception Locked="false" Priority="0" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="Normal"/> <w:lsdexception Locked="false" Priority="0" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="heading 1"/> <w:lsdexception Locked="false" Priority="9" QFormat="true" Name="heading 2"/> <w:lsdexception Locked="false" Priority="9" QFormat="true" Name="heading 3"/> <w:lsdexception Locked="false" Priority="9" QFormat="true" Name="heading 4"/> <w:lsdexception Locked="false" Priority="9" QFormat="true" Name="heading 5"/> <w:lsdexception Locked="false" Priority="9" QFormat="true" Name="heading 6"/> <w:lsdexception Locked="false" Priority="9" QFormat="true" Name="heading 7"/> <w:lsdexception Locked="false" Priority="9" QFormat="true" Name="heading 8"/> <w:lsdexception Locked="false" Priority="9" QFormat="true" Name="heading 9"/> <w:lsdexception Locked="false" Priority="39" Name="toc 1"/> <w:lsdexception Locked="false" Priority="39" Name="toc 2"/> <w:lsdexception Locked="false" Priority="39" Name="toc 3"/> <w:lsdexception Locked="false" Priority="39" Name="toc 4"/> <w:lsdexception Locked="false" Priority="39" Name="toc 5"/> <w:lsdexception Locked="false" Priority="39" Name="toc 6"/> <w:lsdexception Locked="false" Priority="39" Name="toc 7"/> <w:lsdexception Locked="false" Priority="39" Name="toc 8"/> <w:lsdexception Locked="false" Priority="39" Name="toc 9"/> <w:lsdexception Locked="false" Priority="0" Name="header"/> <w:lsdexception Locked="false" Priority="35" QFormat="true" Name="caption"/> <w:lsdexception Locked="false" Priority="10" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="Title"/> <w:lsdexception Locked="false" Priority="1" Name="Default Paragraph Font"/> <w:lsdexception Locked="false" Priority="11" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="Subtitle"/> <w:lsdexception Locked="false" Priority="22" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="Strong"/> <w:lsdexception Locked="false" Priority="20" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="Emphasis"/> <w:lsdexception Locked="false" Priority="59" SemiHidden="false" UnhideWhenUsed="false" Name="Table Grid"/> <w:lsdexception Locked="false" UnhideWhenUsed="false" Name="Placeholder Text"/> <w:lsdexception Locked="false" Priority="1" SemiHidden="false" UnhideWhenUsed="false"

4 QFormat="true" Name="No Spacing"/> <w:lsdexception Locked="false" Priority="60" SemiHidden="false" UnhideWhenUsed="false" Name="Light Shading"/> <w:lsdexception Locked="false" Priority="61" SemiHidden="false" UnhideWhenUsed="false" Name="Light List"/> <w:lsdexception Locked="false" Priority="62" SemiHidden="false" UnhideWhenUsed="false" Name="Light Grid"/> <w:lsdexception Locked="false" Priority="63" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Shading 1"/> <w:lsdexception Locked="false" Priority="64" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Shading 2"/> <w:lsdexception Locked="false" Priority="65" SemiHidden="false" UnhideWhenUsed="false" Name="Medium List 1"/> <w:lsdexception Locked="false" Priority="66" SemiHidden="false" UnhideWhenUsed="false" Name="Medium List 2"/> <w:lsdexception Locked="false" Priority="67" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 1"/> <w:lsdexception Locked="false" Priority="68" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 2"/> <w:lsdexception Locked="false" Priority="69" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 3"/> <w:lsdexception Locked="false" Priority="70" SemiHidden="false" UnhideWhenUsed="false" Name="Dark List"/> <w:lsdexception Locked="false" Priority="71" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful Shading"/> <w:lsdexception Locked="false" Priority="72" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful List"/> <w:lsdexception Locked="false" Priority="73" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful Grid"/> <w:lsdexception Locked="false" Priority="60" SemiHidden="false" UnhideWhenUsed="false" Name="Light Shading Accent 1"/> <w:lsdexception Locked="false" Priority="61" SemiHidden="false" UnhideWhenUsed="false" Name="Light List Accent 1"/> <w:lsdexception Locked="false" Priority="62" SemiHidden="false" UnhideWhenUsed="false" Name="Light Grid Accent 1"/> <w:lsdexception Locked="false" Priority="63" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Shading 1 Accent 1"/> <w:lsdexception Locked="false" Priority="64" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Shading 2 Accent 1"/> <w:lsdexception Locked="false" Priority="65" SemiHidden="false" UnhideWhenUsed="false" Name="Medium List 1 Accent 1"/> <w:lsdexception Locked="false" UnhideWhenUsed="false" Name="Revision"/> <w:lsdexception Locked="false" Priority="34" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="List Paragraph"/> <w:lsdexception Locked="false" Priority="29" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="Quote"/> <w:lsdexception Locked="false" Priority="30" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="Intense Quote"/> <w:lsdexception Locked="false" Priority="66" SemiHidden="false" UnhideWhenUsed="false" Name="Medium List 2 Accent 1"/> <w:lsdexception Locked="false" Priority="67" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 1 Accent 1"/> <w:lsdexception Locked="false" Priority="68" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 2 Accent 1"/> <w:lsdexception Locked="false" Priority="69" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 3 Accent 1"/> <w:lsdexception Locked="false" Priority="70" SemiHidden="false" UnhideWhenUsed="false" Name="Dark List Accent 1"/> <w:lsdexception Locked="false" Priority="71" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful Shading Accent 1"/> <w:lsdexception Locked="false" Priority="72" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful List Accent 1"/> <w:lsdexception Locked="false" Priority="73" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful Grid Accent 1"/> <w:lsdexception Locked="false" Priority="60" SemiHidden="false" UnhideWhenUsed="false" Name="Light Shading Accent 2"/> <w:lsdexception Locked="false" Priority="61" SemiHidden="false" UnhideWhenUsed="false" Name="Light List Accent 2"/> <w:lsdexception Locked="false" Priority="62" SemiHidden="false" UnhideWhenUsed="false" Name="Light Grid Accent 2"/> <w:lsdexception Locked="false" Priority="63" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Shading 1 Accent 2"/> <w:lsdexception Locked="false" Priority="64" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Shading 2 Accent 2"/> <w:lsdexception Locked="false" Priority="65" SemiHidden="false" UnhideWhenUsed="false" Name="Medium List 1 Accent 2"/> <w:lsdexception Locked="false" Priority="66" SemiHidden="false" UnhideWhenUsed="false" Name="Medium List 2 Accent 2"/> <w:lsdexception Locked="false" Priority="67" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 1 Accent 2"/> <w:lsdexception Locked="false" Priority="68" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 2 Accent 2"/> <w:lsdexception Locked="false" Priority="69" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 3 Accent 2"/> <w:lsdexception Locked="false" Priority="70" SemiHidden="false" UnhideWhenUsed="false" Name="Dark List Accent 2"/> <w:lsdexception Locked="false" Priority="71" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful Shading Accent 2"/> <w:lsdexception Locked="false" Priority="72" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful List Accent 2"/> <w:lsdexception Locked="false" Priority="73" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful Grid Accent 2"/> <w:lsdexception Locked="false" Priority="60" SemiHidden="false" UnhideWhenUsed="false" Name="Light Shading Accent 3"/> <w:lsdexception Locked="false" Priority="61" SemiHidden="false" UnhideWhenUsed="false" Name="Light List Accent 3"/> <w:lsdexception Locked="false" Priority="62" SemiHidden="false" UnhideWhenUsed="false" Name="Light Grid Accent 3"/> <w:lsdexception Locked="false" Priority="63" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Shading 1 Accent 3"/> <w:lsdexception Locked="false" Priority="64" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Shading 2 Accent 3"/> <w:lsdexception Locked="false" Priority="65" SemiHidden="false" UnhideWhenUsed="false" Name="Medium List 1 Accent 3"/> <w:lsdexception Locked="false" Priority="66" SemiHidden="false" UnhideWhenUsed="false" Name="Medium List 2 Accent 3"/> <w:lsdexception Locked="false" Priority="67" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 1 Accent 3"/> <w:lsdexception Locked="false" Priority="68" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 2 Accent 3"/> <w:lsdexception Locked="false" Priority="69" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 3 Accent 3"/> <w:lsdexception Locked="false" Priority="70" SemiHidden="false" UnhideWhenUsed="false" Name="Dark List Accent 3"/> <w:lsdexception Locked="false" Priority="71" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful Shading Accent 3"/> <w:lsdexception Locked="false" Priority="72" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful List Accent 3"/> <w:lsdexception Locked="false" Priority="73" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful Grid Accent 3"/> <w:lsdexception Locked="false" Priority="60" SemiHidden="false" UnhideWhenUsed="false" Name="Light Shading Accent 4"/> <w:lsdexception Locked="false" Priority="61" SemiHidden="false" UnhideWhenUsed="false" Name="Light List Accent 4"/> <w:lsdexception Locked="false" Priority="62" SemiHidden="false" UnhideWhenUsed="false" Name="Light Grid Accent 4"/> <w:lsdexception Locked="false" Priority="63" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Shading 1 Accent 4"/> <w:lsdexception Locked="false" Priority="64" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Shading 2 Accent 4"/> <w:lsdexception Locked="false" Priority="65" SemiHidden="false" UnhideWhenUsed="false" Name="Medium List 1 Accent 4"/> <w:lsdexception Locked="false" Priority="66" SemiHidden="false" UnhideWhenUsed="false" Name="Medium List 2 Accent 4"/> <w:lsdexception Locked="false" Priority="67" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 1 Accent 4"/> <w:lsdexception Locked="false" Priority="68" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 2 Accent 4"/> <w:lsdexception Locked="false" Priority="69" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 3 Accent 4"/> <w:lsdexception Locked="false" Priority="70" SemiHidden="false" UnhideWhenUsed="false" Name="Dark List Accent 4"/> <w:lsdexception Locked="false" Priority="71" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful Shading Accent 4"/> <w:lsdexception Locked="false" Priority="72" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful List Accent 4"/> <w:lsdexception Locked="false" Priority="73" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful Grid Accent 4"/> <w:lsdexception Locked="false" Priority="60" SemiHidden="false" UnhideWhenUsed="false" Name="Light Shading Accent 5"/> <w:lsdexception Locked="false" Priority="61" SemiHidden="false" UnhideWhenUsed="false" Name="Light List Accent 5"/> <w:lsdexception Locked="false" Priority="62" SemiHidden="false" UnhideWhenUsed="false" Name="Light Grid Accent 5"/> <w:lsdexception Locked="false" Priority="63" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Shading 1 Accent 5"/> <w:lsdexception Locked="false" Priority="64" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Shading 2 Accent 5"/> <w:lsdexception Locked="false" Priority="65" SemiHidden="false" UnhideWhenUsed="false" Name="Medium List 1 Accent 5"/> <w:lsdexception Locked="false" Priority="66" SemiHidden="false" UnhideWhenUsed="false" Name="Medium List 2 Accent 5"/> <w:lsdexception Locked="false" Priority="67" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 1 Accent 5"/> <w:lsdexception Locked="false" Priority="68" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 2 Accent 5"/> <w:lsdexception Locked="false" Priority="69" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 3 Accent 5"/> <w:lsdexception Locked="false" Priority="70" SemiHidden="false" UnhideWhenUsed="false" Name="Dark List Accent 5"/> <w:lsdexception Locked="false" Priority="71" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful Shading Accent 5"/> <w:lsdexception Locked="false" Priority="72" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful List Accent 5"/> <w:lsdexception Locked="false" Priority="73" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful Grid Accent 5"/> <w:lsdexception Locked="false" Priority="60" SemiHidden="false" UnhideWhenUsed="false" Name="Light Shading Accent 6"/> <w:lsdexception Locked="false" Priority="61" SemiHidden="false" UnhideWhenUsed="false" Name="Light List Accent 6"/> <w:lsdexception Locked="false" Priority="62" SemiHidden="false" UnhideWhenUsed="false" Name="Light Grid Accent 6"/> <w:lsdexception Locked="false" Priority="63" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Shading 1 Accent 6"/> <w:lsdexception Locked="false" Priority="64" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Shading 2 Accent 6"/> <w:lsdexception Locked="false" Priority="65" SemiHidden="false" UnhideWhenUsed="false" Name="Medium List 1 Accent 6"/> <w:lsdexception Locked="false" Priority="66" SemiHidden="false" UnhideWhenUsed="false" Name="Medium List 2 Accent 6"/> <w:lsdexception Locked="false" Priority="67" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 1 Accent 6"/> <w:lsdexception Locked="false" Priority="68" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 2 Accent 6"/> <w:lsdexception Locked="false" Priority="69" SemiHidden="false" UnhideWhenUsed="false" Name="Medium Grid 3 Accent 6"/> <w:lsdexception Locked="false" Priority="70" SemiHidden="false" UnhideWhenUsed="false" Name="Dark List Accent 6"/> <w:lsdexception Locked="false" Priority="71" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful Shading Accent 6"/> <w:lsdexception Locked="false" Priority="72" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful List Accent 6"/> <w:lsdexception Locked="false" Priority="73" SemiHidden="false" UnhideWhenUsed="false" Name="Colorful Grid Accent 6"/> <w:lsdexception Locked="false" Priority="19" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="Subtle Emphasis"/> <w:lsdexception Locked="false" Priority="21" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="Intense Emphasis"/> <w:lsdexception Locked="false" Priority="31" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="Subtle Reference"/> <w:lsdexception Locked="false" Priority="32" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="Intense Reference"/> <w:lsdexception Locked="false" Priority="33" SemiHidden="false" UnhideWhenUsed="false" QFormat="true" Name="Book Title"/> <w:lsdexception

5 Locked="false" Priority="37" Name="Bibliography"/> <w:lsdexception Locked="false" Priority="39" QFormat="true" Name="TOC Heading"/> </w:latentstyles></xml><![endif][if gte mso 10]><style>/* Style Definitions */ table.msonormaltable {mso-style-name:"table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; fontsize:10.0pt; font-family:"times New Roman","serif";}</style><![endif] Calibre Advanced Topics: Mastering PERC Products: Calibre PERC Reliability Verification Solution This course will help you understand the wide breadth of problem areas addressed by Calibre PERC, including ESD, advanced ERC, multiple power domains, layout point-topoint resistance, and layout current density. The course will introduce you to the use of this powerful tool and will provide a basic understanding of setting up and running Calibre PERC jobs. Calibre PERC concepts will be demonstrated through a collection of detailed case studies. Students will be able to explore Calibre PERC job options and debugging techniques through the use of hands-on lab exercises. The course includes a Calibre overview module for those students not familiar with Calibre applications. Live online, Dates: Dec to Dec , Cost: 650 EUR Calibre Advanced Topics: Multi Patterning Products: Calibre DESIGNrev, Calibre Multi-Patterning, Calibre nmdrc, Calibre RVE Starting with the 20nm processing node, the use of two masks to print a single layer becomes a requirement because of lithography issues. This course will help you understand the impact of double patterning on your designs and how to use Calibre to find and fix layout problems associated with this approach. Hsinchu City, Taiwan, China, Dates: Jan to Jan , Cost: 600 USD Shanghai, China, Dates: Oct to Oct , Cost: 4296 CNY Singapore, Singapore, Dates: Oct to Oct , Cost: 1000 USD Hsinchu City, Taiwan, China, Dates: Oct to Oct , Cost: 600 USD Calibre Pattern Matching The Calibre Pattern Matching course will provide all of the information you need to create and use layout patterns. This course will show you how to use patterns to streamline DRC and minimize RET hot spots. Hsinchu City, Taiwan, China, Dates: Oct to Oct , Cost: 300 USD Hsinchu City, Taiwan, China, Dates: Jan to Jan , Cost: 300 USD Capital Analysis Core This course demonstrates how to use the analysis tools in the Capital Analysis products. Capital Analysis Modeling This course was developed to equip you with an introduction to the Analysis model building tool. Capital Component and Symbol Managment The Capital component and symbol management course will provide users with the ability to create and maintain a component and symbol library for use within the Capital toolset. Hands-on lab exercises will guide students through the steps required to create a variety of component types and symbols used in the creation of a wire harness.. Capital Engineer 1 This course introduces you to the basic and more complex functionality within the Capital Harness Classic product. Capital Engineer 2

6 This course will help you advance your skills by introducing you to more complex procedures available within the Capital Harness Classic tool. Capital FormBoard XC This course will teach you to create form board drawings based on the Harness XC design. Students will learn how to manipulate a copy of the original harness design using Form board functionality such as full scale length and width representation, inserting bends, rotating harness bundles and placing plan and end symbol views. Capital Harness Classic System Administration Products: Capital Harness Classic The Capital Harness system admin course takes users through the installation fo the Capital Harness Classic tool. Useres will learn how to set system parameters, define user accounts and set tool preferences. Capital Harness MPM Products: Capital Harness MPM This course will guide users through the tools required to create a structured bill of materials for an example harness. Capital Harness TVM Products: Capital Harness TVM The Capital Harness TVM course was developed to equip the participant with the ability to create harness tasks, component costs, build times and other measurements that make up an assembly process. Capital Harness XC Products: Capital HarnessXC This course introduces you to the basic and more complex functionality within the Capital Harness XC product. This tool provides a seamless transition of data from Capital Logic or Integrator into Capital Harness XC. Capital Integrator This course will equip you with a good understanding of the complete Capital Integrator functionalities. Shanghai, China, Dates: Oct to Oct , Cost: 5214 CNY Capital Labor Costing This course was developed to equip the participant with the ability to create costing reports based on the labour requirement for the creation of a harness. Capital Logic Aero This course provides a detailed look at the Capital Logic toolset from an aerospace perspective, taking the participant from basic to more complex functional designs.

7 Capital Logic Generative Products: Capital Logic This course was developed to provide a detailed look at the Capital Logic toolset, taking the participant from the basic concepts through the more complex functional designs. Capital Logic Interactive Products: Capital Logic This course was developed to provide a detailed look at the capital logic toolset, taking the participant from the basic through to the more complex wiring designs. Capital Material Costing This course will equip you with the ability to create costing reports based on the material costs for the creation of a harness. Capital ModularXC (Functional and Production) Products: Capital ModularXC The Capital ModularXC course was developed to provide users with a comprehensive understanding of modular functionality within the Capital toolset. It combines functional and production module design into one class, replacing the previous separate classes (which are no longer supported). Capital Publisher Aero Products: Capital Publisher The Capital Publisher Aero course was developed to equip the participant with the ability to generate service documentation based on predefined system diagrams. Capital Publisher Automotive Products: Capital Publisher The Capital Publisher Automotive course was developed to equip the participant with the ability to generate service documentation based on automotive design content Capital Systems Administration This course will help system administrators to understand the steps involved in the installation and maintenance of the Capital Harness Classic product, on a progress database environment. Capital Topology Products: Capital Logic The Capital topology course has been created to introduce users to the basic and more complex functionality within the Capital Topology product. This tool provides users with the ability to create a topological view of a vehicle and associate wiring diagrams to this view. Wire routing scenarios can be run and rules can be implemented to ensure wires take a specific route. Capital Training Library

8 Products: Enterprise Tools, Capital Devices, Capital Harness MPM, Capital Harness TVM, Capital Level Manager, Capital ModularXC, Capital Publisher, Capital Systems, Capital Workbooks, Capital FormboardXC, Capital Harness Classic, Capital HarnessXC, Capital Integrator, Capital Logic Courses include interactive videos, written course materials, knowledge checks, and hands-on labs through the Mentor Graphics Virtual Lab platform. This platform utilizes a test environment where you can work with the tools in a hands-on setting, allowing you to implement the skills you're gaining along the way. Catapult High-Level Synthesis Training Library Categories: Catapult Products: Catapult HLS The Catapult High-Level Synthesis (HLS) library contains a set of modules to introduce Engineers to HLS and the use of Catapult for hardware design. Constraint Management in the Xpedition Flow Products: Constraint Management This is a course with great technical content. It will teach you how to get the most out of Constraint Manager in only 2 days in-class training and 4 days of Live Online Training. This course is tested and offered on Windows 7 professional only. Singapore, Singapore, Dates: Oct to Oct , Cost: 1000 USD Meudon, France, Dates: Dec to Dec , Cost: 1300 EUR Herzliya, Israel, Dates: Nov to Nov , Cost: 3324 ILS Sesto San Giovanni (MI), Italy, Dates: Nov to Nov , Cost: 1300 EUR Live online, Dates: Dec to Dec , Cost: 1400 USD Munich, Germany, Dates: Dec to Dec , Cost: 1300 EUR DMS Librarian for DxD /EE PCB Flow in a DMS Environment Categories: DxDesigner/xDX Designer, Expedition/Xpedition Products: Design Review, Schematic Design This course will give you the skills necessary to create, add to and change the different data types in your Central Library when managed by DMS. DxDesigner for Expedition Basics Categories: DxDesigner/xDX Designer, Expedition/Xpedition Products: Schematic Design, PCB Layout The DxDesigner for Expedition is a self-paced class that will help you improve your knowledge and skills on the front end of the design process. You will gain proficiency in schematic capture with DxDesigner, part selection using DxDataBook, and much more. You will also learn how to prepare your final schematic for interfacing with the Mentor Graphics Expedition PCB layout tool. EDM Design EDM Library for Librarians Products: Component Creation and Library Management This course will give you the skills necessary to create, add to and change the different data types in your Central Library when managed by EDM Library Server. The lecture modules build on the knowledge gained from Library Part Creation in the Xpedition Flow training to best interface library objects into a EDM Library Server managed environment. EDM Server for Administrators Categories: PADS Products: PADS PCB Design Software

9 This course will give you the knowledge necessary to install, configure and migrate an EDM Server environment with EDM Library (previously known as DMS) and EDM Design, including the underlying relational database and supporting 3rd-party software. Live online, Dates: Oct to Oct , Cost: 1680 GBP Eldo Platform Essentials for Artist Link Users Categories: Eldo This advanced course will help you improve the skills needed to maximize your productivity and usage of Eldo when using it within Cadence ADE through the Artist Link interface The subjects covered are similar to the ones in the Eldo Platform Essentials Training for all what is about pure analog simulation, but with an extra layer to present how to use most of these features through the Artist link interface, so dedicated to users not familiar with Artist Link and who are using in Cadence ADE PDKs delivered for Eldo. Eldo Platform On-Demand Training Library Categories: Eldo Products: Eldo Platform The contents of this library will help you learn about the Eldo Platform's rich feature set for accurate, fast interactive analog IC design and verification. Eldo Platform Advanced Noise Analyses Categories: Eldo Products: EZwave This session is mainly dedicated to performing noise analyses. In addition, it also covers FFT analysis and Digital Signal Processing, as well as S-parameters extraction and computation. Eldo Platform Advanced Statistical Analyses Categories: Eldo Products: EZwave This advanced course will help you improve the skills needed to maximize your usage of Eldo (now renamed Eldo Platform ) with mastering the most advanced variability analyses. Eldo Platform Control Language (ECL) Categories: Eldo Products: EZwave The Eldo Control Language course will help you to master the extended language capabilities in Eldo (now renamed Eldo Platform ), for a comprehensive and user-defined control of a set of simulations. Eldo Platform Unique Advanced Features Categories: Eldo Products: EZwave This course will make you experience all advanced analyses that make Eldo (now renamed Eldo Platform ) a key differentiator. Eldo Platform Basic Categories: Eldo This course will help you acquire the skills needed to perform effective analog simulations with Eldo. Eldo Platform Essentials Categories: Eldo

10 This advanced course will help you improve the skills needed to maximize your productivity and usage of Eldo (now renamed Eldo Platform ), during either a design phase or a verification process. Electronics Cooling Simulation and Testing Library Categories: FloTHERM, MicRed Products: FloTHERM Flexx, FloTHERM IC, FloTHERM PACK, FloTHERM PCB, FloTHERM XT, T3Ster, TeraLED Electronics Cooling Simulation and Testing Training Library offers a portfolio of learning paths for MicReD and the FloTHERM family of products. Emulation Training Library Categories: Emulation Products: Veloce2 Emulator Learn modeling, compilation and runtime debug aspects of emulation with Veloce. This training is applicable to both Veloce2 and Veloce Strato platforms. Expedition PCB Advanced Packaging This course covers all the necessary skills required to use CES efficiently and effectively in DxDesigner-Expedition and Design Capture-Expedition flows. Expedition Training Library (7.9.5) Categories: DxDesigner/xDX Designer, Expedition/Xpedition Products: PCB Layout A complete portfolio of learning paths for schematic design, constraint entry, PCB Layout and library management using Expediton Enterprise software. FloEFD for Catia V5: Introductory Categories: FloEFD Products: FloEFD This course is designed to provide new users of FloEFD for CATIA V5 with a background sufficient for tackling a wide range of flow and thermal analysis problems. The main goals of the course are to make the student familiar with the operation and functionality of FloEFD for CATIA V5 and to instill good engineering modeling practices. Meudon, France, Dates: Nov to Nov , Cost: 1300 EUR Live online, Dates: Nov to Nov , Cost: 1400 USD FloEFD for Creo: Introductory Categories: FloEFD Products: FloEFD This course is designed to provide new users of FloEFD Creo with a background sufficient for tackling a wide range of flow and thermal analysis problems. The main goals of the course are to make the student familiar with the operation and functionality of FloEFD Creo and to instill good engineering modeling practices. Live online, Dates: Oct to Oct , Cost: 1400 USD FloEFD for NX: Introductory Categories: FloEFD Products: FloEFD NX This course is designed to provide new users of FloEFD for NX with a background sufficient for tackling a wide range of flow and thermal analysis problems. The main goals of the course are to make the student familiar with the operation and functionality of FloEFD and to instill good engineering modeling practices. Frankfurt, Germany, Dates: Nov to Nov , Cost: 1300 EUR FloEFD for Solid Edge: Introductory Categories: FloEFD Products: FloEFD for Solid Edge

11 This course is designed to provide new users of FloEFD for Solid Edge with a background sufficient for tackling a wide range of flow and thermal analysis problems. The main goals of the course are to make sure the student is familiar with the operation and functionality of FloEFD for Solid Edge and to instill good engineering modeling practices. Live online, Dates: Oct to Oct , Cost: 1300 EUR Live online, Dates: Oct to Nov , Cost: 1400 USD FloEFD: Introductory Categories: FloEFD Products: FloEFD This course is designed to provide new users of FloEFD with a background sufficient for tackling a wide range of flow and thermal analysis problems. The main goals of the course are to make the student familiar with the operation and functionality of FloEFD and to instill good engineering modeling practices. Live online, Dates: Oct to Oct , Cost: 1400 USD Frankfurt, Germany, Dates: Oct to Oct , Cost: 1300 EUR Northamptonshire, United Kingdom, Dates: Oct to Oct , Cost: 1120 GBP Live online, Dates: Nov to Nov , Cost: 1950 EUR Live online, Dates: Dec to Dec , Cost: 1950 EUR FloMASTER New User Training Categories: Flomaster Products: FloMASTER This course is designed to provide new users of FloMASTER with a background sufficient for tackling a wide range of flow analysis problems in 1D. The main goals of the course are to make the student familiar with the operation and functionality of FloMASTER and to instill good engineering modeling practices. Live online, Dates: Dec to Dec , Cost: 1120 GBP Live online, Dates: Nov to Nov , Cost: 1400 USD Frankfurt, Germany, Dates: Nov to Nov , Cost: 1300 EUR Meudon, France, Dates: Oct to Oct , Cost: 1300 EUR Northamptonshire, United Kingdom, Dates: Nov to Nov , Cost: 1120 GBP FloTHERM Categories: FloTHERM Products: FloTHERM PACK This course will teach you how to use the FloTHERM thermal analysis software. Complete with instruction and tutorial exercises, the training guides you through all aspects of model building, using SmartParts and libraries, importing data from MCAD and EDA software, sequential optimization and visualization of results. Live online, Dates: Nov to Nov , Cost: 1950 EUR Live online, Dates: Oct to Oct , Cost: 2100 USD Wilsonville, Oregon, Dates: Dec to Dec , Cost: 2100 USD Meudon, France, Dates: Nov to Nov , Cost: 1950 EUR Meudon, France, Dates: Dec to Dec , Cost: 1950 EUR Northamptonshire, United Kingdom, Dates: Nov to Nov , Cost: 1680 GBP Shanghai, China, Dates: Nov to Nov , Cost: 6444 CNY FloTHERM Advanced Categories: FloTHERM Products: FloTHERM In the FloTHERM Advanced Training course you will learn advanced troubleshooting techniques for convergence problems and gridding concerns as well as advanced modeling topics. Wilsonville, Oregon, Dates: Dec to Dec , Cost: 1400 USD Live online, Dates: Oct to Oct , Cost: 1400 USD FloTHERM Scripting Categories: FloTHERM Products: FloTHERM The Scripting for FloTHERM course will help you to take advantage of the FloXML and FloSCRIPT capabilities in FloTHERM, so that you can save time and increase accuracy when using FloTHERM for repetitive tasks.

12 FloTHERM XT Categories: FloTHERM Products: FloTHERM XT The FloTHERM XT course will teach you how to design, build and simulate simple to complicated electronics cooling related models. Marlborough, Massachusetts, Dates: Nov to Nov , Cost: 2100 USD Live online, Dates: Dec to Dec , Cost: 2100 USD Live online, Dates: Oct to Oct , Cost: 1950 EUR Shanghai, China, Dates: Dec to Dec , Cost: 7821 CNY Meudon, France, Dates: Oct to Oct , Cost: 1950 EUR Meudon, France, Dates: Dec to Dec , Cost: 1950 EUR FloTHERM XT Advanced Categories: FloTHERM Products: FloTHERM XT The FloTHERM XT Advanced training course will teach you how to use the advanced features of FloTHERM XT. FloVENT Introduction Categories: FloVENT Products: FloVENT This course is designed to familiarize new and existing users with FloVENT. Attending this training course will take you quickly up the FloVENT learning curve and help you become immediately productive in using the software. Meudon, France, Dates: Nov to Nov , Cost: 1950 EUR Shanghai, China, Dates: Nov to Nov , Cost: 6444 CNY FormalPro Categories: FormalPro Products: FormalPro FormalPro is the Mentor Graphics equivalence checking product for dramatically reducing the time required to verify ASICs and ICs. This class describes background and benefits of formal verification technology and how it applies to current ASIC design methodologies. It will teach you how to setup, compile and verify designs, and then debug and successfully correct design errors. FPGA I/O Optimization in the Xpedition Flow Products: FPGA I/O Optimization The FPGA I/O Optimization course teaches you how to manage the data and monitor the changes between the two design flows while maintaining consistency. Munich, Germany, Dates: Nov to Nov , Cost: 1300 EUR Functional Verification Training Library Categories: FPGA, HDL & Other Languages, Questa & ModelSim Products: ModelSim This library contains learning paths that help you master functional verification tools, and the development of test environments using HDL-based methodologies. Learn how to use ModelSim/Questa GUI and command line to verify and debug HDL designs in interactive mode or build batch mode scripts for fast simulations. Getting Started with Calibre Automatic Waivers Products: Calibre Auto-Waivers

13 The Getting Started with Calibre Automatic Waivers course will equip you with a basic understanding of what the Automatic Waivers tool does and how you can use it. HDL Designer Series Categories: FPGA, HDL & Other Languages Products: HDL Designer This class teaches you to use HDL Designer Series effectively in your FPGA or ASIC design process. The lecture takes you through the HDL Designer Series design flow. This includes modeling the design with both graphics and text, generating HDL, and then simulating and animating the design to verify behavior. High Speed Signal Integrity Principles, HyperLynx Products: HyperLynx Signal Integrity The Signal Integrity Principles Hands-On Workshop will help you properly manage the effects of high speed signals on today s PCB designs. HyperLynx DDRx Interface Analysis Categories: HyperLynx The HyperLynx DDRx Interface Analysis course will help you gain an in-depth understanding of DDRx interfaces and how to use the HyperLynx software to analyze signal integrity, crosstalk, and timing of DDRx in both pre- and post- layout stages of the design process. Herzliya, Israel, Dates: Oct to Oct , Cost: 3324 ILS Munich, Germany, Dates: Dec to Dec , Cost: 1300 EUR Newbury, United Kingdom, Dates: Oct to Oct , Cost: 1120 GBP Meudon, France, Dates: Nov to Nov , Cost: 1300 EUR Meudon, France, Dates: Nov to Nov , Cost: 1300 EUR Live online, Dates: Dec to Dec , Cost: 1400 USD HyperLynx DRC Categories: HyperLynx Products: HyperLynx DRC In this course will learn how to configure the rules, how to run them and how to evaluate the results and cross probe any rule violation back into your PCB. Hsinchu City, Taiwan, China, Dates: Dec to Dec , Cost: 300 USD Live online, Dates: Dec to Dec , Cost: 700 USD HyperLynx High-Speed PCB Training Library Categories: HyperLynx A collection of learning paths that cover High Speed PCB design and analysis methodology using HyperLynx family of tools. HyperLynx High-speed Serial Interface Analysis Categories: HyperLynx Products: HyperLynx Signal Integrity The HyperLynx High-speed Serial Interface Analysis course will help you learn how to use HyperLynx to analyze SERDES channels in pre and post-layout. Live online, Dates: Jan to Jan , Cost: 700 USD Hsinchu City, Taiwan, China, Dates: Dec to Dec , Cost: 300 USD Munich, Germany, Dates: Dec to Dec , Cost: 650 EUR Beijing, China, Dates: Nov to Nov , Cost: 2148 CNY Meudon, France, Dates: Nov to Nov , Cost: 650 EUR Newbury, United Kingdom, Dates: Oct to Oct , Cost: 560 GBP Hsinchu City, Taiwan, China, Dates: Oct to Oct , Cost: 300 USD

14 Live online, Dates: Nov to Nov , Cost: 700 USD HyperLynx SI Analysis Basics, HyperLynx This course will teach you how to use HyperLynx SI to analyze signal integrity, timing, crosstalk and EMI in pre- and post- layout stages of the design process. HyperLynx Signal Integrity Analysis, HyperLynx This course will teach you how to use HyperLynx SI to analyze signal integrity, timing, crosstalk and EMI in pre- and post- layout stages of the design process. Live online, Dates: Dec to Dec , Cost: 2100 USD Munich, Germany, Dates: Oct to Oct , Cost: 1950 EUR Hsinchu City, Taiwan, China, Dates: Jan to Jan , Cost: 900 USD Beijing, China, Dates: Nov to Nov , Cost: 6444 CNY Herzliya, Israel, Dates: Nov to Nov , Cost: 4986 ILS Singapore, Singapore, Dates: Oct to Oct , Cost: 1500 USD Newbury, United Kingdom, Dates: Oct to Oct , Cost: 1680 GBP Marlborough, Massachusetts, Dates: Nov to Nov , Cost: 2100 USD HyperLynx Power Integrity Analysis, HyperLynx Products: HyperLynx Power Integrity This course will help you understand the basic concepts of power distribution and delivery on a PCB, power integrity simulation, identification of power distribution problems on your PCB, and fixing these problems early in the design cycle. Marlborough, Massachusetts, Dates: Nov to Nov , Cost: 1400 USD Live online, Dates: Jan to Jan , Cost: 1400 USD Beijing, China, Dates: Nov to Nov , Cost: 4296 CNY Munich, Germany, Dates: Oct to Oct , Cost: 1300 EUR Herzliya, Israel, Dates: Nov to Nov , Cost: 3324 ILS Singapore, Singapore, Dates: Oct to Oct , Cost: 1000 USD I/O Designer This course teaches you how to manage the data and monitor the changes between the two design flows while maintaining consistency. IC Design Flow With ICstudio Categories: ICStation & ICStudio This course will provide all the knowledge needed to apply the power of ICstudio, Mentor s integrated IC design environment, to your most challenging VLSI designs. IC Design Flow With Pyxis Categories: Pyxis Products: Pyxis Layout, Pyxis Schematic IC Design Flow With Pyxis will provide all the knowledge needed to apply the power of Pyxis, Mentor s integrated IC design environment, to your most challenging VLSI designs. The course covers the full IC design flow, from capture through final layout verification and analysis. Infolytica MagNet Introductory Categories: Infolytica The MagNet Introductory Training Course will help you use MagNet more efficiently and with greater confidence. Learn to avoid common modeling mistakes and decrease simulation time while increasing simulation accuracy.

Manuel scolaire ISN.

Manuel scolaire ISN. Extrait du Icosaweb http://maths.ac-reunion.fr/lycee/isn/manuel-scolaire-isn Manuel scolaire ISN. - Lycée - ISN - Date de mise en ligne : mardi 28 août 2012 Description : Un manuel pour les élèves. Copyright

More information

Fiche Technique : Chauffage piscine pompe à chaleur MECATHERM POOL 65 Monophase 9.5kw frais de ports inclus

Fiche Technique : Chauffage piscine pompe à chaleur MECATHERM POOL 65 Monophase 9.5kw frais de ports inclus SARL Chauffage Direct 345 CHEMIN DE LA BOULINARDE LES MOTTES 26760 Beaumont Les Valence 04 75 80 21 51 http://www.chauffage-direct.fr contact@chauffage-direct.fr Fiche Technique : Chauffage piscine pompe

More information

Sales-mark.- Techn. services - R&D Staff

Sales-mark.- Techn. services - R&D Staff Sales-mark.- Techn. services - R&D Staff Job Content: Heeft u een wetenschappelijke opleiding en bent u opzoek naar een opportuniteit? Reageer dan via deze jobposting zodat we uw profiel gemakkelijk kunnen

More information

Suhrkamp / Insel. Foreign Rights. Stephan Thome God of the Barbarians - Novel. (German title: Gott der Barbaren) ca. 719 pages Clothbound 2018

Suhrkamp / Insel. Foreign Rights. Stephan Thome God of the Barbarians - Novel. (German title: Gott der Barbaren) ca. 719 pages Clothbound 2018 Stephan Thome God of the Barbarians - Novel (German title: Gott der Barbaren) ca. 719 pages Clothbound 2018 Heike Steinweg Stephan Thome, born in 1972 in Biedenkopf, studied Philosophy and Sinology at

More information

Komunikat z 6 listopada 2014

Komunikat z 6 listopada 2014 Komunikat z 6 listopada 2014 Lubuski Oddział Wojewódzki NFZ w Zielonej Górze informuje, że w dniu 04.11.2014 roku na stronie internetowej Centrali NFZ, pod adresem: www.nfz.gov.pl, zamieszczone zostały

More information

Destinazione: Londra Data: Giorni: 4 Mezzo di Trasporto: Mezzo di trasporto Costo: EURO INFORMAZIONI SUL LUOGO: Vedi Programma.

Destinazione: Londra Data: Giorni: 4 Mezzo di Trasporto: Mezzo di trasporto Costo: EURO INFORMAZIONI SUL LUOGO: Vedi Programma. Destinazione: Londra Data: 06-04-2017 Giorni: 4 Mezzo di Trasporto: Mezzo di trasporto Costo: EURO 495.00 INFORMAZIONI SUL LUOGO: Vedi Programma. PROGRAMMA DI VIAGGIO:

More information

Forma't a l'escola del Gremi d'instal ladors de Barcelona

Forma't a l'escola del Gremi d'instal ladors de Barcelona CURSO DE MEMORIAS TÉCNICAS DE DISEÑO Código: MN36 Objetivo : En este curso, se pretende conseguir que el alumno, sepa elaborar en toda su amplitud, el diseño de una instalación eléctrica desde el punto

More information

OEO035 Lo stack LAMP in Ubuntu

OEO035 Lo stack LAMP in Ubuntu Tel. +39 02 365738 info@overneteducation.it www.overneteducation.it OEO035 Lo stack LAMP in Ubuntu Durata: 3 gg Descrizione Normal 0 14 false false false IT X-NONE X-NONE Pagina 1 Il corso fornisce una

More information

Questions & Answers PDF Page 1. Oracle. 1Z0-067 Exam. Oracle Upgrade Oracle9i/10g/11g OCA OR OCP to Oracle Database Exam

Questions & Answers PDF Page 1. Oracle. 1Z0-067 Exam. Oracle Upgrade Oracle9i/10g/11g OCA OR OCP to Oracle Database Exam Questions & Answers PDF Page 1 Oracle 1Z0-067 Exam Oracle Upgrade Oracle9i/10g/11g OCA OR OCP to Oracle Database Exam Thank you for Downloading 1Z0-067 exam PDF Demo You can also Buy our 1Z0-067 Premium

More information

Jesień w lesie, grzyby niesie

Jesień w lesie, grzyby niesie Jesień w lesie, grzyby niesie

More information

Sklep z klimatem. DefSemiHidden="true" DefQFormat="false" DefPriority="99" LatentStyleCount="267">

Sklep z klimatem. DefSemiHidden=true DefQFormat=false DefPriority=99 LatentStyleCount=267> Herbata > Herbata Czarna > Model : - Producent : - DefSemiHidden="true" DefQFormat="false" DefPriority="99" LatentStyleCount="267"> UnhideWhenUsed="false" QFormat="true" Name="Normal" /> UnhideWhenUsed="false"

More information

MOC20488 Developing Microsoft SharePoint Server 2013 Core Solutions

MOC20488 Developing Microsoft SharePoint Server 2013 Core Solutions Tel. +39 02 365738 info@overneteducation.it www.overneteducation.it MOC20488 Developing Microsoft SharePoint Server 2013 Core Solutions Durata: 4.5 gg Descrizione Il corso permetterà di apprendere le abilità

More information

Forma't a l'escola del Gremi d'instal ladors de Barcelona

Forma't a l'escola del Gremi d'instal ladors de Barcelona REPARACION DE APARATOS DE LINEA BLANCA Código: MN208 Desarrollo: Inicio del curso según inscripciones Entrega de documentación Prácticas con los diferentes electrodomésticos Control de asistencia y entrega

More information

What s New in PADS

What s New in PADS What s New in PADS 2007.4 Copyright Mentor Graphics Corporation 2008 All Rights Reserved. Mentor Graphics, Board Station, ViewDraw, Falcon Framework, IdeaStation, ICX and Tau are registered trademarks

More information

Calibre Fundamentals: Writing DRC/LVS Rules. Student Workbook

Calibre Fundamentals: Writing DRC/LVS Rules. Student Workbook DRC/LVS Rules Student Workbook 2017 Mentor Graphics Corporation All rights reserved. This document contains information that is trade secret and proprietary to Mentor Graphics Corporation or its licensors

More information

Keysight U5340A FPGA Development Kit for High-Speed Digitizers

Keysight U5340A FPGA Development Kit for High-Speed Digitizers Keysight U5340A FPGA Development Kit for High-Speed Digitizers 02 Keysight U5340A FPGA Development Kit for High-Speed Digitizers - Brochure Helping You Achieve Greater Performance The FPGA Development

More information

Schematic/Design Creation

Schematic/Design Creation Schematic/Design Creation D A T A S H E E T MAJOR BENEFITS: Xpedition xdx Designer is a complete solution for design creation, definition, and reuse. Overview Creating competitive products is about more

More information

Silicon Photonics Scalable Design Framework:

Silicon Photonics Scalable Design Framework: Silicon Photonics Scalable Design Framework: From Design Concept to Physical Verification Hossam Sarhan Technical Marketing Engineer hossam_sarhan@mentor.com Objective: Scalable Photonics Design Infrastructure

More information

World Class Verilog & SystemVerilog Training

World Class Verilog & SystemVerilog Training World Class Verilog & SystemVerilog Training Sunburst Design - Expert Verilog-2001 FSM, Multi-Clock Design & Verification Techniques by Recognized Verilog & SystemVerilog Guru, Cliff Cummings of Sunburst

More information

Electrical optimization and simulation of your PCB design

Electrical optimization and simulation of your PCB design Electrical optimization and simulation of your PCB design Steve Gascoigne Senior Consultant at Mentor Graphics Zagreb, 10. lipnja 2015. Copyright CADCAM Group 2015 The Challenge of Validating a Design..

More information

Laker Custom Layout Automation System

Laker Custom Layout Automation System The Laker Custom Layout offers powerful solutions for analog, mixed-signal, memory, and custom digital IC design that address key pain points in the layout process. The Laker layout system provides an

More information

Mentor Graphics Solutions Enable Fast, Efficient Designs for Altera s FPGAs. Fall 2004

Mentor Graphics Solutions Enable Fast, Efficient Designs for Altera s FPGAs. Fall 2004 Mentor Graphics Solutions Enable Fast, Efficient Designs for Altera s FPGAs Fall 2004 Agenda FPGA design challenges Mentor Graphics comprehensive FPGA design solutions Unique tools address the full range

More information

Programmable Logic Training Courses

Programmable Logic Training Courses Programmable Logic Training Courses Course Information and Schedule March 1996 through December 1996 (Latest schedule is also available on web at http://www.xilinx.com) Who Should Attend a Training Class?

More information

Course Index Enterprise Online Training (Self Paced Education) Optio Advanced Labeling for Optio Document Designers

Course Index Enterprise Online Training (Self Paced Education) Optio Advanced Labeling for Optio Document Designers Optio Training Course Catalog Bottomline maintains an active schedule of instructor led classroom, instructor led online and selfpaced CD based training programs for Optio Enterprise and Optio Healthcare

More information

Improve Reliability With Accurate Voltage-Aware DRC. Matthew Hogan, Mentor Graphics

Improve Reliability With Accurate Voltage-Aware DRC. Matthew Hogan, Mentor Graphics Improve Reliability With Accurate Voltage-Aware DRC Matthew Hogan, Mentor Graphics BACKGROUND Consumer expectations for longer device operations at sustained performance levels means designing for reliability

More information

Galaxy Custom Designer SE The New Choice in Custom Schematic Editing and Simulation Environment

Galaxy Custom Designer SE The New Choice in Custom Schematic Editing and Simulation Environment Datasheet Galaxy Custom Designer SE The New Choice in Custom Schematic Editing and Simulation Environment Overview Galaxy Custom Designer SE is the next-generation choice for schematic entry, enabling

More information

Virtuoso - Enabled EPDA framework AIM SUNY Process

Virtuoso - Enabled EPDA framework AIM SUNY Process Virtuoso - Enabled EPDA framework AIM SUNY Process CADENCE, LUMERICAL, PHOENIX SOFTWARE Driven by our customers Cadence is the leader with Virtuoso custom design platform for electronics custom and mixed

More information

This course contains the subject matter to prepare candidates for the ivanti Certified Service Desk 2017 Administrator exam.

This course contains the subject matter to prepare candidates for the ivanti Certified Service Desk 2017 Administrator exam. Course Overview The Service Desk Administration 2017 course is a five-day training course covering topics for both administrative and design functions within the Service Desk 2017. Students will learn

More information

DIGITAL DESIGN TECHNOLOGY & TECHNIQUES

DIGITAL DESIGN TECHNOLOGY & TECHNIQUES DIGITAL DESIGN TECHNOLOGY & TECHNIQUES CAD for ASIC Design 1 INTEGRATED CIRCUITS (IC) An integrated circuit (IC) consists complex electronic circuitries and their interconnections. William Shockley et

More information

For more details, Please contact: #25, Dr. Radhakrishnan Salai, CADD Centre Building, Mylapore, Chennai

For more details, Please contact: #25, Dr. Radhakrishnan Salai, CADD Centre Building, Mylapore, Chennai For more details, Please contact: #25, Dr. Radhakrishnan Salai, CADD Centre Building, Mylapore, Chennai - 600 004. LIVEWIRE and LIVEWIRE logo are registered trademarks of CADD Centre Training Services

More information

Keysight U5340A FPGA Development Kit for High-Speed Digitizers

Keysight U5340A FPGA Development Kit for High-Speed Digitizers Keysight U5340A FPGA Development Kit for High-Speed Digitizers 02 Keysight U5340A FPGA Development Kit for High-Speed Digitizers - Brochure Helping You Achieve Greater Performance The FPGA Development

More information

PG Certificate. VLSI Design & Verification (RTL using Verilog, FPGA Design Flow & Verification) (Live Project)

PG Certificate. VLSI Design & Verification (RTL using Verilog, FPGA Design Flow & Verification) (Live Project) PG Certificate in VLSI Design & Verification (RTL using Verilog, FPGA Design Flow & Verification) (Live Project) Certificates by National Skill Development Corporation (NSDC), Ministry of Skill Development

More information

01-1 Electronic Design Automation (EDA) The use of software to automate electronic (digital and analog) design.

01-1 Electronic Design Automation (EDA) The use of software to automate electronic (digital and analog) design. 01-1 Electronic Design Automation (EDA) 01-1 Electronic Design Automation (EDA): (Short Definition) The use of software to automate electronic (digital and analog) design. Electronic Design Automation

More information

Curriculum Guide. Creo 4.0

Curriculum Guide. Creo 4.0 Curriculum Guide Creo 4.0 Live Classroom Curriculum Guide Update to Creo Parametric 4.0 from Creo Parametric 3.0 Introduction to Creo Parametric 4.0 Advanced Modeling using Creo Parametric 4.0 Advanced

More information

Microsoft Windows PowerShell v2 For Administrators

Microsoft Windows PowerShell v2 For Administrators Microsoft Windows PowerShell v2 For Administrators Course 50414 5 Days Instructor-led, Hands-on Introduction This four-day instructor-led course provides students with the knowledge and skills to leverage

More information

EE 4755 Digital Design Using Hardware Description Languages

EE 4755 Digital Design Using Hardware Description Languages EE 4755 Digital Design Using Hardware Description Languages Basic Information URL: http://www.ece.lsu.edu/v Offered by: David M. Koppelman, Room 345 ERAD Building 578-5482. koppel@ece.lsu.edu, http://www.ece.lsu.edu/koppel/koppel.html

More information

Education Brochure. Education. Accelerate your path to business discovery. qlik.com

Education Brochure. Education. Accelerate your path to business discovery. qlik.com Education Education Brochure Accelerate your path to business discovery Qlik Education Services offers expertly designed coursework, tools, and programs to give your organization the knowledge and skills

More information

Putting Curves in an Orthogonal World

Putting Curves in an Orthogonal World Putting Curves in an Orthogonal World Extending the EDA Flow to Support Integrated Photonics Masahiro Shiina October 2018 Traditional IC Design Designers & tool developers have lived in a orthogonal world

More information

Creo 3.0. Curriculum Guide

Creo 3.0. Curriculum Guide Creo 3.0 Curriculum Guide Live Classroom Curriculum Guide Update to Creo Parametric 3.0 from Creo Parametric 2.0 Introduction to Creo Parametric 3.0 Advanced Modeling using Creo Parametric 3.0 Advanced

More information

Virtuoso Layout Suite XL

Virtuoso Layout Suite XL Accelerated full custom IC layout Part of the Cadence Virtuoso Layout Suite family of products, is a connectivity- and constraint-driven layout environment built on common design intent. It supports custom

More information

Live Classroom Curriculum Guide

Live Classroom Curriculum Guide Curriculum Guide Live Classroom Curriculum Guide Creo Elements/Pro 5.0 (formerly Pro/ENGINEER Wildfire 5.0) Update from Pro/ENGINEER Wildfire 4.0 Creo Elements/Pro 5.0 (formerly Pro/ENGINEER Wildfire 5.0)

More information

The Microprocessor as a Microcosm:

The Microprocessor as a Microcosm: The Microprocessor as a Microcosm: A Hands-On Approach to VLSI Design Education David Harris David_Harris@hmc.edu November 2002 Harvey Mudd College Claremont, CA Outline Introduction Course Organization

More information

Adding Curves to an Orthogonal World

Adding Curves to an Orthogonal World Adding Curves to an Orthogonal World Extending the EDA Flow to Support Integrated Photonics Paul Double July 2018 Traditional IC Design BREXIT AHOY! Designers & tool developers have lived in a orthogonal

More information

WebEx University. WebEx University. Mastering Cisco WebEx Meeting Center. Program Overview

WebEx University. WebEx University. Mastering Cisco WebEx Meeting Center. Program Overview WebEx University WebEx University Mastering Cisco WebEx Meeting Center Program Overview Program Introduction Thank you for your interest in the Cisco WebEx Meeting Center Mastery Program. Please contact

More information

Philip Andrew Simpson. FPGA Design. Best Practices for Team-based Reuse. Second Edition

Philip Andrew Simpson. FPGA Design. Best Practices for Team-based Reuse. Second Edition FPGA Design Philip Andrew Simpson FPGA Design Best Practices for Team-based Reuse Second Edition Philip Andrew Simpson San Jose, CA, USA ISBN 978-3-319-17923-0 DOI 10.1007/978-3-319-17924-7 ISBN 978-3-319-17924-7

More information

Reuse MATLAB Functions and Simulink Models in UVM Environments with Automatic SystemVerilog DPI Component Generation

Reuse MATLAB Functions and Simulink Models in UVM Environments with Automatic SystemVerilog DPI Component Generation Reuse MATLAB Functions and Simulink Models in UVM Environments with Automatic SystemVerilog DPI Component Generation by Tao Jia, HDL Verifier Development Lead, and Jack Erickson, HDL Product Marketing

More information

LiTE Design PORTFOLIO

LiTE Design PORTFOLIO LiTE Design We Focus on scaling to new & latest technology in Electronic Design System, to develop & produce innovative products, services & solutions with our Potential that Exceeds the expectations of

More information

Creo 2.0. Curriculum Guide

Creo 2.0. Curriculum Guide Creo 2.0 Curriculum Guide Live Classroom Curriculum Guide Update to Creo Parametric 2.0 from Creo Elements/Pro 5.0 Update to Creo Parametric 2.0 from Pro/ENGINEER Wildfire 4.0 Introduction to Creo Parametric

More information

Certified Technical Training for Emerson Flow Instruments. Helping you to maximize your Flow instrument investment

Certified Technical Training for Emerson Flow Instruments. Helping you to maximize your Flow instrument investment Certified Technical Training for Emerson Flow Instruments Helping you to maximize your Flow instrument investment Utilize the full range of product features to achieve the highest value from your flow,

More information

Automating Administration with Windows PowerShell 2.0

Automating Administration with Windows PowerShell 2.0 Automating Administration with Windows PowerShell 2.0 Course No. 10325 5 Days Instructor-led, Hands-on Introduction This course provides students with the knowledge and skills to utilize Windows PowerShell

More information

AN INTRODUCTION TO HYPERLYNX SI/PI TECHNOLOGY

AN INTRODUCTION TO HYPERLYNX SI/PI TECHNOLOGY AN INTRODUCTION TO HYPERLYNX SI/PI TECHNOLOGY BY STEVE KAUFER, MENTOR H I G H S P E E D D E S I G N W H I T E P A P E R OVERVIEW Digital designers are now required to make the leap from time domain to

More information

So you think developing an SoC needs to be complex or expensive? Think again

So you think developing an SoC needs to be complex or expensive? Think again So you think developing an SoC needs to be complex or expensive? Think again Phil Burr Senior product marketing manager CPU Group NMI - Silicon to Systems: Easy Access ASIC 23 November 2016 Innovation

More information

Pro/ENGINEER Wildfire 2.0 Curriculum

Pro/ENGINEER Wildfire 2.0 Curriculum Pro/ENGINEER Wildfire 2.0 Curriculum Live Classroom Virtual Class Web Based NOTE: For a graphical depiction of the curriculum based on job role, please visit this page: http://www.ptc.com/services/edserv/learning/paths/ptc/proe_wf2.htm

More information

NETZOOM PRO CLASSROOM TRAINING

NETZOOM PRO CLASSROOM TRAINING 2015 NetZoom Pro Classroom Training Program NETZOOM PRO CLASSROOM TRAINING By Altima Technologies, Inc. This brochure explains the training structure for NetZoom & NetZoom Pro. Altima Technologies, Inc.

More information

Revision Notes: July2004 Generate tutorial for single transistor analysis. Based on existing schematic entry tutorial developed for ECE410

Revision Notes: July2004 Generate tutorial for single transistor analysis. Based on existing schematic entry tutorial developed for ECE410 Cadence Analog Tutorial 1: Schematic Entry and Transistor Characterization Created for the MSU VLSI program by Professor A. Mason and the AMSaC lab group. Revision Notes: July2004 Generate tutorial for

More information

Learn to develop.net applications and master related technologies.

Learn to develop.net applications and master related technologies. Courses Software Development Learn to develop.net applications and master related technologies. Software Development with Design These courses offer a great combination of both.net programming using Visual

More information

WHAT IS BFA NEW MEDIA?

WHAT IS BFA NEW MEDIA? VISUAL & TYPE WEB & INTERACTIVE MOTION GRAPHICS DIGITAL IMAGING VIDEO DIGITAL PHOTO VECTOR DRAWING AUDIO To learn more and see three years of our best student work, please visit: webdesignnewmedia.com

More information

Expert Layout Editor. Technical Description

Expert Layout Editor. Technical Description Expert Layout Editor Technical Description Agenda Expert Layout Editor Overview General Layout Editing Features Technology File Setup Multi-user Project Library Setup Advanced Programmable Features Schematic

More information

PrimeTime: Introduction to Static Timing Analysis Workshop

PrimeTime: Introduction to Static Timing Analysis Workshop i-1 PrimeTime: Introduction to Static Timing Analysis Workshop Synopsys Customer Education Services 2002 Synopsys, Inc. All Rights Reserved PrimeTime: Introduction to Static 34000-000-S16 Timing Analysis

More information

Baseband IC Design Kits for Rapid System Realization

Baseband IC Design Kits for Rapid System Realization Baseband IC Design Kits for Rapid System Realization Lanbing Chen Cadence Design Systems Engineering Director John Rowland Spreadtrum Communications SVP of Hardware Engineering Agenda How to Speed Up IC

More information

Training Fees 4,250 US$ per participant for Public Training includes Materials/Handouts, tea/coffee breaks, refreshments & Buffet Lunch

Training Fees 4,250 US$ per participant for Public Training includes Materials/Handouts, tea/coffee breaks, refreshments & Buffet Lunch Training Title PLC & SCADA SYSTEMS Training Duration 5 days Training Venue and Dates REF IC012 PLC & SCADA Systems 5 04-08 Feb $4,250 Abu Dhabi, UAE Training Fees 4,250 US$ per participant for Public Training

More information

Cadence Tutorial A: Schematic Entry and Functional Simulation Created for the MSU VLSI program by Andrew Mason and the AMSaC lab group.

Cadence Tutorial A: Schematic Entry and Functional Simulation Created for the MSU VLSI program by Andrew Mason and the AMSaC lab group. Cadence Tutorial A: Schematic Entry and Functional Simulation Created for the MSU VLSI program by Andrew Mason and the AMSaC lab group. Revision Notes: Aug. 2003 update and edit A. Mason add intro/revision/contents

More information

Keysight KS8400A Test Automation Platform 2017 Developer s System Software. Technical Overview

Keysight KS8400A Test Automation Platform 2017 Developer s System Software. Technical Overview Keysight KS8400A Test Automation Platform 2017 Developer s System Software Technical Overview 02 Keysight KS8400A Test Automation Platform 2017 Developer s System Software - Technical Overview Product

More information

THE HIGHER EDUCATION PROGRAM

THE HIGHER EDUCATION PROGRAM THE HIGHER EDUCATION PROGRAM 2013-14 Educating Tomorrow s Technology Leaders Today 2007-2008 THE HIGHER EDUCATION PROGRAM Educating Tomorrow s Technology Leaders Today 1 Copyright Mentor Graphics Corporation

More information

Advanced Automated Administration with Windows PowerShell

Advanced Automated Administration with Windows PowerShell Advanced Automated Administration with Windows PowerShell Course 10962B - Three days - Instructor-led - Hands-on Introduction This three-day instructor-led course is a follow on course from the 10961:

More information

Lecture 1: Introduction Course arrangements Recap of basic digital design concepts EDA tool demonstration

Lecture 1: Introduction Course arrangements Recap of basic digital design concepts EDA tool demonstration TKT-1426 Digital design for FPGA, 6cp Fall 2011 http://www.tkt.cs.tut.fi/kurssit/1426/ Tampere University of Technology Department of Computer Systems Waqar Hussain Lecture Contents Lecture 1: Introduction

More information

Course Index Enterprise Online Training (Self Paced Education) Optio Advanced Labeling for Optio Document Designers

Course Index Enterprise Online Training (Self Paced Education) Optio Advanced Labeling for Optio Document Designers Optio Training Course Catalog Bottomline maintains an active schedule of instructor led classroom, instructor led online and selfpaced CD based training programs for Optio Enterprise and Optio Healthcare

More information

EE 4755 Digital Design Using Hardware Description Languages

EE 4755 Digital Design Using Hardware Description Languages EE 4755 Digital Design Using Hardware Description Languages Basic Information URL: http://www.ece.lsu.edu/v Offered by: David M. Koppelman, Room 3316R P. F. Taylor Hall 578-5482. koppel@ece.lsu.edu, http://www.ece.lsu.edu/koppel/koppel.html

More information

COURSE LISTING. Courses Listed. with ABAP Dialog Programming. 25 December 2017 (08:57 GMT) NW001 - SAP NetWeaver - Overview

COURSE LISTING. Courses Listed. with ABAP Dialog Programming. 25 December 2017 (08:57 GMT) NW001 - SAP NetWeaver - Overview with ABAP Dialog Programming Courses Listed NW001 - SAP NetWeaver - Overview SAPTEC - SAP NetWeaver Application Server Fundamentals BC100 - ( ABAP) BC100E - Introduction to Programming with ABAP BC400

More information

Many Roles and Point Solutions are Used in Product Development

Many Roles and Point Solutions are Used in Product Development Creo 1.0 Many Roles and Point Solutions are Used in Product Development 2D Markup 2D 2D Parametric Direct Parametric CAE Direct Assy App 2D Direct ROLES Product Manager Design Manager Designer Engineer

More information

Designing into a Foundry Low Power High-k Metal Gate 28nm CMOS Solution for High-Performance Analog Mixed Signal and Mobile Applications

Designing into a Foundry Low Power High-k Metal Gate 28nm CMOS Solution for High-Performance Analog Mixed Signal and Mobile Applications Designing into a Foundry Low Power High-k Metal Gate 28nm CMOS Solution for High-Performance Analog Mixed Signal and Mobile Applications A Collaborative White Paper by RAMBUS and GLOBALFOUNDRIES W h i

More information

ESE 570 Cadence Lab Assignment 2: Introduction to Spectre, Manual Layout Drawing and Post Layout Simulation (PLS)

ESE 570 Cadence Lab Assignment 2: Introduction to Spectre, Manual Layout Drawing and Post Layout Simulation (PLS) ESE 570 Cadence Lab Assignment 2: Introduction to Spectre, Manual Layout Drawing and Post Layout Simulation (PLS) Objective Part A: To become acquainted with Spectre (or HSpice) by simulating an inverter,

More information

Virtuoso Custom Design Platform GXL. Open Database. PDKs. Constraint Management. Customer IP

Virtuoso Custom Design Platform GXL. Open Database. PDKs. Constraint Management. Customer IP Virtuoso Custom Design Platform GL The Cadence Virtuoso custom design platform is the industry s leading design system for complete front-to-back analog, RF, mixed-signal, and custom digital design. The

More information

PELLISSIPPI STATE TECHNICAL COMMUNITY COLLEGE MASTER SYLLABUS HPC INTERNETWORKING & GRID TECHNOLOGY HPC 1020

PELLISSIPPI STATE TECHNICAL COMMUNITY COLLEGE MASTER SYLLABUS HPC INTERNETWORKING & GRID TECHNOLOGY HPC 1020 PELLISSIPPI STATE TECHNICAL COMMUNITY COLLEGE MASTER SYLLABUS HPC INTERNETWORKING & GRID TECHNOLOGY HPC 1020 Class Hours: 3.0 Credit Hours: 4.0 Laboratory Hours: 3.0 Revised: Spring 03 NOTE: This course

More information

electronic lab 11 Fedora Electronic Lab empowers hardware engineers and universities with opensource solutions for micro nano electronics engineering.

electronic lab 11 Fedora Electronic Lab empowers hardware engineers and universities with opensource solutions for micro nano electronics engineering. The Fedora Project is out front for you, leading the advancement of free, open software and content. electronic lab 11 Community Leader in opensource EDA deployment Fedora Electronic Lab empowers hardware

More information

FloTHERM. Optimizing the Thermal Design of Electronics.

FloTHERM. Optimizing the Thermal Design of Electronics. FloTHERM Optimizing the Thermal Design of Electronics M e c h a n i c a l a n a l y s i s FloTHERM has more users than all other competing analysis software combined, making it the clear market leader

More information

Live Classroom Curriculum Guide

Live Classroom Curriculum Guide Curriculum Guide Live Classroom Curriculum Guide Milling using Pro/ENGINEER Wildfire 4.0 Pro/ENGINEER Mechanica Simulation using Pro/ENGINEER Wildfire 4.0 Introduction to Pro/ENGINEER Wildfire 4.0 Pro/ENGINEER

More information

Hardware Design Environments. Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University

Hardware Design Environments. Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University Hardware Design Environments Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University Outline Welcome to COE 405 Digital System Design Design Domains and Levels of Abstractions Synthesis

More information

PCB Design Tools User Guide

PCB Design Tools User Guide PCB Design Tools User Guide Intel Quartus Prime Pro Edition Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1. Signal Integrity

More information

PDK-Based Analog/Mixed-Signal/RF Design Flow 11/17/05

PDK-Based Analog/Mixed-Signal/RF Design Flow 11/17/05 PDK-Based Analog/Mixed-Signal/RF Design Flow 11/17/05 Silvaco s What is a PDK? Which people build, use, and support PDKs? How do analog/mixed-signal/rf engineers use a PDK to design ICs? What is an analog/mixed-signal/rf

More information

ALTERA FPGAs Architecture & Design

ALTERA FPGAs Architecture & Design ALTERA FPGAs Architecture & Design Course Description This course provides all theoretical and practical know-how to design programmable devices of ALTERA with QUARTUS-II design software. The course combines

More information

ECDL PROFILE DO IT YOU WAY

ECDL PROFILE DO IT YOU WAY NEW ECDL using MS Office 2007, 2010 or 2013 ECDL Profile ECDL PROFILE DO IT YOU WAY Your ECDL With ECDL Profile, you choose the module combinations best suited to you. After passing the tests, those modules

More information

Vivado Design Suite User Guide

Vivado Design Suite User Guide Vivado Design Suite User Guide Design Flows Overview Notice of Disclaimer The information disclosed to you hereunder (the Materials ) is provided solely for the selection and use of Xilinx products. To

More information

Hardware Software Codesign of Embedded Systems

Hardware Software Codesign of Embedded Systems Hardware Software Codesign of Embedded Systems Rabi Mahapatra Texas A&M University Today s topics Course Organization Introduction to HS-CODES Codesign Motivation Some Issues on Codesign of Embedded System

More information

Full Custom Layout Optimization Using Minimum distance rule, Jogs and Depletion sharing

Full Custom Layout Optimization Using Minimum distance rule, Jogs and Depletion sharing Full Custom Layout Optimization Using Minimum distance rule, Jogs and Depletion sharing Umadevi.S #1, Vigneswaran.T #2 # Assistant Professor [Sr], School of Electronics Engineering, VIT University, Vandalur-

More information

CMOS Design Lab Manual

CMOS Design Lab Manual CMOS Design Lab Manual Developed By University Program Team CoreEl Technologies (I) Pvt. Ltd. 1 Objective Objective of this lab is to learn the Mentor Graphics HEP2 tools as well learn the flow of the

More information

DATASHEET VIRTUOSO LAYOUT SUITE GXL

DATASHEET VIRTUOSO LAYOUT SUITE GXL DATASHEET Part of the Cadence Virtuoso Layout Suite family of products, is a collection of fully automated layout capabilities such as custom placement and routing, layout optimization, module generation,

More information

Sign up for the Barco University experience Best in class, first in business

Sign up for the Barco University experience Best in class, first in business Sign up for the Barco University experience Best in class, first in business Barco certification training Validate your expertise In today s competitive marketplace, exclusive skills and profound knowledge

More information

Training Venue and Dates September, 2019 $4,000 Dubai, UAE PLC & SCADA Systems Trainings will be conducted in any of the 5 star hotels.

Training Venue and Dates September, 2019 $4,000 Dubai, UAE PLC & SCADA Systems Trainings will be conducted in any of the 5 star hotels. Training Title PLC & SCADA SYSTEMS Training Duration 5 days Training Venue and Dates 5 15-19 September, 2019 $4,000 Dubai, UAE PLC & SCADA Systems Trainings will be conducted in any of the 5 star hotels.

More information

VLSI Lab Tutorial 3. Virtuoso Layout Editing Introduction

VLSI Lab Tutorial 3. Virtuoso Layout Editing Introduction VLSI Lab Tutorial 3 Virtuoso Layout Editing Introduction 1.0 Introduction The purpose of this lab tutorial is to guide you through the design process in creating a custom IC layout for your CMOS inverter

More information

THE HIGHER EDUCATION PROGRAM

THE HIGHER EDUCATION PROGRAM THE HIGHER EDUCATION PROGRAM 2012 Educating Tomorrow s Technology Leaders Today 2007-2008 THE HIGHER EDUCATION PROGRAM Educating Tomorrow s Technology Leaders Today 1 Copyright Mentor Graphics Corporation

More information

Upgrading to Windows Server 2008

Upgrading to Windows Server 2008 Upgrading to Windows Server 2008 This 5-day workshop provides participants with the knowledge and skills to work with Network Infrastructure and Active Directory technologies in Windows Server 2008. This

More information

Modular SystemVerilog

Modular SystemVerilog SystemVerilog (IEEE 1800 TM ) is a significant new language based on the widely used and industrystandard Verilog hardware description language. The SystemVerilog extensions enhance Verilog in a number

More information

Microsemi IP Cores Accelerate the Development Cycle and Lower Development Costs

Microsemi IP Cores Accelerate the Development Cycle and Lower Development Costs Microsemi IP Cores Accelerate the Development Cycle and Lower Development Costs October 2014 Introduction Today s FPGAs and System-on-Chip (SoC) FPGAs offer vast amounts of user configurable resources

More information

PlanAhead Release Notes

PlanAhead Release Notes PlanAhead Release Notes What s New in the 11.1 Release UG656(v 11.1.0) April 27, 2009 PlanAhead 11.1 Release Notes Page 1 Table of Contents What s New in the PlanAhead 11.1 Release... 4 Device Support...

More information

Your Student s Head Start on Career Goals and College Aspirations

Your Student s Head Start on Career Goals and College Aspirations Your Student s Head Start on Career Goals and College Aspirations INFORMATION TECHNOLOGY (IT) NETWORKING PATHWAY The Destinations Networking Pathway prepares students to test and evaluate computer network

More information

DO-254 Testing of High Speed FPGA Interfaces by Nir Weintroub, CEO, and Sani Jabsheh, Verisense

DO-254 Testing of High Speed FPGA Interfaces by Nir Weintroub, CEO, and Sani Jabsheh, Verisense DO-254 Testing of High Speed FPGA Interfaces by Nir Weintroub, CEO, and Sani Jabsheh, Verisense As the complexity of electronics for airborne applications continues to rise, an increasing number of applications

More information

NetVault Backup Web-based Training Bundle - 2 Student Pack

NetVault Backup Web-based Training Bundle - 2 Student Pack NetVault Backup Web-based Training Bundle - 2 Student Pack Description Get access to both Netvault Backup Implementation & Administration Web-based Training course and Netvault Backup Advanced Administration

More information

An overview of standard cell based digital VLSI design

An overview of standard cell based digital VLSI design An overview of standard cell based digital VLSI design Implementation of the first generation AsAP processor Zhiyi Yu and Tinoosh Mohsenin VCL Laboratory UC Davis Outline Overview of standard cellbased

More information

Contents 1 Introduction 2 Functional Verification: Challenges and Solutions 3 SystemVerilog Paradigm 4 UVM (Universal Verification Methodology)

Contents 1 Introduction 2 Functional Verification: Challenges and Solutions 3 SystemVerilog Paradigm 4 UVM (Universal Verification Methodology) 1 Introduction............................................... 1 1.1 Functional Design Verification: Current State of Affair......... 2 1.2 Where Are the Bugs?.................................... 3 2 Functional

More information