Module 2: Adding IP to a Hardware Design

Transcription

1 For Academic Use Only Systemy wbudowane laboratorium Uniwersytet Zielonogórski Wydział Elektrotechniki, Informatyki i Telekomunikacji Instytut Informatyki i Elektroniki Zakład InŜynierii Komputerowej Module 2: Adding IP to a Hardware Design Targeting MicroBlaze on the Spartan -3E Kit This material exempt per Department of Commerce license exception TSU

2 Module 2: Adding IP to a Hardware Design Lab Introduction Objectives Procedure This lab guides you through the process of adding additional IP to an existing processor system by using Xilinx Platform Studio (XPS). You will add GPIO peripheral from the IP Catalog tab to interface to the push buttons and DIP switches on the Spartan-3E Starter Kit. At the end of the lab, you will generate the bitstream and test the peripherals in hardware. After completing this lab, you will be able to: Add additional IP to a hardware design Update ucf file to support external ports of the added IP Setup some of the compiler settings The purpose of this lab exercise is to extend the hardware design (Figure 2-1) created in Lab 1according to the following procedure 1. Open the project 2. Add and connect GPIO peripherals in the system 3. Configure the GPIO peripherals 4. Make external GPIO connections 5. Analyze the MHS file 6. Add the software application and compile 7. Verify the design in hardware Adding IP to a Hardware Design 2-3

3 Figure 2-1. Extend the System from the previous lab For each procedure within a primary step, there are general instructions (indicated by the symbol). These general instructions only provide a broad outline for performing the procedure. Below these general instructions, you will find accompanying step-by-step directions and illustrated figures that provide more detail for performing the procedure. If you feel confident about completing a procedure, you can skip the step-by-step directions and move on to the next general instruction. Adding IP to a Hardware Design 2-4

4 Open the Project Step 1 Create a lab2 folder and copy the contents of the lab1 folder into the lab2. Launch Xilinx Platform Studio (XPS) and open the project file. ❶ Create a lab2 folder in the d:\xup\embedded\labs directory and copy the contents from lab1 to lab2 ❷ Open XPS by selecting Start Programs Xilinx ISE Design Suite 10.1 Platform Studio Xilinx Platform Studio ❸ Select Open a recent project, Click OK and browse to C:\xup\embedded\labs\lab2 ❹ Click system.xmp to open the project Add and Connect GPIO Peripherals to the System Step 2 Add two instances of an XPS GPIO Peripheral from the IP catalog to the processor system via the System Assembly View. XPS provides two methods for adding peripherals to an existing project. You will use the first method, the System Assembly View panel, to add most of the additional IP and connect them. The second method is to manually edit MHS file. ❶ Select the IP Catalog tab in the left window and click on plus sign next to General Purpose IO entry to view the available cores under it (Figure 2-2) Figure 2-2. System Assembly View Adding IP to a Hardware Design 2-5

5 ❷ Double-click on the XPS General Purpose IO core twice, to add two instances to the System Assembly View ❸ Change the instance names of the peripherals to dip and push, by clicking once in the name column, typing the new name for the peripheral followed by pressing Enter key At this point, the System Assembly View should look like the following (Figure 2-3): Figure 2-3. System Assembly View After Adding Peripherals ❹ Click once in Bus Connection column for the push and dip instances to connect them as slave devices to the PLB. At this point, the Bus Connections tab should look like the following (Figure 2-4): Adding IP to a Hardware Design 2-6

6 Figure 2-4. Bus Interfaces Tab showing Bus Connections to the Added Peripherals ❺ Select the Addresses filter You can manually assign the base address and size of your peripherals or have XPS generate the addresses for you. ❻ Click under the size column in the push and dip instances, change it to 64K, and hit Enter key ❼ Click Generate Addresses (located on the right most end of the tabs) to automatically generate the base and high addresses for the peripherals in the system. The base address and high addresses will change as shown in Figure 2-5 below Figure 2-5. Peripherals Memory Map Adding IP to a Hardware Design 2-7

7 Configure the GPIO Peripherals Step 3 There are four push buttons and four DIP switches on the Spartan-3E starter kit. You will first configure the push and dip instances according to their sizes and direction, and then make external pin connections. ❶ Select the Ports filter in the toolbar of the System Assembly View ❷ Double-click on the push instance to access the configuration window Notice that the peripheral can be configured for two channels, but, since we want to use only one channel leave the Enable Channel 2 unchecked. ❸ Click on the GPIO Data Bus Width down arrow and set it to 4, you will use 4 push buttons on the Spartan-3E starter kit. The settings for the Common parameters should be set according to Figure 2-6 below. Set the GPIO data width to 4 Figure 2-6. Configurable Parameters of GPIO Instance for Push Buttons ❹ Next click Channel 1 and set Channel 1 is Bi-directional to False and Channel 1 is input Only to True (Figure 2-7): Adding IP to a Hardware Design 2-8

8 Set the Push GPIO as input Figure 2-7. Setting Configurable Parameters for Push Buttons ❻ Set the same parameters for the dip instance, as performed for the push buttons. Make External GPIO Peripheral Connections Step 4 You will connect the push and dip instances to the push buttons and DIP switches on the Spartan-3E starter kit. In order to do this, you must establish the GPIO data ports as external FPGA pins and then assign them to the proper locations on the FPGA via the UCF file. The location constraints are provided for you in this section. Normally, one would consult the Spartan-3E starter kit user manual to find this information. ❶ Make the GPIO_in port of the push instance as external by selecting Make External. You should see a new external net connection (Figure 2-8). Adding IP to a Hardware Design 2-9

9 The external pin push_gpio_in_pin is added and connected to the GPIO_in port via the net push_gpio_in Figure 2-8. GPIO_in Port Connection Added to push Instance ❷ Set the GPIO_in port of dip as external. The GPIO_in ports of both dip and push are now connected externally on the FPGA (Figure 2-9). Adding IP to a Hardware Design

10 The GPIO_in ports of dip and push instances are connected to external pins Figure 2-9. Push and DIP Instances External Ports ❹ Click on the system.ucf file under the Project tab and add the following code to assign pins to push buttons (The constraints are provided in lab2.ucf file in c:\xup\embedded\sources directory. Copy it from there and paste it in your ucf file) Figure UCF file (pin assignments). ❺ Save the system.ucf and close it Analyze the MHS file Step 5 Open the system.mhs file, study its contents, and answer the following questions. ❶ Double-click the system.mhs file to open it if it is not already open Study the external ports sections and answer the following questions? 1. Complete the following: ❸ Review the entire MHS file Number of external ports: Number of external ports that are output: Number of external ports that are input: Number of external ports that are bidirectional:? 2. List the instances to which the sys_clk_s is connected: Adding IP to a Hardware Design

11 List the devices connected to the mb_plb bus: ❹ Review the memory map in the Addresses tab of the System Assembly View? 3. Draw the address map of the system, providing instance names $0000_0000 $FFFF_FFFF Add Software Application and Compile Step 6 Add an existing c program to implement the functionality of push button and LEDs. Compile the program. ❶ Click on Applications tab and under Sources, right-click on TestApp_Memory.c file and select Remove ❷ Right click on Sources and add lab2.c file from c:\xup\embedded\sources folder A snippet of the source code is shown in Figure 2-11 Adding IP to a Hardware Design

12 Figure Snippet of source code. ❸ In the Application tab, double-click on compiler options to open the Compiler Options dialogue box. ❹ In the Environment tab, select the option Use Default Linker Script. Adding IP to a Hardware Design

13 Figure Setting the Default Linker Script ❺ In the Debug and Optimization tab, set the optimization to No Optimization. This will ensure that the for loop (used for software delay) in the source code is not optimized away. Adding IP to a Hardware Design

14 Figure Setting the Optimization level ❺ Click on to compile the source code. Make sure that it compiles error free Note: This will automatically run LibGen to generate the required libraries if it has not been done already. Verify the Design in Hardware Step 7 Download the bitstream to the Spartan-3E xc3s500e device. ❶ Start a HyperTerminal session Baud rate: Data bits: 8 Parity: none Stop bits: 1 Flow control: none ❷ Connect and power up the Spartan-3E starter kit. ❸ Select Device Configuration Update Bitstream This may take a few minutes to synthesize, implement, and generate the bitstream. ❹ Download the bitstream by selecting Device Configuration Download Bitstream Adding IP to a Hardware Design

15 Note: Once the bitstream is downloaded, you should see the DONE LED ON and a message displayed in HyperTerminal as shown in Figure 2-14 Figure Screen Shot after the BitStream Downloading ❺ After pressing the buttons and toggling the switches, and you should see the corresponding values being displayed on the HyperTerminal (Figure 2-15) Figure Push button and DIP switch status displayed on hyperterminal ❻ Disconnect and close the HyperTerminal window, and also close XPS Conclusion GPIO peripherals were added from the IP catalog and connected to a MicroBlaze system that was created in the first lab. The peripherals were configured and external FPGA connections were established. Pin location constraints were made in the UCF file to connect the peripherals to push buttons and DIP switches on the Spartan-3E starter kit. In future labs in this course, you will learn how to add user cores, add software to the system, simulate the design, debug the software, and verify the functionality of the completed design by using a Spartan-3E Starter Kit. Adding IP to a Hardware Design