A Review on RISC Processor

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1 A Review on RISC Processor Prabhat Pandey Assistant Professor Dept. of Electronics & Communication Acropolis Institute of Technology & Research, Indore, M.P. (India) Shahnawaz Khan M. Tech. Scholar Embedded System & VLSI Design Acropolis Institute of Technology & Research, Indore, M.P. (India) Abstract Pipeline processor is a processor that applies to the single cycle architecture. It executes several instructions simultaneously, improving throughput significantly. It must add logic to handle dependencies between simultaneously executing instructions. It requires non-architectural pipeline registers. All the commercial high performance processor use pipeline today. This paper presents an overview of RISC processor using architectural features. A literature review of previous research works is also exist. Keywords CISC, HLLs, ISA, MULADD, MVC, RISC. I. INTRODUCTION A. Principle Originally the analysis of code sequences showed that the vast majority of available instructions were used very little. Thus, only a very small set of instructions was mainly used in programs. This is why the RISC architecture makes the choice to limit the set of instructions to only a few, imposing on all, in return, an identical number of cycles to execute. In this way, it is possible to start a new instruction every clock cycle: this constitutes the "pipeline". The advantage of this technique is that, now, the processor behaves as if there was an instruction executed by clock cycle. In addition, the division of each instruction in several steps allows a greater clock frequency since the combinatorial depth between two registers is decreased. These two characteristics result in a division of execution time for all basic instructions [1]. B. Disadvantages This is paid at the cost of a certain decrease in the legibility of the troublesome code when we program in assembler and especially if we optimize it: the Instruction MVC (MoVe Character) of System 360 still remained more legible than the sequence of instructions doing the same thing in a RISC machine. But for whom coded strcpy() in C, there was no difference. And in execution time, the optimized C code was generally more efficient in pure speed through tricks of use of the pipeline effect by the compiler. The RISC code is generally less compact, since all instructions are the same size, while the most used instructions are shorter in a CISC instruction set. C. Advantages Because each instruction was simple, decoding and execution by the processor had to be very fast, ideally in a single cycle, or two instructions per cycle, which was not the case with CISC instructions. On CISC processors the instructions were generally implemented as micro-code in the microprocessor, each execution of this microcode took a cycle. For a Motorola for example, the fastest instructions took 4 cycles and the longest up to 160 cycles for the divisions. This has changed with the Motorola 68030, some of whose instructions could only take a single cycle [2-4]. On the contrary, the RISC processors that were used on more powerful computers were given instructions of the type MULADD (multiplication + addition), the most used instruction in the vector and matrix computation. These hardwired instructions took only one cycle to multiply two registers, add another register and save the result either in one of these registers or in another. This is the case for example in the PowerPC architecture, which equipped the Macintosh from 1994 to 2006, or the BeBox, which was in 1995 the first dual-processor microcomputer. Another advantage of CISC RISC is energy loss through heat dissipation. Early models of PowerPC with computing capabilities similar to or better than the x86 of the same era, did not need heat sinks, while we began to see combinations of radiators and fans on them.

2 II. RISC MACHINES The dominant architecture in the PC market, the Intel IA-32, belongs to the Complex Instruction Set Computer (CISC) design. The obvious reason for this classification is the complex nature of its Instruction Set Architecture (ISA). The motivation for designing such complex instruction sets is to provide an instruction set that closely supports the operations and data structures used by Higher-Level Languages (HLLs). However, the side effects of this design effort are far too serious to ignore. The decision of CISC processor designers to provide a variety of addressing modes leads to variable-length instructions. For example, instruction length increases if an operand is in memory as opposed to in a register. This is because we have to specify the memory address as part of instruction encoding, which takes many more. This complicates instruction decoding and scheduling. The side effect of providing a wide range of instruction types is that the number of clocks required to execute instructions varies widely. This again leads to problems in instruction scheduling and pipelining. For these and other reasons, in the early 1980s designers started looking at simple ISAs. Because these ISAs tend to produce instruction sets with far fewer instructions, they coined the term Reduced Instruction Set Computer (RISC). Even though the main goal was not to reduce the number of instructions, but the complexity, the term has stuck. However, there is not any exact definition for RISCs [5-8]. A computer can qualify to be a RISC if it can meet most of the following characteristics: Instruction set is simple. Instructions are of a uniform length. Instruction set uses few instruction formats. Little overlapping of instruction functionality. Instruction set implements few addressing modes. Few instructions move data to and from the main memory. All operate instruction manipulate only data from the register file. Instruction set supports a limited number of data types. A. RISC Architectures Table 1: Characteristics of desktop and server RISC Date announced Instruction ALPHA MIPS-I POWER-PC Addressing modes Integer register GPR 64 31GPR 32 General Purpose Register (GPR) Date announced Instruction Addressing modes Integer register Table 3.2: Characteristics of embedded RISC 31GPR 32 ARM THUMB MIPS / GPR 32 8GPR 32 8GPR 32/64 Table 2 shows that embedded RISC have 8 to 16 general purpose registers and the length of instruction is 16 to 32 while Table 1 shows that desktop and server RISC have 32 general purpose registers and the length of instruction is fixed i.e.32. It has been also observed that desktop and server RISC require less no. of addressing modes as compare to the embedded RISC. B. Architectural Features of RISC Processors RISC processors rely on code optimization on the compiler, while instructions are easy to decode for the processor. For that: These processors have many "general" registers (at least 16, usually 32), all equivalent, to facilitate their allocation by the compiler. The instructions are fixed size, often 32. The arithmetic instructions generally have 3 addresses: 2 registers serving as operands and an output register. Access to the memory is the subject of specific instructions, and a value must first be loaded into a register to be used: we speak of loadstore architecture or register-register instructions. Additions were made later to improve their performance: smaller instructions or code compression methods were introduced and registry windows speed up function calls on some architectures. Current RISC architectures can also use vector instructions and a floating point unit. Other types of architectures have sought to reduce the complexity of the instruction set, but differ from the RISC architectures by the means used: operands are the elements of the top of a stack and not registers for battery processors, while transport

3 triggered architectures only provide value transfer instructions between registers and compute units. C. History A processor such as Inmos Transputer (later STMicroelectronics) adopted the solution of replacing the registers (whose designation consumes in the instructions) by a stack. Other RISC machines, on the other hand, like the IBM RS / 6000, multiplied the registers to such a degree that they could no longer be programmed efficiently in assembler, the programmer's memory always doing worse than the optimization algorithms of C language compilers. The MIPS R3000 processors were the first in the market to implement the RISC architecture, followed by the Alpha of Digital. MIPS Technologies was also the first company to produce RISC 64-bit processors (mainly used on Silicon Graphics stations). PowerPC processors, derived from the RS / 6000 and used among others on Macintosh are RISC architecture, as well as SPARC processors used by Sun Microsystems among others for their servers and workstations. PC-compatible microcomputers were powered up to generation 486 by CISC microprocessors (NEC, STMicroelectronics, AMD, Intel) Since the 586 generation, the CISC architecture has been emulated in the IA-32 architecture chips by the firmware of an underlying RISC processor. In the world of embedded electronics, the APS3, ARM and MIPS processors also have a RISC architecture. D. CISC / RISC performance comparison We know a case of the same software running both on a micro-programmed RISC machine emulating a CISC and natively: it is about AIX running on an IBM 9370 (chip IBM 860 microprogramming architecture 370) and at the same time, on the PC / RT (6150) which used this same 860 chip natively: the performance gap in raw computation was then a factor of 2 in favour of the PC / RT. Today, the performance of the two families of processors is substantially comparable. E. Positioning The calculation unit of the RISC processors, because of its simplicity, is often smaller. At equal chip size, we can therefore add a larger cache, and most often two caches: one for the data and the other for the instructions (which is never necessary to rewrite in the memory main, hence simpler circuits). RISC architecture has been found in various RISC such as in the desktop, servers and embedded RISC. Desktop and server RISC are digital ALPHA, IBM and Motorola POWERPC, MIPS-I etc. while embedded RISC are ARM (Advanced RISC Machine), ARM thumb, MIPS-16 etc. III. LITERATURE REVIEW In [1], authors implemented the 32-bit RISC MIPS processor on Spartan-6 FPGA. The project involves simulation and synthesis of a processor. A Reduced Instruction Set compiler (RISC) is a microprocessor that had been designed to perform a small set of instructions, with the aim of increasing the overall speed of the processor. The idea of this project was to create a RISC MIPS processor as a building block in Verilog HDL. In [2], authors presented the design and implementation of 32 bit MIPS processor. The architecture with pipelined control RISC core consists of fetch, decode, execute, pipeline control and memory. The reduction in the power is achieved using HDL modification techniques. The design is based on program counter, instruction memory, logical unit, arithmetic unit and optimization techniques. In [3], authors presented the design of a RISC (Reduced Instruction Set Computer) CPU architecture based on MIPS (Microprocessor Interlock Pipeline Stages) using VHDL. It also describes the instruction set, architecture and timing diagram of the processor. Floating point number to fixed number conversion is the main task while working on this numbers, this conversion has been achieved by using Float to Fixed number converter module. In [4], authors implemented a 5-stage pipelined 32- bit High performance MIPS based RISC Core. MIPS (Microprocessor without Interlocked Pipeline Stages) is a RISC (Reduced Instruction Set Computer) architecture. A RISC is a microprocessor that had been designed to perform a small set of instructions, with the aim of increasing the overall speed of the processor. MIPS have 5 stages of pipeline viz. Instruction Fetch (IF), Instruction Decode (ID), Execution (EX), Memory Access (MEM) and Write Back (WB) modules. The various modules being used are Instruction Memory, Data Memory, ALU, Registers etc. In [5], authors proposed 5 stage pipelined architecture of 32 bit RISC Processor (MIPS) using VHDL. The simulations are done with ModelSim simulator. A Reduced Instruction Set computer is a microprocessor that had been designed to perform a

4 small set of instructions, with the aim of increasing the overall speed of the processor. In paper [6], the author proposed a 16-bit nonpipelined RISC processor, which is used for signal processing applications. A high speed and low power modified Wallace tree multiplier has been designed and introduced in the design of ALU. The RISC processor has been designed for executing 27- instruction set. It is expandable up to 32 instructions, based on the user requirements. The processor has been realized using Verilog HDL, simulated using Modelsim 6.2 and synthesized using Synopsys. This paper extended the utility of the processor towards convolution application, which is one of the most important signal processing application. The simulations depict the total dissipated power by the processor to be approximately μw with the total area of nm2. Paper [7] details the design of an embedded RISC controller used for mixed signal audio integrated circuits. This processor replaced an existing 8 bit CISC embedded processor and obtained a performance improvement of about 6x. This performance improvement was entirely due to architectural improvements using the same input clock rate and external ROM IP block. A design for a single cycle RISC processor has been discussed that does not use pipelining. This operation is obtained by folding the processor execution into the memory cycle. The RISC uses a ripple through latch style of design as opposed to a synchronous flip-flop style design. Paper [8] presented the design of a 16-bit RISC processor core. The quasi-adiabatic DCPAL circuit design style is employed in the designs. The major blocks constituting the processor core are the Arithmetic and Logical Unit (ALU), Program Counter, Adiabatic Register file and Control Unit housing the instruction decoders. The schematic designs are drawn using the schematic edit tool and the extracted net lists are used in the simulations. The design is validated by developing and testing the equivalent CMOS circuit counterparts for the processor core design. 250nm Technology model library from TSMC are used in the designs. Use of the identical design environment for the adiabatic and CMOS logic circuits ensures justifiable comparison among the circuits. The schematic design and HSPICE simulations are realized using the industry standard tool flow. Adiabatic gain values of up to 10 are realized in the circuits. In paper [9], the author proposed a design of a 16-bit RISC CPU core using an adiabatic logic which is called a two phase drive adiabatic dynamic CMOS logic (2PADCL), in this paper. The proposed adiabatic RISC CPU is non-pipelined with a latency of three cycles, and also consists of six blocks; an arithmetic and logic unit (ALU), a program counter, a register file, an instruction decoder unit, a multiplexer and a clock control unit. Through the SPICE simulation, the 2PADCL CPU was evaluated for 0.35mm standard CMOS library and was compared with the CMOS CPU. The simulation results show that the power consumption of the adiabatic CPU is about 1/4 compared to that of the CMOS CPU. In [10], authors focused on principles of adiabatic logic, its classifications and comparison of various adiabatic logic circuits. An attempt has been made in this paper to modify some adiabatic logic circuits to minimize total power consumption with respect to normal CMOS logic. This paper investigates the design approaches of low power adiabatic gates in terms of energy dissipation. A computer simulation using SPICE is carried out on several inverter circuits. In [11], practical issues in the design of power clock generators needed by adiabatic logic circuits are explained. Synchronous and asynchronous power clock generators are designed for an 8-bit adiabatic carry look-ahead adder and the more energy efficient circuit for the power clock generation is determined to be the 2N synchronous power clock generator that exhi conversion efficiency of 77% at 1 operating frequency. Many problems are associated with asynchronous power clock generators such as unstable frequency problems due to the sensitivity of their oscillation frequencies to their capacitive load variations in different cycles of the system operation and their disability for the generation of 4.8 and more phase shifted power clocks needed in some adiabatic logic circuits. The synchronous power clock generators can be utilized as an efficient solution without having any of the above problems. Synchronous power clock generators are synchronized to external time base signals usually available in large systems. In [12], authors proposed an architectures for very fast and low power DEC circuits that can be used in Low power RISC processors. The designs operate on the 2N-2N2P energy recovery logic design approach. The 350nm technology library files from AMS350nm standard CMOS technology are used in the work. The proposed circuit reduces the operation complexity and number of devices used. It paves way for reduced area, less power dissipation and lower energy added with increase in speed performance.

5 In [13], authors presented performance analysis of different Fast Adders. The comparison is done on the basis of three performance parameters i.e. Area, Speed and Power consumption. This paper presented a modified carry select adder designed in different stages. Results obtained from modified carry select adders are better in area and power consumption. All the adders designed are 32- wide. CSAS 5 stage consists of 5 stages with each block from LSB block to MSB blocks are [ ] wide. These adders are faster than ripple carry adders but slower than carry select adders. In [14], authors presented additional reduction of latency and power consumption of the Wallace tree multiplier. This is accomplished by the use of 4:2, 5:2 compressors and by the use of Sklansky adder. The result shows that the proposed architecture is 44.4% faster than the conventional CMOS architecture, along with 11% of reduced power consumption realization at 200MHz. In [15], authors presented the ODALRISC processor, which is an ultra-small and low power consuming configurable 32-bit RISC processor. The base version is synthesized using 0.18 mum technologies, taking less than 16 k gates and consuming power less than 0.1 mw/mhz. In [16], authors proposed a design of general purpose processor with a 5 stage pipeline, to incorporate programmable resources in to a processor. RISC processors have a CPI (clock per instruction) of one cycle. This is due to the optimization of each instruction on the CPU and a technique called pipelining. This technique allows each instruction to be processed in a set number of stages. This in turn allows for the simultaneous execution of a number of different instructions, each instruction being at a different stage in pipeline. The development approach of the overall system design depends on the design specification, analysis and simulation. The RISC Processor core is high performance 32-bit microprocessor. This processor make it especially suited to embedded control applications. In [17], authors described the use of a reconfigurable processor core based on RISC architecture as starting point for application-specific processor design. By using a common base instruction set, development cost can be reduced and design space exploration is focused on the application-specific aspects of performance. An important aspect of deploying any new architecture is verification which usually requires lengthy software simulation of a design model. IV. CONCLUSION Finding out literature review is very important for any research project. It clearly represents the background development & also establishes the need of the work. It obtain related problem regarding improvements in the study already done in past and allows unresolved problems to emerge. In such a way, it clearly defines all Limitation & boundaries regarding the development of the research project. On-going through the various research papers, books and literature, it came to the conclusion that various keywords and techniques are efficient to solve problem domain. These paper discuss the previous work done on RISC processor. REFERENCE [1] Pranjali S. Kelgaonkar, Shilpa Kodgire, Pipelined 32bit RISC MIPS Processor on Spartan-6 FPGA, International Journal of Science, Engineering and Technology Research (IJSETR), ISSN: , Vol. 5, Issue 8, August [2] P. Ajith Kumar, M. Vijaya Lakshmi, Design of a Pipelined 32 Bit MIPS Processor with Floating Point Unit, International Journal of Innovative Research in Science, Engineering and Technology, ISSN: , Vol. 5, Issue 7, July [3] S. P. Ritpurkar, M. N. Thakare, G. D. Korde, Design and Simulation of 32-Bit RISC Architecture based on MIPS using VHDL, IEEE, International Conference on Advanced Computing and Communication Systems (ICACCS -2015), Coimbatore, INDIA, January [4] Topiwala, Mohit N., and N. Saraswathi, Implementation of a 32-bit MIPS Based RISC Processor using Cadence, IEEE International Conference on Advanced Communication Control and Computing Technologies (ICACCCT), pp , May [5] Sharda P. Katke, G.P. Jain, Design and Implementation of 5 Stages Pipelined Architecture in 32 Bit RISC Processor, International Journal of Emerging Technology and Advanced Engineering, ISSN: , Vol. 2, Issue 4, April [6] Samiappa Sakthikumaran, S. Salivahanan, V. S. Kanchana Bhaaskaran, 16-Bit RISC Processor Design for Convolution Application IEEE-International Conference on Recent Trends in Information Technology, ICRTIT [7] Robert S. Plachno, VP of Audio, A True Single Cycle RISC Processor without Pipelining, ESS Design White Paper RISC Embedded Controller. [8] V. B. Saambhavi and V. S. Kanchana Bhaaskaran, A 16-BIT RISC MICROPROCESSOR USING DCPAL CIRCUITS, International Journal of Advanced Engineering Technology (IJAET), Vol. 2, no. 1, pp.1-9, [9] Yasuhiro Takahashi, Member, IACSIT, Toshikazu Sekine, and Michio Yokoyama, Design of a 16-bit Nonpipelined RISC CPU in a Two Phase Drive Adiabatic Dynamic CMOS Logic, International Journal of Computer and Electrical Engineering, Vol. 1, No. 1, April [10] Samanta, S. A Contemporary Review of Adiabatic Computing, IEEE Symp. Computers and Devices for Communication, CODEC 2009.

6 [11] Hamid Mahnzoodi-Meimand and Ali Afiali-Kusha, EFFICIENT POWER CLOCK GENERATION FOR ADIABATIC LOGIC, IEEE, [12] Samiappa Sakthikumaran et al., A Very Fast and Low Power Incrementer and Decrementer Circuits, International Journal of Computer Communication and Information System (IJCCIS) Vol2. No , pp [13] Padma Devi, Ashima Girdher, Balwinder Singh, Improved Carry Select Adder with Reduced Area and Low Power Consumption, International Journal of Computer Applications ( ) Volume 3 No.4, June [14] Vinoth, C., A novel low power and high speed Wallace tree multiplier for RISC processor, IEEE, Electronics Computer Technology (ICECT), rd International Conference. [15] Imyong Lee, ODALRISC: A small, low power, and configurable 32-bit RISC processor, SoC Design Conference, ISOCC '08. [16] M. Kishore Kumar & M. D. Shabeena Begum, FPGA BASED IMPLEMENTATION OF 32 BIT RISC PROCESSOR, International Journal of Engineering Research and Applications (IJERA), Vol. 1, Issue 3, pp [17] Gschwind, M., FPGA prototyping of a RISC processor core for embedded applications, Very Large Scale Integration (VLSI) Systems, IEEE Transactions, 2001.