An FPGA Implementation of 8-bit RISC Microcontroller

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1 An FPGA Implementation of 8-bit RISC Microcontroller Krishna Kumar mishra 1, Vaibhav Purwar 2, Pankaj Singh 3 1 M.Tech scholar, Department of Electronic and Communication Engineering Kanpur Institute of Technology, Kanpur 2 Assistant Professor, Department of Electronic and Communication Engineering Kanpur Institute of Technology, Kanpur 3 Assistant Professor, Department of Electronic and Communication Engineering Kanpur Institute of Technology, Kanpur ABSTRACT Microprocessor and Microcontroller designs are based on Reduced Instruction Set Computer (RISC). The design constraints are speed, power and area. In this paper, thirty instructions are discussed to achieve the RISC Microcontroller designing. It has four ports to communicate with other I/O Devices. A Finite State Machine designing approach has been used for designing the basic units and they combined using structural programming. The analysis shows that RISC Microcontroller enhances the speed by reducing the clock period than other Microcontroller (Sim2, and Intel AD8051). The Microcontroller has been designed using Very high speed integrated circuit Hardware Description Language (VHDL), Xilinx 9.2i and simulated on Model Sim 6.5 ISE. Keywords:- RISC, CISC, CPU, VHDL 1.INTRODUCTION This paper targets the design of a RISC (Reduced Instruction Set Computer) Microcontroller using VHDL (Very high speed integrated circuit Hardware Description Language) by structural programming. Furthermore, the goal of this work is to reduce the clock period and enhance the speed of microcontroller by using the RISC architecture which has fixed length instruction and decoding is very easier. Most of the instructions are working on the data stored in internal registers. LOAD and STORE instruction access the data in data memory. CISC processors are mainly emphasis on hardware. They support various address mode and data types. Due to variation in length of instruction they are generally implemented using micro-programmed model. The execution of an instruction takes more than one cycle. The proposed microcontroller follows the non pipelined architecture. It has four stages; Fetch Decode, Stage control and an Execute. The Fetch unit fetches the instructions from program memory. Decode unit decodes the instructions and execution unit execute them. The stage control unit controls the flow to follow the fetch, decode and execute path. The top level entity of proposed 8-bit microcontroller is shown in fig.1. The controller has clock and Reset as input and PORTA_8, PORTB_8, PORTC_8 and PORTD_8 are 8 bit I/O port for communication with other devices. Fig.1: Top level entity: proposed Controller [1] Volume 3, Issue 1, January 2015 Page 35

2 2.INSTRUCTION SET ARCHITECTURE The first step is to fix the instruction for the execution. The proposed controller supports thirty instructions of fixed length op-code. The instruction register width is 16-bit; the first five bits are used as op-code A.Register File The proposed RISC Microcontroller has two types of registers: - General Purpose and Special Purpose Registers. It has sixteen GPR (general purpose registers, A0-A15), are used for communication within the control unit. Also it has four special purpose registers (port_a, port_b, port_c, port_d), are used for communicating with I/O devices. All registers in the design can hold an 8-bit data. The base resister for the proposed controller is A0. B.Instruction Formats All the instructions are of fixed length in this proposed Microcontroller and instruction register length is sixteen bit. The proposed microcontroller design supports three types of instruction formats. Immediate type, Register type, Jump type. The different instruction format is shown in fig 2. Fig.2 : Instruction Formats The length of the OP-CODE of this proposed RISC Microcontroller is 5-bit, also 3-bit are used for destination register and source register both. In the Immediate type of instruction an 8-bit immediate data is a part of the instruction. In this type a destination register is also available. In register type instruction format both the source and destination be registers. Also in jump type, a 11-bit program memory address is used as part of the instruction C.Instruction Set There are 30 instructions grouped into 4 categories: Arithmetic and Logic instructions, Branch instructions, Data transfer instructions and the Bit and Bit-test instructions. The design support two flags: ZERO and CARRY. Table 1 represents the instruction set used in this design i. Arithmetic and Logic Operation Table.1: Instruction set ii. Branch Instruction Volume 3, Issue 1, January 2015 Page 36

3 iii. Data Transfer Instructions iv. Bit and Bit Test Instructions The ADD, SUB and MUL operation performs the addition subtraction and multiply operation between destination and source registers and the result is stored in destination register. If the result of operation is zero, it sets the zero flag otherwise cleared. If any carry occur during the operation of an addition, carry flag is set or otherwise it is reset. The instruction AND, OR and XOR performs the AND, OR and Exclusive-OR operation between the destination and source registers and the result is stored in destination register. The instruction INC performs the increment operation between the destination and source registers, the value is increased by 1 and the result is stored in destination register. The instruction DEC performs the decrement operation between the destination and source registers, the value is decreased by 1 and the result is stored in destination register. The instruction COM and NEG performs the one s complement and two s complement operation between the destination and source registers. The JMP instruction performs the unconditional jump in the program memory and JNZ and JEQ are conditional jump instruction, they perform jump operation based on zero and carry flag. The CP instruction performs the comparison operation between source and destination registers. If the destination register is higher than source register, carry flag is set other- wise it is in reset. The LRL and LRR operation performs the rotate left and rotate right operation. The MOV instructions perform the data movement between source and destination registers. The MVI instruction performs the movement of an immediate data to the destination register. The LD and ST instruction perform load and store the data to or from the data memory and the base register for this operation is destination register. The LDI instruction perform load of an immediate data to or from the data memory and the base register for this operation is destination register. The IN and OUT operation performs are used to communicate with other I/O devices. The BS and BC instruction performs set and clear the bit position in the destination register. The LSL and LSR instruction perform shift left and shift right operation The NOP instruction perform the no operation, it delays the controller clock by one cycle. Volume 3, Issue 1, January 2015 Page 37

3.RISC MICROCONTROLLER ARCHITECTURE Fig. 3: Internal architecture [2] Figure 3 shows the top-level block diagram of the RISC Microcontroller Architecture.

4 3.RISC MICROCONTROLLER ARCHITECTURE Fig. 3: Internal architecture [2] Figure 3 shows the top-level block diagram of the RISC Microcontroller Architecture. The whole architecture can be divided mainly into five units, Fetch unit, Decode unit, Control unit, and Execute unit and I/O unit. The design uses a program counter of 13-bit, so the program memory depth is (8k x 16). Data memory is of size 256 byte. Fetch unit fetches the instructions from program memory, Decode unit decodes the instructions according to the instruction set architecture, Control unit helps to follow the fetch, decode and execute path and the execute unit is in charge of executing the current instruction. I/O unit provide a connection with the outside world. A.Stage control unit The function of stage control unit to control the flow of execution of an instruction in various stages (Fetch, Decode and Execute. The top-level entity is shown in fig.4 Fig.5:Algorithm : Stage Control Unit [1] Fig. 4: the top-level entity: Stage Control Unit [1] This unit is a combinational unit. Stage control unit checks for the completion signal from one unit and provides an enable signal to the next unit. The algorithm used is shown in fig.5. After the removal of reset signal it is in Fetch_aft_rst state and enables the fetch unit and wait for the completion signal from the fetch unit. If fetch operation is completed then it moves to the Decode state and enables the decode unit. Once the decoding is completed it moves to the Execute state and enables the execution unit. The execution unit completes the operation then it moves to the Fetch state for fetching the new instruction, and the operation continues. B.Fetch Unit The function of the instruction fetch unit is to obtain an instruction from the program memory using the current value of the program counter (PC) and increment the program counter (PC) value for the next instruction. The fetch unit is directly connected to the program memory. It consist of 13-bit program counter which hold the address of next instruction to be executed and a 16-bit Instruction Register (IR) which hold he current instruction to be execute. The top-level entity of fetch unit is shown in fig.6. Volume 3, Issue 1, January 2015 Page 38

Fig.6: Top-level entity: Fetch unit [4] c.decode Unit. Fig.7: Flow chart: Fetch unit [4] Decode unit in the proposed to perform the decoding of the instruction register obtained from the fetch unit.

The input to the decode unit is Inst_reg, a 16 bit register from the fetch unit and output is destination register (3-bit), source register (3-bit), immediate bus (8-bit), Branch address (11-bit),

The immediate bus is used to hold an 8-bit immediate value for immediate data transfers. The branch address bus is a 11-bit bus used to hold the addresses for jump operations.

5 Fig.6: Top-level entity: Fetch unit [4] c.decode Unit. Fig.7: Flow chart: Fetch unit [4] Decode unit in the proposed to perform the decoding of the instruction register obtained from the fetch unit. The toplevel entity of decode is shown in fig.8. The input to the decode unit is Inst_reg, a 16 bit register from the fetch unit and output is destination register (3-bit), source register (3-bit), immediate bus (8-bit), Branch address (11-bit), and a bit position (8 bit). The source and destination register is used to identify the source and destination registers used. The immediate bus is used to hold an 8-bit immediate value for immediate data transfers. The branch address bus is a 11-bit bus used to hold the addresses for jump operations. The Bit_pos bus is an 8-bit used for holding the bit position for the bit set and bit clear operations. Fig.8: Top-level entity: Decode unit [4] Fig.9: Flow chart: Decode unit [4] D.Execution Unit The function of execution unit to perform the execution of the instructions that is already decoded. Top-level entity of execution unit is shown in Fig.10. The execution unit is divided into many subunits to perform operations. Such as a. MOVE unit MOVE unit is designed to perform MVI and MOV instructions. The MVI is move Immediate. It performs the immediate movement of an 8-bit data to destination register. For example MVI A0, Performs the movement of immediate value to the destination register A0. The MOV instruction performs the movement of data Volume 3, Issue 1, January 2015 Page 39

6 between source and destination registers. For example MOV A1, A2; performs the movement of the content of A2 into A1. a. ARITHMETIC unit The ARITHMETIC unit is designed to perform ADD, SUB, MUL, INC and DEC instructions. The ADD, SUB and MUL instruction performs the addition, subtraction and multiplication of content in registers. The example is: - ADD A1, A2. This instruction performs the addition of contents in register A1 and A2. After the addition the result of operation is stored in destination register (A1). If any carry occur during the addition operation a carry flag is set. The content of register A1 is not altered. The INC and DEC instruction performs the increment and decrement of content in registers. For example INC A1, A2. This instruction performs the increment of contents in register A1 and A2. After the increasing the result of operation is stored in destination register (A1). Fig.10: Top-level entity: Execution unit [2] Table.2 b. LOGIC unit The LOGIC unit is designed to perform OR, NOR, XOR, AND, NAND, COM, NEG and CP instructions. The OR, NOR, AND, NAND and XOR instruction is used performs the OR, NOR, AND, NAND and Exclusive-OR operation between the source and destination registers. The example is: -XOR A1, A2. This instruction performs the Exclusive- OR operation between registers A1 and A2. After the execution of operation the result is stored on to the register A2. The content of register A2 is not altered. If the result of operation is zero then a zero flag is set. The CP instruction is used to perform comparison between source and destination registers. The example is: - CP A1, A2. This instruction performs the comparison operation between registers A1 and A2. After the execution of operation the result is stored on to the register A2. If the contents of registers are same the zero flag is set or otherwise it is reset. The content of registers is not altered after the execution. The COM instruction is used performs the One s complement operation using the source registers. The example is: One s complement A1, NOT A1. This instruction performs the One s complement operation of registers A1. After the execution of operation the result is stored on to the same register A1. If the result of operation is zero then a zero flag is set. The NEG instruction is used performs the Two s complement operation using the source registers. The example is: Two s complement A1, NOT A1+1. This instruction performs the Two s complement operation of registers A1. After the execution of operation the result is stored on to the same register A1. If the result of operation is zero then a zero flag is set. c. LOAD_STORE unit The LOAD_STORE unit is designed to perform LD and ST instructions. The base register used for load and store operation is A0. The LD instruction is used to perform the LOAD operation. As a part of instruction an 8-bit data Volume 3, Issue 1, January 2015 Page 40

memory address is specified. For example LD 00101010 instruction loads the content of memory location 00101010 (0x2A H) in the base register A0.

7 memory address is specified. For example LD instruction loads the content of memory location (0x2A H) in the base register A0. The ST instruction is used to perform the STORE operation. The memory address is specified a part of the instruction. For example ST d. JUMP unit The JUMP unit is designed to perform JMP, JNZ and JEQ instructions. They performs the jump in program memory. The jump address is specified as a part of instruction. The JMP is an unconditional jump instruction and JNZ and JEQ are conditional jump instruction. The maximum supported jump in program memory is This unit works on the content of Status of flag registers. The examples are JMP 0x02A, JNZ 0x12F, JEQ 0X2BF. In the instruction JMP 0x02A, it jumps to the program memory location 0x02A.For this instruction only the program counter (PC) value is substituted with jump address. e. IN_OUT unit The IN and OUT instructions used to transfer the data to and from the Input/output ports. The IN instruction stores the data from port to the base register A0. The OUT instruction stores the data on to the I/O port from base register A0.The address of ports are shown in Table. For example IN , OUT The IN instruction stores the status of the port to the base register R0. The OUT instructions load the base register on to the port All the ports are directly mapped to the first four locations in the data memory as shown in table.2 f. SET_CLEAR unit The SET_CLEAR unit is used to perform bit setting and resetting of the specified register. This operation is done by specifying the bit position as a part of the instruction. The example is BS A0, This instruction sets (high) the first position in the A0 register. Also BC A0, , this instruction resets (zero) the zero bit position in A0 register. g. NOP Unit The NOP unit is used to perform the no operation. This operation used to wait the operation of the controller to 3 clock cycle. Only op-code is used as a part of the instruction. It doesn t alter the content of any register. h. SHIFT unit The LSR and LSL instruction is used performs the logical shift right and logical shift left operation using the source registers. This operation is done by shifting the bit position (right/left) as a part of the instruction. For example LSR A1, This instruction sets (high) the first position in the A1 register. i. ROTATE unit The LRR and LRL instruction are used to perform the logical rotate right and logical rotate left operation using the source registers. This operation is done by rotating the bit position as a part of the instruction. for example LRR A1, This instruction sets (high) the last position in the A1 register. and instruction LRR A1, sets (high) the first position in the A1 register. 4.SIMULATION RESULTS The proposed RISC Microcontroller is designed using VHDL and simulated using ModelSim 6.5ISE. Each operation is verified by performing the simulation where the code is placed on the program memory. Fig.11 shows MVI A0 ( ) operation, the movement of data immediately to destination register and the value is stored in register file. Fig 12 shows the addition of content of A0 ( ) and A1 ( ). Fig. 11: MVI A0, Volume 3, Issue 1, January 2015 Page 41

8 Fig.12: ADD A0, A1 5.COMPARISON WITH DIFFERENT MICROCONTROLLER Table.3: Comparison 6.CONCLUSION The designing of the 8-bit RISC Microcontroller using VHDL presented in this paper. Design of each module (Fetch, Decode, Execute, and Stage Control Unit.) has been done independently using structural programming. This Microcontroller supports 30 instructions. It executes all the instructions in single clock cycle, including jumps, multiplication, comparison and external accesses. Table.3 is the comparison chart between different Microcontroller and current design. The analysis shows that all the instructions execute in one machine cycle in current design while in Sim2 and ATMEL AD8051 Microcontroller most of the instruction execute in two or three cycles hence the speed is much faster in current design than Sim2 Microcontroller. This Microcontroller can support maximum frequency up to MHz and maximum clock period is ns. The delay of the Microcontroller is ns. REFERENCES [1] Aneesh.R, Jiju.K, Design of FPGA based 8-bit RISC controller IP core using VHDL, IEEE, 13 th International Conference On Computer Modeling and Simulation. pp [2] Deepak Kumar, K.Anusudha, RISC SYSTEM DESIGN IN XILINX. International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering Vol. 2, Issue 4, April Volume 3, Issue 1, January 2015 Page 42

[3] Yap Zi He, Building A RISC Microcontroller in an FPGA, International Joint Conference On Artificial Intelligence. March 2002. [4] Mrs. Rupali S. Balpande, Mrs.Rashmi S.

9 [3] Yap Zi He, Building A RISC Microcontroller in an FPGA, International Joint Conference On Artificial Intelligence. March [4] Mrs. Rupali S. Balpande, Mrs.Rashmi S. Keote, Design of FPGA based Instruction Fetch & Decode module of 32- bit RISC (MIPS) Processor. International Conference on Communication Systems and Network Technologies. pp [5] Victor P. Rubio, A FPGA Implementation of a MIPS RISC processor for Computer Architecture Education. International SOC Design Conference, New Maxico [6] R.Uma, Design & Performance Analysis of 8-bit RISC Processor using Xilinx. IJERA Vol -2, Issue 2,. pp April AUTHOR Krishna Kumar Mishra received the B. Tech degree in Electronics & Communication Engineering from U.P. Technical University in Presently he is pursuing the M. Tech degree in Electronics & Communication Engineering from U.P. Technical University. During he has taught in one of the best engineering College of U.P. Technical University. He has a master skill in Microprocessor, Microcontroller, VLSI design and Electronic Circuit. Volume 3, Issue 1, January 2015 Page 43

Design of 16-bit RISC Processor Supraj Gaonkar 1, Anitha M. 2

Design of 16-bit RISC Processor Supraj Gaonkar 1, Anitha M. 2 1 M.Tech student, Sir M Visvesvaraya Institute of Technology Bangalore. Karnataka, India 2 Associate Professor Department of Telecommunication