Computer Structure. Unit 4. Processor

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1 Computer Structure Unit 4. Processor Departamento de Informática Grupo de Arquitectura de Computadores, Comunicaciones y Sistemas UNIVERSIDAD CARLOS III DE MADRID

2 Contents Computer elements Processor organization Registers ALU Control unit Interconnections Control unit Execution of instructions Execution modes Computer startup Interrupts Control unit design Performance and parallelism ARCOS-UC3M Computer Structure 2

3 Computer elements 3 Processor Main memory Bus I/O module I/O module I/O module Peripheral Peripheral Peripheral ARCOS-UC3M Computer Structure 3

4 Interconection 4 Processor Main memory Data bus Address bus Control bus I/O module I/O module I/O module Peripheral Peripheral Peripheral ARCOS-UC3M Computer Structure 4

5 Motherboard ARCOS-UC3M Computer Structure 5

6 Processor elements 6 Registers Arithmetic logic unit Control unit Cache memory ARCOS-UC3M Computer Structure 6

7 Registers n Element that stores a set of bits Register Load n There can be other signal to reset the register ARCOS-UC3M Computer Structure 7

8 Registers 8 n Register n Input Load Load Falling edge content Output ARCOS-UC3M Computer Structure 8

9 Types of registers Visible to programmers Not visible Temporary registers Control and state registers Program counter, PC Instruction register, RI Memory address register, MAR Memory buffer register, MBR Program status word, PWS ARCOS-UC3M Computer Structure 9

10 Register file (register bank) 10 Set of registers that can be read and written by supplying a register number to be accessed Number of register is power of 2: n registers log 2 n bits for the selection. k bits of selection 2 k registers. Fast element ARCOS-UC3M Computer Structure 10

11 Register file 11 A n B n RA RB RC k k k 0 1 SC 2 k -1 E n ARCOS-UC3M Computer Structure 11

12 Register file 12 A n B n RA RB k k 0 1 With 32 registers, k=5 RC k SC 2 k -1 E n ARCOS-UC3M Computer Structure 12

13 13 Register file A n B What is the value of RA to obtain the content of register 14? n RA RB RC k k k 0 1 SC 2 k -1 E n ARCOS-UC3M Computer Structure 13

14 Scheme for reading A B RA k k -1 M U X RB k M U X ARCOS-UC3M Computer Structure 14

15 Arithmetic logic unit (ALU) 15 A B n n OP p 2 p operations n R Carry Overflow Zero Positive Negative PWS ARCOS-UC3M Computer Structure 15

16 Control Unit 16 Rest of the processor Control unit Control signal Clock signal Value of every control signal in every clock cycle ARCOS-UC3M Computer Structure 16

17 Memory access 17 L E Memory n ADDR Address n DATA Datum ARCOS-UC3M Computer Structure 17

18 Tristate buffer 18 E S E C S 0 0 Z 1 0 Z C ARCOS-UC3M Computer Structure 18

19 Bus access 19 CA CB CC RA RB RC TA TB TC Bus ARCOS-UC3M Computer Structure 19

20 Example What control signals must be activated to copy the content of RA in RB? CA CB CC RA RB RC TA TB TC Bus ARCOS-UC3M Computer Structure 20

21 Datapath (RB RA) 21 CA CB CC RA RB RC TA TB TC Bus All control signals deactivated ARCOS-UC3M Computer Structure 21

22 Datapath (RB RA) 22 CA CB CC RA RB RC TA TB TC Bus ARCOS-UC3M Computer Structure 22

23 23 Structure of a computer based on internal bus ARCOS-UC3M Computer Structure 23

24 Other registers PC: program counter IR: instruction register SP: stack pointer MAR: memory address register MBR: memory buffer register PSW: program status word Transparent registers: RT1, RT2, RT3. ARCOS-UC3M Computer Structure 24

25 Features bit computer Memory addressed by bytes One cycle per read and write operations 32 registers R0..R31 As in the MIPS: R0 = 0 y SP = R29 Registers not visible: RT1, RT2, RT3 Other registers for control and state MAR, MBR, PC, PSW, RI ARCOS-UC3M Computer Structure 25

26 Register-transfer level design Register-transfer level language (RTL) Register 1 Register 2 Specifies what happens in the computer using transfers among registers ARCOS-UC3M Computer Structure 26

27 Elemental operations Transfer operations: MAR PC Process operations: R1 R2 + RT2 RTL Specifies transfers among registers Specifies what happens in the computer using transfers among registers ARCOS-UC3M Computer Structure 27

28 Control signals ARCOS-UC3M Computer Structure 28

29 Controls signals Signals for memory access Signals for load in registers Signal to control tristate gates Signals to select MUX Signals to control the register file (RA, RB, RC y SC) ARCOS-UC3M Computer Structure 29

30 Control signals 30 Control signal activated in every clock cycle Can be obtained from RTL Elemental Op. MAR PC Control signals activated T4, C1 R1 R2 + RT1 RB = (R2) MA = 1 MB = 0 Cod Op. ADD T5 RC = (R1) SC ARCOS-UC3M Computer Structure 30

31 Register file ARCOS-UC3M Computer Structure 31

Control signals of the register file A, B: output gates E: imnput gate Tx : tristate activation signal Rx : Register selection signal SC: Signal to load in register Register bank (RB): A: output of

32 Control signals of the register file A, B: output gates E: imnput gate Tx : tristate activation signal Rx : Register selection signal SC: Signal to load in register Register bank (RB): A: output of BR B: output of BR E: input in BR RA: register selection by A RB: register selection by B RC: register selection by E SC: write in register (load) selected by SC T1: Output of RB to internal bus T2: Output of RB to internal bus ARCOS-UC3M Computer Structure 32

33 Registers Bank Example Control signals for the operation R1 R2, where R1 is the register 1 and R2 is the register 2: RA = RC = T1 y SC Rest of signal: 0 clock RA RC T1 SC Clock cycle Load in negative edge-triggered, when signal changes from high to low. The datum is available in R1 in next cycle ARCOS-UC3M Computer Structure 33

34 Memory and associated registers Main memory, MBR and MAR ARCOS-UC3M Computer Structure 34

Control signal for memory access MAR: memory address register MBR : memory buffer register Tx: Tristate activation signal Cx: signal to load in register Main memory R: Read W: Write C1: from

35 Control signal for memory access MAR: memory address register MBR : memory buffer register Tx: Tristate activation signal Cx: signal to load in register Main memory R: Read W: Write C1: from internal bus to MAR C2: from data bus to MBR C3: from internal bus to MBR Td: output of MAR to address bus Ta: output of MBR to data bus T3: output of to internal bus ARCOS-UC3M Computer Structure 35

36 Memory access operations Read: MAR <address> (C1) Read cycle (R) MBR MP[Address] (..., C2) Write: MAR <address> (..., C1) MBR <datum> (..., C3) Write cycle(w) ARCOS-UC3M Computer Structure 36

00001, SC (R2 MBR) Clock RA RC 00010 00001 Clock cycle T1 SC Load in negative edge-triggered, when

37 Example of memory access Control signal for R2 Memoria[R1]: First cycle: RA = 00001, T1, C1 (MAR R1) Second cycle (assuming one cycle per read operation): Td, L, C2 (MBR Memory) Third cycle: T3, Rc = 00001, SC (R2 MBR) Clock RA RC Clock cycle T1 SC Load in negative edge-triggered, when signal changes from high to low. The datum is available in R1 in next cycle ARCOS-UC3M Computer Structure 37

38 Memory access example Chronogram and control signal Reloj RA RC First cycle: RA = 00001, T1, C1 (MAR R1) Second cycle: Td, L, C2 (MBR Memory) Third cycle: T3, Rc = 00001, SC (R2 MBR) T1 C1 C2 Td L SC T3 Rest of signals: 0 ARCOS-UC3M Computer Structure 38

39 Arithmetic and logic unit (ALU) ARCOS-UC3M Computer Structure 39

40 Control signals ALU C9: internal bus to register RT1 C10: internal bus to register RT2 MA: operand selector: A ó RT1 MB: operand selector: B ó RT2 Cod. OP: operation to perform in ALU (+,-,AND, OR, ) C11: ALU result to register RT3 T5: ALU result to internal bus T6: output of RT3 to internal bus ARCOS-UC3M Computer Structure 40

41 Example of operations Operation Op. code Adition 000 substraction 001 Mult. 010 División 011 And 100 Or 101 Xor 110 Not (sobre MA) 111 ARCOS-UC3M Computer Structure 41

42 Example of operation in the ALU Control signal for RT3 R1 + RT1: MA = 1, MB = 0 RB = C11 Cod.Op = 000 clock RB MA C Clock cycle Load in negative edge-triggered, when signal changes from high to low. The datum is available in R1 in next cycle Cod. Op Rest of signals: ARCOS-UC3M Computer Structure 42

43 Control unit Control unit with PC, IR, and PSW ARCOS-UC3M Computer Structure 43

44 PC, IR, and PSW registers Program counter (PC): contains the address of the instruction to be fetched Instruction register (IR): contains the instruction recently fetched Program status word (PSW): contains status information: Information about last operation in ALu. Bits to indicate: sign, Zero, carry, overflow, etc. Execution mode: bit that indicates whether CPU is executing in supervisor or user mode Interrupt enable/disable ARCOS-UC3M Computer Structure 44

45 PC, IR, and PSW registers and control signals Program counter, PC: C4: PC PC + 4 C5: internal bus to PC T4: PC to internal bus Program status word, PSW C7: internal bus to PSW C8: ALU flags to PSW T7: PSW to internal bus Instruction register, IR: C6: internal bus to IR T8: IR to internal bus ARCOS-UC3M Computer Structure 45

46 Control unit Basic functions: Fetch instructions from memory Decoding Instruction execution Start Fetch Decoding Execution Stop ARCOS-UC3M Computer Structure 46

47 Clock A computer is synchronous cycle The clock controls the behavior The clock controls the operations In a clock cycle one o more elemental operations are executed if there are not conflicts In one cycle the needed control signals are activated In the same cycle, following operations can be perform: MAR PC y RT3 RT2 + RT1 In the same cycle, following operations cannot be perform: MAR PC y R1 RT3 Why? ARCOS-UC3M Computer Structure 47

48 Exercise What is the cycle of a computer with a clock frequency of 1 GHz? ARCOS-UC3M Computer Structure 48

49 Instruction cycle 49 Instruction fetch Fetch (read) the instruction stored in the memory address stored in PC. The instruction is stored in IR. Increment PC Decoding: Interpret the instruction stored in IR in order to select: Operation to do Addressing to apply Control signals to activate Execution Perform the indicated operation activating the appropriate control signals ARCOS-UC3M Computer Structure 49

50 Example: Fetch 50 Cycle Elemental op. C1 MAR PC C2 PC PC + 4 C3 MBR MP C4 IR MBR Cycle Elemental op. C1 MAR PC C2 PC PC + 4, MBR MP C3 IR MBR Simultaneous operations can be made ARCOS-UC3M Computer Structure 50

51 Fetch (c1) 51 C1: MAR PC C2: PC PC + 4, MBR MP C3: IR MBR ARCOS-UC3M Computer Structure 51

52 Fetch (c2) 52 C1: MAR PC C2: PC PC + 4, MBR MP C3: IR MBR ARCOS-UC3M Computer Structure 52

53 Fetch (c3) 53 C1: MAR PC C2: PC PC + 4, MBR MP C3: IR MBR ARCOS-UC3M Computer Structure 53

54 Control signals in fetch 54 Control signals activated in fetch. Obtained from RTL Cycle Elemental Op. Control signals activated C1 MAR PC T4, C1 C2 PC PC + 4, MBR MP C4, Td, L, C2 C3 IR MBR T3, C6 ARCOS-UC3M Computer Structure 54

55 Execution of lw $reg, addr Cycle C1 Elemental op. MAR PC C2 PC PC + 4, MBR MP C3 C4 C5 C6 C7 MBR MP Decoding MAR IR(addr) MBR MP $Reg MBR ARCOS-UC3M Computer Structure 55

56 Execution of jal addr Cycle C1 Elemental OP. MAR PC C2 PC PC + 4, MBR MP C3 C4 C5 IR MBR Decoding PC addr ARCOS-UC3M Computer Structure 56

57 57 Exercise: Elemental operations for these instructions Instructions in one word: sw $reg, dir add $rd, $ro1, $ro2 addi $rd, $ro1, inm lw $reg1, desp($reg2) j dir jr $reg beq $ro1, $ro2, desp ARCOS-UC3M Computer Structure 57

58 Instructions that occupy several words Example: addm R1, addr R1 R1 + [addr] format: addm R1 addr 1st word 2nd word Cycle C1 Elemenal Op. MAR PC C2 PC PC + 4, MBR MP C3 C4 C5 IR MBR Decoding MAR PC Cycle C6 C7 C8 C9 C10 Elemenal Op. MBR MP, PC PC + 4 MAR MBR MBR MP RT1 MBR R1 R1 + RT1 ARCOS-UC3M Computer Structure 58

59 Execution modes User mode Processor cannot execute privileged instructions (I/O instructions, interrupt enabled, ) When an user process executes a privileged instruction, the processor generates an interrupt Kernel (supervisor) mode Reserved to operating system Processor can execute all instructions The mode is indicates using a bit in the PSW register ARCOS-UC3M Computer Structure 59

60 Interrupts Signal received in control unit. Break the normal sequence of execution Reasons: Error in the execution of an instruction (division by zero, ) Illegal instruction Illegal memory access Device that requests the attention of the processor Clock. Clock interrupts When an interrupt is generated, the current program is stopped and the execution is transferred to another program that manages the interrupt ARCOS-UC3M Computer Structure 60

61 Interrupts classification Synchronous HW exceptions Division by zero, illegal memory access, Asynchronous HW exceptions HW errors External interrupts Devices, clock interrupt System calls Machine instructions that provoke an interrupt used to activate the operating system ARCOS-UC3M Computer Structure 61

62 Interrupt handling Interrupts disabled Start Fetch Instruciton execution Interrupt cycle Iinterrupts enabled Stop ARCOS-UC3M Computer Structure 62

63 Interrupt cycle In this cycle, control unit: Check interrupts. If there are activated interrupts: Save PC and PSW Change from user mode to kernel mode Get the address of the interrupt handling routine Load in PC the above address (next instruction will be the first instruction of the interrupt handling routine) ARCOS-UC3M Computer Structure 63

64 Interrupt handling routine Belongs to operating system Saves the rest or processor registers Processes the interrupt Restores the registers previously saved Executes the machine instruction: RETI Restores the PSW of the interrupted program (changes from kernel mode to user mode again) Restores PC (next instruction executed will be one of the previously interrupted program) ARCOS-UC3M Computer Structure 64

65 Interrupt vector table Operating system Memory Element that interrupts INT vector Control unit vector Interrupt handling routine ARCOS-UC3M Computer Structure 65

66 Interrupt vector table An element that activates an interrupt provides the interrupt vector This vector is an index into the interrupt vector table This table contains the address for each interrupt handling routine Control unit reads the address of the vector table and load this value in PC Every operating system fills this table with the addresses of the interrupt handling routines. This addresses are operating system dependent ARCOS-UC3M Computer Structure 66

67 PC interrupts (Windows 7) ARCOS-UC3M Computer Structure 67

68 Software interrupts system call (example: Linux) close(fd) ; Aplication User mode close(int desc) { MOVE %eax, #NUM_CLOSE MOVE %ebx, desc INT 0x80 %eax = returned value RET } libc.so Instruction that provokes A SW interrrupt Kernel mode _sys_call_table _system_call( ) sys_call_table(%eax) ret_from_sys_call _ret_from_syscall rescheduling sys_close() ARCOS-UC3M Computer Structure 68

69 Control unit design IR CO PSW Interupts Control unit Control signals Clock Every control signal is a function of the value of: IR content PSW content Period of time (clock) ARCOS-UC3M Computer Structure 69

70 Control unit design For each machine instruction: Define, using RTL, the behavior of every clock cycle Translate this behavior to control signals values in every clock cycle Design a circuit to generate the value of every control signal in every clock cycle ARCOS-UC3M Computer Structure 70

71 Example of state machine Example for a computer with 4 instructions machine add r1, r2 lw r1, addr bz dir sw r1 ARCOS-UC3M Computer Structure 71

72 Control techniques Hardwired implementation Microprogrammed control ARCOS-UC3M Computer Structure 72

73 Hardwired control Control unit uses gates. Its inputs logic signals are transformed intro a set of output logic signals Features: Very fast Difficult to modify Redesign ARCOS-UC3M Computer Structure 73

74 Microprogrammed control unit Basic idea: use a memory (control memory) to store the control signal values for each period of each instruction Features: Easy modification Updates, etc.. Ej.: PSP, IPhone, etc. Simplify the design ARCOS-UC3M Computer Structure 74

75 Microprogrammed control unit IR PSW Interrupt signals CO Clock signal Sequencing logic C1 C2 C3 C4 R5 C6 C7 C8 C9 C10 C11 Td Ta T1 T2 T3 T4 T5 T6 T7 T8 RA4 RA3 RA2 Ra Control memory RB4 Rb3 RB2 RB1 RB0 RC4 RC3 RC2 RC1 RC0 SC L E Cop3 Cop2 Cop1 Cop Microinstruction Control signals ARCOS-UC3M Computer Structure 75

76 Microinstructions Each control memory word defines the value of each control signal in a period Microinstruction A microinstruction includes a bit for each control signal ARCOS-UC3M Computer Structure 76

77 Microcode and microprogram Microprogram: Set of microinstruction for each machine instruction Microcode(firmware): Set of microprograms of a computer ARCOS-UC3M Computer Structure 77

78 Basic structure of a microprogrammed control unit Three elements: Control memory to store all microinstructions. Procedure to associate to each machine instruction the appropriated microprogram Procedure that converts the operation code of a machine instruction into the address of the control memory where the program is stored Mechanism to obtain the rest of microinstructions Two alternatives: Explicit sequencing Implicit sequencing ARCOS-UC3M Computer Structure 78

79 Explicit sequencing Each microinstruction includes the address of the next microinstruction Control memory with great capacity ARCOS-UC3M Computer Structure 79

80 Implicit sequencing All instructions of a microprogram are stored consecutively in memory Need: Translation step (ROM o PLA) Microaddresses register ARCOS-UC3M Computer Structure 80

81 Microinstruction format Microinstruction format: Specify the number of bits and the control signals Signals grouped into fields: Tristate bus signals ALU signals Registers bank signals Memory signals Multiplexor signals ARCOS-UC3M Computer Structure 81

82 Startup of a computer ROM init. The reset loads predefined values in registers: PC address of the init program (ROM memory) Execute the init program System test Load in memory the operating system loader PC init address of the operating system loader Execute the operating system loader program to load the rest of the operating system Execute the operating system OS loader Rest of OS ARCOS-UC3M Computer Structure 82

83 Model of processor based on datapath (without internal bus) PC +4 Instructions Memory Registers Banck Data memory ARCOS-UC3M Computer Structure 83

84 Program execution time = _ + _ N is the number of instructions of the program CPI is the average number of clock cycles to execute an instruction t CPU_cycle is the cycle clock duration AMI is the average number of memory access per instruction t mem_cycle is the time needed for a memory access ARCOS-UC3M Computer Structure 84

85 Instruction level parallelism Concurrent execution of several machine instructions Pipielined processor : use pipelines in which multiple instructions are overlapped in execution Superscalar processor: multiple independent instruction pipelines are used. Each pipeline can handle multiple instructions at a time Multicore processor: several processors or cores in the same chip ARCOS-UC3M Computer Structure 85

86 Pipelining Stages in the execution of instructions IF: instruction fetch D: Decoding RO: read operands EX: execution WO: write operands ARCOS-UC3M Computer Structure 86

87 Execution without pipeline Time IF D RO EX WO IF D RO EX WO If each stage consumes N clock cycles, one instruction is executed every 5 x N cycles ARCOS-UC3M Computer Structure 87

88 Execution with pipeline Time RI D RO EX WO IF D RO EX WO IF D RO EX WO IF D RO EX WO If each stage consumes N clock cycles, one instruction is executed every N cycles ARCOS-UC3M Computer Structure 88

89 Superscalar Time IF D RO EX WO IF D RO EX WO IF D RO EX WO IF D RO EX WO IF D RO EX WO IF D RO EX WO IF D RO EX WO IF D RO EX WO Several independent pipelines ARCOS-UC3M Computer Structure 89

90 Multicores Multiples processors in the same chip ARCOS-UC3M Computer Structure 90

CPU Structure and Function

CPU Structure and Function Chapter 12 Lesson 17 Slide 1/36 Processor Organization CPU must: Fetch instructions Interpret instructions Fetch data Process data Write data Lesson 17 Slide 2/36 CPU With Systems