CPU Organization (Design)

Transcription

1 ISA Requirements CPU Organization (Design) Datapath Design: Capabilities & performance characteristics of principal Functional Units (FUs) needed by ISA instructions (e.g., Registers, ALU, Shifters, Logic Units,...) Components Ways in which these components are interconnected (buses connections, multiplexors, etc.). Connections How information flows between components. Control Unit Design: Components & their connections needed by ISA instructions Control/sequencing of operations of datapath components to realize ISA instructions Logic and means by which such information flow is controlled. Control and coordination of FUs operation to realize the targeted Instruction Set Architecture to be implemented (can either be implemented using a finite state machine or a microprogram). Hardware description with a suitable language, possibly using Register Transfer Notation (RTN). 4 th Edition Chapter rd Edition Chapter EECC55 - Shaaban # Lec # 4 Winter

2 Major CPU Design Steps Analyze instruction set to get datapath requirements: Using independent RTN, write the micro-operations required for target ISA instructions. 2 This provides the the required datapath components and how they are connected. 2 Select set of datapath components and establish clocking methodology (defines when storage or state elements can read and when they can be written, e.g clock edge-triggered) e.g Flip-Flops 3 Assemble datapath meeting the requirements. 4 Identify and define the function of all control points or signals needed by the datapath. Analyze implementation of each instruction to determine setting of control points that affects its operations. 5 Control unit design, based on micro-operation timing and control signals identified: Combinational logic: For single cycle CPU. Hard-Wired: Finite-state machine implementation. i.e CPI = Microprogrammed. ISA Requirements CPU Design e.g Any instruction completed in one cycle EECC55 - Shaaban #2 Lec # 4 Winter

3 CPU Design & Implantation Process Top-down Design: Specify component behavior from high-level requirements (ISA). Bottom-up Design: Assemble components in target technology to establish critical timing (hardware delays, critical path timing). Iterative refinement: Establish a partial solution, expand and improve. Instruction Set Architecture (ISA): Provides Requirements Datapath Processor ISA Requirements Control CPU Design Reg. File Mux ALU Reg Mem Decoder Sequencer Target VLSI implementation Technology Cells Gates EECC55 - Shaaban #3 Lec # 4 Winter

4 Datapath Design Steps Write the micro-operation sequences required for a number of representative target ISA instructions using independent RTN. Independent RTN statements specify: the required datapath components and how they are connected. 2 From the above, create an initial datapath by determining possible destinations for each data source (i.e registers, ALU). This establishes connectivity requirements (data paths, or connections) for datapath components. Whenever multiple sources are connected to a single input, a multiplexor of appropriate size is added. (or destination) Find the worst-time propagation delay (critical path) in the datapath to determine the datapath clock cycle (CPU clock cycle, C). Complete the micro-operation sequences for all remaining instructions adding datapath components + connections/multiplexors as needed. EECC55 - Shaaban #4 Lec # 4 Winter

5 MIPS Instruction Formats R-Type op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits [3:26] [25:2] [2:6] [5:] [:6] [5:] I-Type: ALU Load/Store, Branch J-Type: Jumps op rs rt Immediate (imm6) 6 bits 5 bits 5 bits 6 bits 26 2 [3:26] [25:2] [2:6] [5:] op target address 6 bits 26 bits op: Opcode, operation of the instruction. rs, rt, rd: The source and destination register specifiers. shamt: Shift amount. funct: Selects the variant of the operation in the op field. address / immediate: Address offset or immediate value. target address: Target address of the jump instruction. 6 [3:26] [25:] EECC55 - Shaaban #5 Lec # 4 Winter Or address offset

6 MIPS R-Type R (ALU) Instruction Fields Opcode for R-Type= R-Type: All ALU instructions that use three registers OP rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits [3:26] [25:2] [2:6] [5:] [:6] [5:] op: Opcode, basic operation of the instruction. For R-Type op = Independent RTN: rs: The first register source operand. rt: The second register source operand. rd: The register destination operand. shamt: Shift amount used in constant shift operations. funct: Function, selects the specific variant of operation in the op field. Funct field value examples: Add = Sub = 34 AND = 36 OR =37 NOR = 39 st operand 2nd operand Destination Destination register in rd Operand register in rs Rs, rt, rd are register specifier fields Function Field Instruction Word R[rd] R[rs] funct R[rt] PC PC + 4 Mem[PC] Operand register in rt Examples: R-Type = Register Type Register Addressing used (Mode ) add $,$2,$3 sub $,$2,$3 and $,$2,$3 or $,$2,$3 EECC55 - Shaaban #6 Lec # 4 Winter

7 MIPS ALU I-Type I Instruction Fields I-Type ALU instructions that use two registers and an immediate value Loads/stores, conditional branches. st operand Destination 2nd operand OP rs rt Immediate (imm6) 6 bits 5 bits 5 bits 6 bits [3:26] [25:2] [2:6] [5:] imm6 op: Opcode, operation of the instruction. rs: The register source operand. rt: The result destination register. immediate: Constant second operand for ALU instruction. imm6 OP = 8 Examples: OP = 2 I-Type = Immediate Type Immediate Addressing used (Mode 2) Result register in rt add immediate: addi $,$2, and immediate andi $,$2, imm6 = 6 bit immediate field Independent RTN for addi: Instruction Word R[rt] R[rs] + imm6 PC PC + 4 Source operand register in rs Mem[PC] Constant operand in immediate EECC55 - Shaaban #7 Lec # 4 Winter

8 MIPS Load/Store I-Type I Instruction Fields Examples: Base OP rs rt address 6 bits 5 bits 5 bits 6 bits op: Opcode, operation of the instruction. For load word op = 35, for store word op = 43. rs: The register containing memory base address. rt: For loads, the destination register. For stores, the source register of value to be stored. address: 6-bit memory address offset in bytes added to base register. imm6 source register in rt Offset Store word: sw $3, 5($4) Load word: lw $, ($2) Destination register in rt Base or Displacement Addressing used (Mode 3) Src./Dest. [3:26] [25:2] [2:6] [5:] Offset base register in rs imm6 = 6 bit immediate field (e.g. offset) imm6 base register in rs Signed address offset in bytes Sign Extended Instruction Word Mem[PC] Mem[R[rs] + imm6] R[rt] PC PC + 4 Instruction Word Mem[PC] R[rt] Mem[R[rs] + imm6] PC PC + 4 EECC55 - Shaaban #8 Lec # 4 Winter

9 MIPS Branch I-Type I Instruction Fields OP rs rt address 6 bits 5 bits 5 bits 6 bits imm6 [3:26] [25:2] [2:6] [5:] Signed address offset in words op: Opcode, operation of the instruction. Word = 4 bytes rs: The first register being compared rt: The second register being compared. address: 6-bit memory address branch target offset in words added to PC to form branch address. imm6 OP = 4 Examples: OP = 5 Independent RTN for beq: PC-Relative Addressing used (Mode 4) Register in rs Register in rt Branch on equal beq $,$2, Branch on not equal bne $,$2, Sign extended Instruction Word Mem[PC] R[rs] = R[rt] : PC PC imm6 x 4 R[rs] R[rt] : PC PC + 4 imm6 = 6 bit immediate field (e.g. offset) offset in bytes equal to instruction address field x 4 Added to PC+4 to form branch target Imm6 x 4 EECC55 - Shaaban #9 Lec # 4 Winter

10 MIPS J-Type J Instruction Fields J-Type: Include jump j, jump and link jal OP jump target 6 bits 26 bits op: Opcode, operation of the instruction. Jump j op = 2 Jump and link jal op = 3 jump target: jump memory address in words. Examples: [3:26] [25:] Jump j Jump and link jal Jump target in words Word = 4 bytes Jump memory address in bytes equal to instruction field jump target x 4 Effective -bit jump address: PC(3-28),jump_target, PC(3-28) From jump target = 25 PC+4 4 bits 26 bits 2 bits Independent RTN for j: Instruction Word Mem[PC] PC PC + 4 PC PC(3-28),jump_target, J-Type = Jump Type Pseudodirect Addressing used (Mode 5) EECC55 - Shaaban # Lec # 4 Winter

11 R I I ADD and SUB: add rd, rs, rt sub rd, rs, rt OR Immediate: ori rt, rs, imm6 LOAD and STORE Word lw rt, rs, imm6 3 sw rt, rs, imm6 A Subset of MIPS Instructions 3 35 = lw 43 = sw op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits [3:26] [25:2] [2:6] [5:] [:6] [5:] op rs rt Immediate (imm6) 6 bits 5 bits 5 bits 6 bits [3:26] [25:2] [2:6] [5:] op rs rt Immediate (imm6) 6 bits 5 bits 5 bits 6 bits [3:26] [25:2] [2:6] [5:] = add 34 = sub Offset in bytes I BRANCH: beq rs, rt, imm op rs rt Immediate (imm6) 6 bits 5 bits 5 bits 6 bits [3:26] [25:2] [2:6] [5:] Offset in words EECC55 - Shaaban # Lec # 4 Winter

12 Basic MIPS Instruction Processing Steps Instruction/program Memory Instruction Fetch Next Instruction Instruction Decode Obtain instruction from program storage Instruction Mem[PC] Update program counter to address of next instruction PC PC + 4 Determine instruction type Obtain operands from registers Common steps for all instructions Execute Result Store Compute result value or status Store result in register/memory if needed (usually called Write Back). Done by Control Unit (Based on Opcode) T = I x CPI x C EECC55 - Shaaban #2 Lec # 4 Winter

13 Overview of MIPS Instruction Micro-operations operations All instructions go through these common steps: Send program counter to instruction memory and fetch the instruction. (fetch) Instruction Mem[PC] Common Steps Update the program counter to point to next instruction PC PC + 4 one or two registers, using instruction fields. (decode) Load reads one register only. Additional instruction execution actions (execution) depend on the instruction in question, but similarities exist: All instruction classes (except J type) use the ALU after reading the registers: Memory reference instructions use it for effective address calculation. Arithmetic and logic instructions (R-Type), use it for the specified operation. Branches use it for comparison. Additional execution steps where instruction classes differ: Memory reference instructions: Access memory for a load or store. Arithmetic and logic instructions: Write ALU result back in register. Branch instructions: Possibly change next instruction address (update PC) based on comparison (i.e if branch is taken). EECC55 - Shaaban #3 Lec # 4 Winter

14 A Single Cycle MIPS CPU Design Design target: A single-cycle per instruction MIPS CPU design All micro-operations of an instruction are to be carried out in a single CPU clock cycle. Cycles Per Instruction = CPI = CPU Performance Equation: T = I x CPI x C CPI = 4 Add Add Abstract view of single cycle MIPS CPU showing major functional units (components) and major connections between them Data PC A ddress Instruction Inst ruct ion memory ISA Register # Re g ist er s ALU Address Register # Register # Dat a memory Data 4 th Edition Figure 4. page 32-3 rd Edition Figure 5. page 287 EECC55 - Shaaban #4 Lec # 4 Winter

15 R-Type Example: Micro-Operation Sequence For ADD add rd, rs, rt = add 34 = sub OP rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits [3:26] [25:2] [2:6] [5:] [:6] [5:] Instruction Word Mem[PC] Fetch the instruction PC PC + 4 Increment PC R[rd] R[rs] + R[rt] Memory Add register rs to register rt result in register rd Independent RTN? Program i.e Funct =add = Common Steps EECC55 - Shaaban #5 Lec # 4 Winter

16 Initial Datapath Components Three components needed by: Instruction Fetch: Instruction Mem[PC] Program Counter Update: PC PC + 4 Instruction address Instruction Inst ruct ion memory PC Instruction Word Add -bit a. Instruction memory b. Program counter c. Adder Sum Two state elements (memory) needed to store and access instructions: Instruction memory: Only read access (by user code). No read control signal needed. 2 Program counter (PC): -bit register. Written at end of every clock cycle (edge-triggered) : No write control signal. 3 -bit Adder: To compute the the next instruction address (PC + 4). 4 th Edition Figure 4.5, page 38-3 rd Edition Figure 5.5, page Basics of logic design/logic building blocks review in Appendix C in Book CD (4 th Edition Appendix B) EECC55 - Shaaban #6 Lec # 4 Winter

17 Instruction Fetch & PC Update: 2 Building The Datapath Instruction Mem[PC] PC PC + 4 Add 4 2 PC PC + 4 PC address Instruction Portion of the datapath used for fetching instructions and incrementing the program counter (PC). Inst ruct ion memory Instruction Mem[PC] PC write or update is edge triggered at the end of the cycle 4 th Edition Figure 4.6 page 39-3 rd Edition Figure 5.6 page 293 Clock input to PC, memory not shown EECC55 - Shaaban #7 Lec # 4 Winter

18 ISA Register File Register numbers Data More Datapath Components register register 2 Write register Write Data Re g ist e r s data data 2 R[rs] R[rt] Main -bit ALU Data 4 ALU operation (Function) Zero ALU ALU result e.g add = RegWrite -bit Arithmetic and Logic Unit (ALU) Register File: a. Registers b. ALU Zero = Zero flag = When ALU result equals zero Contains all ISA registers. Two read ports and one write port. Register writes by asserting write control signal Clocking Methodology: Writes are edge-triggered. Thus can read and write to the same register in the same clock cycle. 4 th Edition Figure 4.7, page 3-3 rd Edition Figure 5.7, page Basics of logic design/logic building blocks review in Appendix C in Book CD (4 th Edition Appendix B) EECC55 - Shaaban #8 Lec # 4 Winter

19 Register File Details Register File consists of registers: Two -bit output busses: busa and busb One -bit input bus: busw Register is selected by: Write Enable Write Data busw Clk RW RA RB bit Registers RA (number) selects the register to put on busa (data): busa = R[RA] RB (number) selects the register to put on busb (data): busb = R[RB] RW (number) selects the register to be written via busw (data) when Write Enable is Write Enable: R[RW] busw Clock input (CLK) The CLK input is a factor ONLY during write operations. During read operation, it behaves as a combinational logic block: RA or RB valid => busa or busb valid after access time. busa busb EECC55 - Shaaban #9 Lec # 4 Winter

20 Write Port Write Register RW 5 rd? rt? A Possible Register File Implementation 5-to- Decoder Register Write Enable (RegWrite) 3 3. Register Write Data (Bus W) Clock input to registers not shown in diagram Write Data In Write Data In Write Data In Write Data In Write Enable busw Clk. Register Register. Register 3 Register 3 RW RA bit Registers Data Out Data Out Data Out Data Out Also see Appendix C in Book CD (3 rd Edition Appendix B) - The Basics of Logic Design Each Register contains edge triggered D-Flip Flops RB busa busb to- MUX 3 3 EECC55 - Shaaban 5 Register (RA) rs -to- MUX 3 3 #2 Lec # 4 Winter Register 2 (RB) rt 2 Ports R[rs] Register Data (Bus A) R[rt] Register Data 2 (Bus B)

21 Idealized Memory Write Enable Address Data In DataOut Memory (idealized) One input bus: Data In. Clk One output bus: Data Out. Memory word is selected by: Enable Address selects the word to put on Data Out bus. Write Enable = : address selects the memory word to be written via the Data In bus. Clock input (CLK): The CLK input is a factor ONLY during write operation, During read operation, this memory behaves as a combinational logic block: Address valid => Data Out valid after access time. Ideal Memory = Short access time. EECC55 - Shaaban Compared to other components in CPU datapath #2 Lec # 4 Winter

22 Clocking Methodology Used: Edge Triggered Writes Clk Setup Hold Don t Care Setup Hold CLK-to-Q CLK-to-Q Clock Critical Path (Longest delay path) All storage element (e.g Flip-Flops, Registers, Data Memory) writes are triggered by the same clock edge. Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew Clock Here writes are triggered on the rising edge of the clock EECC55 - Shaaban #22 Lec # 4 Winter

23 Simplified Datapath For MIPS R-Type Instructions From Instruction Memory [25:2] [2:6] Instruction [5:] rs rt rd register register 2 Registers Write register Write data RegWrite data data 2 R[rs] R[rt] 4 3 ALU ALU operation (Function) Zero ALU result e.g add = Components and connections as specified by RTN statement Clock input to register bank not shown R[rd] Destination register R[rd] write or update is edge triggered at the end of the cycle R[rs] + R[rt] i.e Funct = function =add EECC55 - Shaaban #23 Lec # 4 Winter

24 More Detailed Datapath For R-Type R Instructions With Control Points Identified RegWr busw Clk Rd Rs Rw Ra Rb -bit Registers Rt busa busb R[rs] R[rt] ALUctr 4 ALU Function =Add, Subtract Result R[rd] R[rs] + R[rt] i.e Funct = function =add EECC55 - Shaaban #24 Lec # 4 Winter

25 Clk PC Old Value Rs, Rt, Rd, Op, Func ALUctr RegWr busa, B busw busw Clk RegWr R-Type Register-Register Timing Rd Rs Rt Rw Ra Rb -bit Registers Clk-to-Q New Value Old Value Old Value Old Value Old Value Old Value Instruction Memory Access Time New Value busa busb R[rs] R[rt] Delay through Control Logic New Value ALUct r ALU New Value Register File Access Time New Value ALU Delay New Value Result PC+4 Register Write Occurs Here All register writes occur on falling edge of clock (clocking methodology) EECC55 - Shaaban #25 Lec # 4 Winter

26 Logical Operations with Immediate Example: Micro-Operation Sequence For ORI ori rt, rs, imm op rs rt Immediate (imm6) 6 bits 5 bits 5 bits 6 bits [3:26] [25:2] [2:6] [5:] Instruction Word Mem[PC] Fetch the instruction PC PC + 4 Increment PC Common Steps R[rt] R[rs] OR ZeroExt[imm6] Done by Main ALU.. Not in book version OR register rs with immediate field zero extended to bits, result in register rt Imm6 EECC55 - Shaaban #26 Lec # 4 Winter

27 Datapath For Logical Instructions With Immediate RegDst busw Clk Rd Mux Rs Rt RegWr imm6 Rt Rw Ra Rb -bit Registers 6 2x MUX (width 5 bits) busb ZeroExt busa R[rt] Mux R[rs] ALUSrc ALUctr ALU Result 2x MUX (width bits) Function = OR R[rt] R[rs] OR ZeroExt[imm6].. Imm6 EECC55 - Shaaban #27 Lec # 4 Winter

28 Load Operations Example: Micro-Operation Sequence For LW 35 3 Instruction Word Mem[PC] Fetch the instruction PC PC op rs rt Immediate (imm6) 6 bits 5 bits 5 bits 6 bits R[rt] Mem[R[rs] + SignExt[imm6]] Data Memory lw rt, rs, imm6 [3:26] [25:2] [2:6] [5:] Instruction Memory Effective Address To load from Increment PC Immediate field sign extended to bits and added to register rs to form memory load address, write word at load effective address to register rt Signed Address offset in bytes Common Steps EECC55 - Shaaban #28 Lec # 4 Winter

29 Additional Datapath Components For 4 th Edition Figure 4.8, page 3 3 rd Edition Figure 5.8, page 296 Loads & Stores MemWrite Address Write data data Dat a memory Mem 6 Sig n extend For SignExt[imm6] a. Data memory unit Inputs: for address and write (store) data Output for read (load) data Data memory write or update is edge triggered at the end of the cycle (clocking methodology) b. Sign-extension unit 6-bit input sign-extended into a -bit value at the output EECC55 - Shaaban #29 Lec # 4 Winter

30 Datapath For Loads LW RegDst busw Clk Rd RegWr Mux imm6 Rt Rs Rw Ra Rb -bit Registers 6 busb Extender Base Address register R[rs] busa R[rt] Offset Mux ALUSrc ALUctr ALU Data In Clk Function = add Effective Address MemWr WrEn Adr Data Memory MemtoReg Mux ExtOp MemRd R[rt] Mem[R[rs] + SignExt[imm6]] Data Memory Effective Address EECC55 - Shaaban #3 Lec # 4 Winter

31 Store Operations Example: Micro-Operation Sequence For SW sw rt, rs, imm6 2 6 op rs rt Immediate (imm6) 6 bits 5 bits 5 bits 6 bits [3:26] [25:2] [2:6] [5:] Signed Address offset in bytes Instruction Word Mem[PC] Fetch the instruction PC PC + 4 Increment PC Common Steps Mem[R[rs] + SignExt[imm6]] R[rt] Effective Address Data Memory To store at Immediate field sign extended to bits and added to register rs to form memory store effective address, register rt written to memory at store effective address. EECC55 - Shaaban #3 Lec # 4 Winter

32 Datapath For Stores SW RegDst busw Clk Rd RegWr Mux imm6 Rt 5 5 Rs 5 Rw Ra Rb -bit Registers 6 Rt busb Extender Base Address register R[rs] busa R[rt] Offset Add = Mux ALUctr R[rt] Data In ALU Effective Address Clk MemWr WrEn Adr Data Memory MemtoReg Mux ExtOp ALUSrc MemRd Mem[R[rs] + SignExt[imm6]] R[rt] Data Memory Effective Address EECC55 - Shaaban # Lec # 4 Winter

33 Conditional Branch Example: Micro-Operation Sequence For BEQ 4 3 Instruction Word Mem[PC] Fetch the instruction PC PC beq rs, rt, imm6 2 op rs rt immediate 6 bits 5 bits 5 bits 6 bits [3:26] [25:2] [2:6] [5:] 6 Increment PC PC Offset in words Common Steps Zero R[rs] - R[rt] Condition Action Zero : PC PC + ( SignExt(imm6) x 4 ) Zero is zero flag of main ALU Branch Target Calculate the branch condition R[rs] == R[rt] (i.e R[rs] - R[rt] = ) Calculate the next instruction s PC address Then Zero = EECC55 - Shaaban #33 Lec # 4 Winter

34 Main ALU evaluates branch condition New adder to compute branch target: Sum of incremented PC and sign-extended lower 6-bits on the instruction. [25:2] rs Instruction [2:6] rt register register 2 Write register Write data [5:] imm6 RegWrite PC+4 from instruction datapath ISA Regist ers data data 2 SignExt(imm6) x 4 Sh if t lef t 2 6 Sig n extend SignExt(imm6) Datapath For Branch Instructions R[rs] R[rt] Add Sum 4 ALU operation ALU Zero (Main ALU) Branch target New -bit Adder (Third ALU) for Branch Target PC ( SignExt(imm6) x 4 = Subtract To branch control logic Zero flag = if R[rs] - R[rt] = (i.e R[rs] = R[rt]) Zero R[rs] - R[rt] Main ALU Evaluates Branch Condition (subtract) 4 th Edition Figure 4.9, page 32-3 rd Edition Figure 5.9, page 297 EECC55 - Shaaban #34 Lec # 4 Winter

35 More Detailed Datapath For Branch Operations Branch Zero Instruction Address Zero 4 imm6 PC Ext Adder PC+4 Adder Mux Branch Target PC Clk PC busw Clk RegWr Rs Rw Ra Rb -bit Registers Rt busa busb R[rs] R[rt] Equal? Main ALU (subtract) Zero R[rs] - R[rt] Sign extend shift left 2 Branch Target ALU New Third ALU (adder) New 2X -bit MUX to select next PC value EECC55 - Shaaban #35 Lec # 4 Winter

36 Combining The Datapaths For Memory Instructions and R-Type R Instructions [25:2] rs 4 [2:6] rt R[rs] R[rt] R[rt] rt/rd MUX not shown [5:] imm6 SignExt(imm6) Highlighted muliplexors and connections added to combine the datapaths of memory and R-Type instructions into one datapath This is book version ORI not supported 4 th Edition Figure 4. Page 34-3 rd Edition Figure 5. Page 299 EECC55 - Shaaban #36 Lec # 4 Winter

37 Instruction Fetch Datapath Added to ALU R-Type R and Memory Instructions Datapath PC+ 4 PC Combination of Figure 4. (p. 34) and Figure 4.6 (p. 39) [3 rd Edition Figure 5. (p. 299) and Figure 5.6 (p. 293)] Add 4 PC address rt Instruction Inst ruct ion memory rs rt/rd MUX not shown register register 2 Write register Write data RegWrite data data 2 Re gist e r s 6 Sig n extend R[rs] ALUSrc R[rt] M u x 4 ALU operation Zero ALU ALU result R[rt] Write data MemWrite Address data Dat a memory Mem MemtoReg M u x This is book version ORI not supported, no zero extend of immediate needed EECC55 - Shaaban #37 Lec # 4 Winter

38 A Simple Datapath For The MIPS Architecture Datapath of branches and a program counter multiplexor are added. Resulting datapath can execute in a single cycle the basic MIPS instruction: - load/store word - ALU operations - Branches Zero PC +4 Branch Branch Target rs rt R[rs] 4 R[rt] rt/rd MUX not shown This is book version ORI not supported, no zero extend of immediate needed 4 th Edition Figure 4. page 35-3 rd Edition Figure 5. page 3 EECC55 - Shaaban #38 Lec # 4 Winter

39 Main ALU Control The main ALU has four control lines (detailed design in Appendix B) with the following functions: 4 th Edition ALU Control Lines ALU Function Appendix C AND OR add subtract Set-on-less-than NOR Not Used 3 rd Edition For our current subset of MIPS instructions only the top five functions will be used (thus only three control lines will be used) For R-type instruction the ALU function depends on both the opcode and the 6-bit funct function field For other instructions the ALU function depends on the opcode only. A local ALU control unit can be designed to accept 2-bit ALUop control lines (from main control unit) and the 6-bit function field and generate the correct 4-bit ALU control lines. Or 3 bits depending on number functions actually used EECC55 - Shaaban #39 Lec # 4 Winter

40 Local ALU Decoding of func Field Opcode op 6 Main Control Add = func 6 ALUop 2 Subtract = ALU Control (Local) ALUctr 4 Or 3 bits ALU Instruction Opcode Instruction Operation ALUOp Funct Field Desired ALU Action ALU Control Lines LW SW Branch Equal R-Type R-Type R-Type R-Type R-Type Load word Store word branch equal add subtract AND OR set on less than XXXXXX XXXXXX XXXXXX add add subtract add subtract and or set on less than R-Type = EECC55 - Shaaban #4 Lec # 4 Winter

41 Local ALU Control Unit Add = Subtract = R-type ={ Add Subtract Add Subtract AND OR Set-On-less-Than 2 (2 lines From main control unit) Page 32 Function Field 3 ALU Control Lines 4 th line = More details found in Appendix D in Book CD (3 rd Edition Appendix C) EECC55 - Shaaban #4 Lec # 4 Winter

42 Single Cycle MIPS Datapath Necessary multiplexors and control lines are identified here and local ALU control added: PC 4 address Add register ALUSrc register 2 Zero rt [3:] R[rt] ALU ALU Instruction Instruction memory Instruction [25:2] rs Instruction [2:6] Instruction [5:] rd Instruction [5:] imm6 M ux RegDst PC +4 Write register Write data RegWrite data data 2 Registers 6 Sign extend Function Field Instruction [5:] Shift left 2 R[rs] M u x ALU control ALUOp Add ALU result result PC +4 R[rt] PCSrc M ux Branch Target MemWrite Address Write data Data memory Mem data MemtoReg M u x Zero Branch ALUOp (2-bits) = add = subtract = R-Type This is book version ORI not supported, no zero extend of immediate needed 4 th Edition Figure 4.5 page - 3 rd Edition Figure 5.5 page 35 EECC55 - Shaaban #42 Lec # 4 Winter

43 imm6 Putting It All Together: A Single Cycle Datapath Branch Zero 4 PC Ext PC+4 Adder Adder PCSrc Mux Branch Target Clk Inst Memory PC Adr RegDst RegWr busw Clk Rs imm6 <2:25> Rd Rt 5 5 Rt Rs 5 Rw Ra Rb -bit Registers 6 <6:2> Rd <:5> Rt busa busb Extender <:5> Imm6 R[rt] Zero R[rs] Mux Instruction<3:> Function Field ALUop (2-bits) ALU Control = ALU Main ALU = add = subtract = R-Type MemWr WrEn Adr Data In Data Memory Clk MemtoReg Mux e.g Sign Extend + Shift Left 2 (Includes ORI not in book version) ExtOp ALUSrc MemRd EECC55 - Shaaban #43 Lec # 4 Winter

44 Instruction Memory Adr Instruction<3:> <:5> <:5> <6:2> <2:25> <2:25> <:25> Op Fun Rt Rs Rd Imm6 Jump_target Control Unit Control Lines RegDst ALUSrc MemtoReg RegWrite Mem Mem Write Branch ALOp (2-bits) DATA PATH EECC55 - Shaaban #44 Lec # 4 Winter

45 Signal Name RegDst The Effect of The Control Signals Effect when deasserted (=) The register destination number for the write register comes from the rt field (instruction bits 2:6). Effect when asserted (=) The register destination number for the write register comes from the rd field (instruction bits 5:). RegWrite ALUSrc Branch (BEQ) Mem MemWrite MemtoReg None The second main ALU operand comes from the second register file output ( data 2) R[rt] The PC is replaced by the output of the adder that computes PC + 4 None None The value fed to the register write data input comes from the main ALU. The register on the write register input is written with the value on the Write data input. The second main ALU operand is the sign-extended lower 6 bits on the instruction (imm6) If Zero = The PC is replaced by the output of the adder that computes the branch target. Data memory contents designated by the address input are put on the data output. Data memory contents designated by the address input are replaced by the value on the Write data input. The value fed to the register write data input comes from data memory. EECC55 - Shaaban #45 Lec # 4 Winter

46 Control Line Settings Control Lines Instruction RegDst ALUSrc Memto- Reg Reg Write Mem Mem Write Branch ALUOp ALUOp R-Format lw sw X X beq X X 4 th Edition Figure 4.8 page 3 3 rd Edition Figure 5.8 page 38 ALUOp (2-bits) = add = subtract = R-Type EECC55 - Shaaban #46 Lec # 4 Winter

47 The Truth Table For The Main Control (Opcode) Similar to Figure 4.22 Page 7 (3 rd Edition Figure 5.22 Page 32) EECC55 - Shaaban #47 Lec # 4 Winter

48 PLA Implementation of the Main Control Control Lines To Datapath Figure D.2.5 in Appendix D (3 rd Edition Figure C.2.5 in Appendix C) PLA = Programmable Logic Array - Appendix C (3 rd Edition Appendix B) EECC55 - Shaaban #48 Lec # 4 Winter

49 Single Cycle MIPS Datapath Control Unit Added PC 4 Add Instruction [3 26] 6 Sign extend Shift left 2 Add ALU result Instruction [25 2] register address R[rs] Instruction [2 6] rt data register 2 Zero Instruction R[rt] [3 ] ALU M Write ALU register data 2 result Instruction u Instruction [5 ] M memory x u rd Write x data Registers Instruction [5 ] 4 th Edition Figure 4.2, page 6 3 rd Edition Figure 5.7, page 37 PC +4 Opcode imm6 Control RegDst Branch Mem MemtoReg ALUOp MemWrite ALUSrc RegWrite Function Field Instruction [5 ] In this book version, ORI is not supported no zero extend of immediate needed. rs PC +4 ALU control PC +4 Branch Target Write data ALUOp (2-bits) = add = subtract = R-Type M u x Address data Data memory M u x EECC55 - Shaaban #49 Lec # 4 Winter

50 Adding Support For Jump: Micro-Operation Sequence For Jump: J j jump_target OP Jump_target 2 Instruction Word Mem[PC] Fetch the instruction PC PC bits 26 bits [3:26] [25:] Increment PC Jump address in words PC PC(3-28),jump_target, Update PC with jump address Common Steps Jump Address PC(3-28) jump target 4 bits 26 bits 2 bits 4 highest bits from PC + 4 EECC55 - Shaaban #5 Lec # 4 Winter

51 Datapath For Jump Branch Zero Next Instruction Address 4 Adder PC+4 PCSrc JUMP Instruction(5-) Instruction(25-) jump_target imm6 e.g Sign Extend + Shift Left 2 26 PC Ext Shift left 2 Adder 4 Branch Target 28 Mux PC+4(3-28) Mux Jump Address PC Clk PC PC(3-28),jump_target, Jump Address PC(3-28) jump target 4 bits 26 bits 2 bits EECC55 - Shaaban #5 Lec # 4 Winter

52 Single Cycle MIPS Datapath Extended To Handle Jump with Control Unit Added 4 Add Instruction [25 ] Shift left 2 Jump address [3 ] PC +4 PC + 4 [3 28] 4 PC +4 Add ALU result PC +4 Branch Target M u x M u x Opcode Instruction [3 26] Control RegDst Jump Branch Mem MemtoReg ALUOp MemWrite ALUSrc RegWrite Shift left 2 PC address Instruction [3 ] Instruction memory Instruction [25 2] Instruction [2 6] Instruction [5 ] Instruction [5 ] imm6 4 th Edition Figure 4.24 page 9 3 rd Edition Figure 5.24 page 34 M u x register register 2 Write register Write data data data 2 Registers 6 Sign extend Function Field Instruction [5 ] R[rt] In this book version, ORI is not supported no zero extend of immediate needed. rd rs rt R[rs] M u x ALU control ALU Zero ALU result R[rt] Address Write data ALUOp (2-bits) = add = subtract = R-Type Data memory data M u x EECC55 - Shaaban #52 Lec # 4 Winter

53 Control Line Settings (with jump instruction, j added) Instruction RegDst ALUSrc Memto- Reg Reg Write Mem Mem Write Branch ALUOp ALUOp Jump R-Format lw sw X X beq X X j X X X X X X Figure 4.8 page 3 (3 rd Edition Figure 5.8 page 38) modified to include j EECC55 - Shaaban #53 Lec # 4 Winter

54 Clk PC Old Value Rs, Rt, Rd, Op, Func ALUctr Worst Case Timing (Load) Clk-to-Q New Value Old Value Old Value Instruction Memoey Access Time New Value Delay through Control Logic New Value ExtOp Old Value New Value ALUSrc Old Value New Value MemtoReg Old Value New Value RegWr Old Value New Value busa busb Old Value Delay through Extender & Mux Old Value Register Write Occurs Register File Access Time New Value New Value ALU Delay Address Old Value New Value Data Memory Access Time busw Old Value New EECC55 - Shaaban #54 Lec # 4 Winter

55 Instruction Timing Comparison Arithmetic & Logical PC Inst Memory Reg File mux ALU mux setup Load PC Inst Memory Reg File mux ALU Data Mem muxsetup Critical Path Store PC Inst Memory Reg File mux ALU Data Mem Branch PC Inst Memory Reg File cmp mux Jump PC Inst Memory mux EECC55 - Shaaban #55 Lec # 4 Winter

56 Simplified Single Cycle Datapath Timing Assuming the following datapath/control hardware components delays: Memory Units: 2 ns ALU and adders: 2 ns Register File: ns Control Unit < ns Ignoring Mux and clk-to-q delays, critical path analysis: ns Control Unit } Obtained from low-level target VLSI implementation technology of components 2 ns 2 ns 2 ns Instruction Memory Register Main ALU Data Memory ns Register Write PC + 4 ALU Critical Path Branch Target ALU (Load) Critical Path = 8 ns (LW) 2 ns Time 2ns 3ns 4ns 5ns 7ns 8ns ns = nanosecond = -9 second EECC55 - Shaaban #56 Lec # 4 Winter

57 Performance of Single-Cycle (CPI=) CPU Assuming the following datapath hardware components delays: Memory Units: 2 ns ALU and adders: 2 ns Register File: ns The delays needed for each instruction type can be found : Nanosecond, ns = -9 second Instruction Instruction Register ALU Class Memory Operation Data Register Total Memory Write Delay ALU 2 ns ns 2 ns ns 6 ns Load 2 ns ns 2 ns 2 ns ns 8 ns Store 2 ns ns 2 ns 2 ns 7 ns Branch 2 ns ns 2 ns 5 ns Jump 2 ns 2 ns Load has longest delay of 8 ns thus determining the clock cycle of the CPU to be 8ns C = 8 ns The clock cycle is determined by the instruction with longest delay: The load in this case which is 8 ns. Clock rate = / 8 ns = 25 MHz A program with I =,, instructions executed takes: Execution Time = T = I x CPI x C = 6 x x 8x -9 =.8 s = 8 msec T = I x CPI x C EECC55 - Shaaban #57 Lec # 4 Winter

58 Adding Support for jal to Single Cycle Datapath The MIPS jump and link instruction, jal is used to support procedure calls by jumping to jump address (similar to j ) and saving the address of the following instruction PC+4 in register $ra ($3) i.e. Return Address jal Address R[3] PC + 4 jal uses the j instruction format: PC Jump Address op (6 bits) Target address (26 bits) We wish to add jal to the single cycle datapath in Figure 4.24 page 9 (3 rd Edition Figure 5.24 page 34). Add any necessary datapaths and control signals to the single-clock datapath and justify the need for the modifications, if any. Specify control line values for this instruction. EECC55 - Shaaban #58 Lec # 4 Winter

59 jump and link, jal support to Single Cycle Datapath Instruction Word R[3] PC + 4 PC Jump Address Mem[PC] Jump Address PC + 4 PC + 4 Branch Target PC rd rs rt R[rt] R[rs] 2 imm6. Expand the multiplexor controlled by RegDst to include the value 3 as a new input Expand the multiplexor controlled by MemtoReg to have PC+4 as new input 2. EECC55 - Shaaban #59 Lec # 4 Winter

60 jump and link, jal support to Single Cycle Datapath Adding Control Lines Settings for jal (For Textbook Single Cycle Datapath including Jump) RegDst Is now 2 bits MemtoReg Is now 2 bits Memto- Reg Mem Mem RegDst ALUSrc Reg Write Write Branch ALUOp ALUOp Jump R-format lw sw xx xx beq xx xx J xx x xx x x x JAL x x x x R[3] PC+ 4 Instruction Word R[3] PC + 4 PC Jump Address Mem[PC] PC Jump Address EECC55 - Shaaban #6 Lec # 4 Winter

61 Load Word Register Adding Support for LWR to Single Cycle Datapath We wish to add a variant of lw (load word) let s call it LWR to the single cycle datapath in Figure 4.24 page 9 (3 rd Edition Figure 5.24 page 34). LWR $rd, $rs, $rt The LWR instruction is similar to lw but it sums two registers (specified by $rs, $rt) to obtain the effective load address and uses the R-Type format Loaded word from memory written to register rd Add any necessary datapaths and control signals to the single cycle datapath and justify the need for the modifications, if any. Specify control line values for this instruction. EECC55 - Shaaban #6 Lec # 4 Winter

62 LWR (R-format LW) support to Single Cycle Datapath Instruction Word Mem[PC] PC PC + 4 R[rd] Mem[ R[rs] + R[rt] ] No new components or connections are needed for the datapath just the proper control line settings Adding Control Lines Settings for LWR (For Textbook Single Cycle Datapath including Jump) Memto- Reg Mem Mem RegDst ALUSrc Reg Write Write Branch ALUOp ALUOp Jump R-format lw sw x x beq x x J x x x x x x LWR rd R[rt] Add EECC55 - Shaaban #62 Lec # 4 Winter

63 Jump Memory Adding Support for jm to Single Cycle Datapath We wish to add a new instruction jm (jump memory) to the single cycle datapath in Figure 4.24 page 9 (3 rd Edition Figure 5.24 page 34). jm offset($rs) The jm instruction loads a word from effective address (R[rs] + offset), this is similar to lw except the loaded word is put in the PC instead of register $rt. Jm used the I-format with field rt not used. OP rs rt address (imm6) 6 bits 5 bits 5 bits 6 bits Not Used Add any necessary datapaths and control signals to the single cycle datapath and justify the need for the modifications, if any. Specify control line values for this instruction. EECC55 - Shaaban #63 Lec # 4 Winter

64 Adding jump memory, jm support to Single Cycle Datapath Instruction Word Mem[PC] PC Mem[R[rs] + SignExt[imm6]]. Expand the multiplexor controlled by Jump to include the Data (data memory output) as new input 2. The Jump control signal is now 2 bits Jump 2 2 Jump PC + 4 Branch Target 2 rs rt R[rt] R[rs] rd imm6 EECC55 - Shaaban #64 Lec # 4 Winter

65 Adding jm support to Single Cycle Datapath Adding Control Lines Settings for jm (For Textbook Single Cycle Datapath including Jump) Jump is now 2 bits Memto- Reg Mem Mem RegDst ALUSrc Reg Write Write Branch ALUOp ALUOp Jump R-format lw sw x x beq x x J x x x x x x Jm x x x add PC Mem[R[rs] + SignExt[imm6]] EECC55 - Shaaban #65 Lec # 4 Winter

66 Drawbacks of Single Cycle Processor. Long cycle time: All instructions must take as much time as the slowest Here, cycle time for load is longer than needed for all other instructions. Cycle time must be long enough for the load instruction: PC s Clock -to-q + Instruction Memory Access Time + Register File Access Time + ALU Delay (address calculation) + Data Memory Access Time + Register File Setup Time + Clock Skew Real memory is not as well-behaved as idealized memory Cannot always complete data access in one (short) cycle. 2. Impossible to implement complex, variable-length instructions and complex addressing modes in a single cycle. e.g indirect memory addressing. e.g R[$] Mem[ Mem[$2] ] 3. High and duplicate hardware resource requirements Any hardware functional unit cannot be used more than once in a single cycle (e.g. ALUs). 4. Does not allow overlap of instruction processing (instruction pipelining, chapter 6). EECC55 - Shaaban #66 Lec # 4 Winter