Hardware Design Guidelines for Freescale s High-Performance Digital Signal Processors

Transcription

1 June 2010 Hardware Design Guidelines for Freescale s High-Performance Digital Signal Processors Colin McEwan Systems and Applications Engineer

2 Agenda Introduction and Review Agenda The Freescale AMC ECO-System Estimating DSP Farm Density and Risk DDR3 Design SerDes Design Power Design Session Review and Wrap Up

3 Session Introduction Relevant for customer designing with Frescale s MSC814x, MSC815x & MSC825x family of Digital Signal Processors. Details Freescale s high speed DSP farm designs and the collateral available Examines the problems and solutions of DSP farm design Main Benefit Provides practical examples based on existing Freescale designs My role at Freescale Systems and Applications Engineer, 10 years of DSP/PowerQuicc and QoreIQ platform design experience

4 Session Objectives Learn to: Identify the design collateral that exists to assist with MSC814x and MSC815x and MSC825x DSP designs Recognize the major design issues in high speed DSP farm design and how they can be overcome Use our design tips for high speed interface design (DDR3 and SerDes) Know where to go for assistance

5 AMC Eco-System Integrated Platforms MPC MSC8126 P MSC8156 PowerQUICC/ QoreIQ MPC8548 MPC8641D MPC8572 P2020 DSP MS MSC8144 MSC8144 MSC8156 Technology SDRAM, DDR, 10/100 Base T DDR2, SRIO,1G Ethernet multicore DDR3, SRIO, PCIe, multicore 5

6 AMC Eco-System MSC815x/MSC825x RJ45 Features: 3x MSC8156 with 6x SC3850 StarCore cores at 1GHz Dual 64-bit wide 512MByte DDR3 memory Connectivity: 3.125GHz SRIO (x4) Dual Gigabit Ethernet Applications Areas: MSC815x 3G LTE WIMAX WCDMA MSC825x Medical Imaging Aerospace Defense Test and Measurement RJ45 Mezzanine DDR III DDR III Mezzanine DDR III DDR III Mezzanine DDR III DDR III DDR DDR DDR DDR DDR DDR MSC8156 MSC8156 MSC8156 GigE GigE PCIe/sRIO srio I2C GigE GigE srio srio I2C GigE GigE srio srio I2C 4x 4x 4x 4x 4x 4x EEPROM Ethernet RGMII Switch MUX I2C Ethernet PHY SRIO SWITCH 4x MUX 4x 4x 4x Module Management Controller Port 0 Port 1 Port 4:7 Port 8:11 Port 12:15 Port 17:20 IPMB-L 6

7 AMC Eco-System MSC8144 Features: 4x MSC8144 each with 4x SC3400 StarCore cores at 1GHz 256MByte of 32-bit DDR2 memory DDR II DDR II MSC8144 DDR GigE srio MSC8144 DDR GigE srio Ethernet PHY Ethernet Switch Port 0 Port 1 Connectivity: 3.125GHz (x4) SRIO Gigabit Ethernet Applications Areas: Baseband Media Gateways Radio Network Contoller DDR II DDR II bit MSC8144 DDR GigE srio MSC8144 DDR GigE srio x4 x4 x4 x4 SRIO Switch x4 x4 Control MMC Port 4:7 Port 8:11 IPMB-L 7

8 AMC Eco-System Design Collateral Available Design Description User Manuals Getting Started Guides Constraint Guidelines Schematics Bill Of Materials Netlist Gerbers and PCB Graphics Files (.brd) Firmware Examples DDR Timing Information Design/Layout Reviews 8

9 High Density DSP Farm Design Project Risk Typically design project timescales are estimated based on: Schematic Design If the requirements are well-defined, this stage can be accurately estimated Layout High Board density will impact layout timescales Placing final few components in a DSP farm can be time consuming Routing High Board density will impact routing time hard to judge and typically where delays occur Auto-router may not complete resulting in numerous attempts and/or excessive manual routing Re-routing can cause significant delay Not uncommon for 50% of time spent routing last 10% of board! Fabricate Fixed timescale based on PCB cost (number of layers, technology used) Assembly Fixed timescales base on lead time the more you pay, the quicker (i.e. 3, 5,10 day) turn around 9

10 High Density Farm Design Estimating Density Based on experience Freescale has created some approximations that allow early calculation of (AMC-like) board density (pins/cm2) DDR II bit bit MSC8144 DDR GigE srio MSC Ethernet PHY Ethernet Switch Port 0 Port 1 Estimated pins = BGA pins and IC legs in Block Diagram x 1.9 DDR II DDR GigE srio Counted pins = 5322 Estimated pins = Estimated Board density = estimated pins/118cm2 = 86 cm2 Actual Board density was 77 cm2 DDR II DDR II bit bit MSC8144 DDR GigE srio MSC8144 DDR GigE srio x4 x4 x4 x4 Control CPLD SRIO Switch PSU 675 x4 x4 Control MMC Port 4:7 Port 8:11 IPMB-L 170 Risk Board density (pins/cm2) Comments Very high >95 May not be possible to route Pins/cm2 High Difficult to route, risk of delay Medium Care required Low <50 Lots of space (easy!) 10

11 DDR3 Design Introduction Customers begin to inquire and expect DDR3 support on their new product offerings, especially as the price cross-over point is expected this year (2010). Freescale s MSC815x and MSC825x product family support DDR3 High density DSP farm design is easier with DDR3 Utilize Fly-By Technologies Lower Power Higher Density Farm designs typically use on-board DDR (without ECC) Controller designs use on-board or DIMM DDR (with/without ECC) 11

12 DDR3 Design DDR Highlights and Comparison Feature/Category DDR1 DDR2 DDR3 Data Rate Mbps Mbps Mbps Densities 128 Mb 1 Gb 256 Mb 4 Gb 512 Mb 8 Gb I/O Signaling SSTL_2 SSTL_18 SSTL_15 Termination Motherboard termination to V TT for all signals On-die termination (ODT) for data group. V TT termination for address, command and control On-die termination (ODT) for data group. V TT termination for address, command and control Data Strobes (DQS) Single Ended Differential or single Differential Fly-By Technology No No Yes 12

13 DDR3 Design Fly-By Routing Address, control and clocks use Fly-By architecture v. branch architecture for routing Daisy chain topology for these signals Provides improved signal quality Reduces number of stubs and their length Enables higher speeds Requires write leveling to optimize timing Fly-By creates too much skew between clock and strobe DDR2 DDR3 Command/Address Controller Command/Address VTT Data & Strobe Controller 13

14 DDR3 Design Constraint Setting Not all developers will simulate DDR risky! As a guideline follow Jedec DDR3 unbuffered DIMM standard: PC3-6400/PC3-8500/PC /PC DDR3 SDRAM Unbuffered DIMM Design Specification on DIMM as a guideline to reduce risk Order Signals Group Matching Rules CK, CTRL & ADD/CMD 1 Clock Match CK0+ & CK0- to each SDRAM to within 0.1mm (max length from 1 st to last SDRAM= 153mm) 2 CTRL group Match length of ODT0, CKE0 signals to each SDRAM to within 1mm 3 CTRL to CLK Match length of CTRL signals to each SDRAM to within +/- 0.5mm of clock 4 ADD/CMD group Match the length of A[0:12], BA[0:2], CS, RAS, CAS, WE to each SDRAM within 1mm 5 ADD/CMD to CLK Match length of ADD/CMD signals to each SDRAM to within +/- 0.5mm of clock Data & Strobe 6 Data Byte 0 Match DQS0+ & DQS0- to SDRAM to within 0.1mm Match DQ[0:7], DM0 to within +/- 0.2mm of DQS0 7 Data Byte 1 Match DQS1+ & DQS1- to SDRAM to within 0.1mm Match DQ[8:15], DM1 to within +/- 0.2mm of DQS1 8 Data Byte to data Byte Match data bytes within 12mm (arbitrary) 14

15 Route all DDR data signals next to a solid reference DDR3 Design Layout/Routing Guidelines Route data bytes on the same plane and avoid switching layers Route all DDR address/command signals next to a solid reference (ground or power) Control the single ended impedance to between 50 and 60 Ώ Control the differential signals to 100 Ώ Keep the number of vias to a minimum and the same across groups Account for via delay (1 via = 2.5mm) Do not route signals at edge of board Check for parallelism (< 25mm) Check for segment over voids 15

16 DDR3 Design Layout/Routing VTT (0.75v) Layers 1 Top 2 PWR_2V5 3 SIG1 4 GND 5 SIG2 6 SIG3 7 PWR_1V5 8 PWR_0V75/GND 9 SIG4 10 SIG5 11 GND 12 SIG6 13 PWR_1V0 14 BOTTOM CLK Control Address Command U1 U2 DATA U3 MSC8156 U4 16

17 DDR3 Design Capacitance Capacitance Frequently overlooked in importance and frequently is the cause of customer problems Design tips Use solid planes Locate 1.5V decoupling at components (constrain!) Use the full range of capacitors on VTT plane 0.01uF, 0.1uF,1uf 10uF & 100uF Isolate VTT termination capacitors from VREF biasing capacitors (VTT noisy) Generate 0.75v VREF using 1.5V low impedance divider 0.75V (VTT) 1.5V U2 U1 VREF o.1uf 100 VREF 0.01uF, 0.1uF,1uf 10uF & 100uF U4 U3 MSC

18 SerDes Design Introduction Serialisation/Deserialisation (SerDes) interfaces like SRIO and PCI Express to offer high performance, point to point system level interconnect RapidiO A peer-to-peer interconnect specifically designed for the embedded market Suitable for non-hierarchical multiple CPU designs PCI Express A replacement for PCI More relevant for hierarchical designs Freescale s MSC814x, MSC815x and MSC825x support configurable high speed SerDes interfaces giving the system architect multiple design options For example the MSC8156 supports dual 4-port High Speed Serial Interface (HSSI) blocks. Each block supports various combination of: RapidIO (4x, 1x, 3.125GHz, 2.5GHz, 1.25GHz) PCI Express (1x, 4x, 2.5GHz, 1.25GHz) SGMII Select you option during the reset configuration phase DSP farm designs tend to use RapidIO Interconnect 18

19 SerDes Design Highlights and Comparison Feature/Category Serial RapidIO PCI Express Technology Peer to Peer Interconnect Hierarchical based Interconnect Differential x1, x4 Differential x1, x4 Data Rate (Gen1) 1.25, 2.5, GBaud 1.25, 2.5 GBaud Data Rate (Gen2) 5, GBaud 5 GBaud Signaling XAUI AC coupled 0.01uF series termination at RX end Proprietary AC coupled 0.1uF series termination at TX end Channel ~80 to 100cm with 2 connectors ~40 to 50 cm with 2 connectors Latency Lower Higher Bandwidth Higher Lower 19

20 SerDes RapidIO Basics Follow the application note AN3656 MSC8156 & MSC8256 DSP Family High Speed Serial Interface Hardware Design Considerations Check the available Serdes Options RapidIO uses 125MHz (3.125, 2.5, 1.25GBaud) PCI Express uses 100MHz Clock (2.5, 1.25GBaud) For 1x Mode use RapidIO lane 0 If booting over RapidIO, use HSSI #0 (not 1) HSSI uses dedicated power supplies Use a separate filtered supply Ensure there is proper AC termination Perform signal integrity analysis Check eye diagram at RX and TX end SRIO SWITCH CPS10Q 20

21 SerDes Design RapidIO Constraint Setting Always simulate check the eye diagram Check appropriate data sheets and design guidelines Include stubs in constraints Order Signals Group Matching Rules Clock 1 Reference Clock Match differential pairs to within 0.1mm Data 2 Differential Data Pair (x1) Match differential pairs to within 0.1mm 3 Data Group (x4) Match group of differential pairs to within 25 mm 4 Data pair spacing Keep 0.5mm between data pair i.e TX0+/- and TX1+/- Clock to Data No constraint TX Data to RX Data No constraint 21

22 Use 100 ohm differential pairs Ensure capacitive decoupling is at the correct end SRIO at RX PCIe at TX Always route over solid plane (No exceptions) Check for Segment over Void (Tools can automate this) Avoid switching planes SerDes Design Constraint Setting Do not route at board edge Check for Parallelism (Tools can automate this) Set to less than 25mm Keep away from power especially switching components (FETS, etc.) Match symmetry of routing Use side-by-side break out (ideal world) Use Serpentine at end Better to break differential matching to keep length matched 22

23 Power Design Introduction High density farms will push the limits of power and thermal design AMC Standard (PICMG AMC.0 R2.0) states The average power consumed by an AMC Module during a 25 ms duration shall not exceed 80 W. This shall apply to all size versions of single and double AMC modules. The value includes all power drawn from the PWR and the Management Power. On an AMC the power area can be 1/4 of the available board space Dense high power designs and high speed signals do not mix well! Power modules v. discrete design Power Modules More expensive Less fine tuning Easy to design in Discrete Design Cheaper Meet the exact specification Higher design risk AMC Thermal Design must be considered Thermal simulation can impact component placement The AMC component envelope limits the heat sink size A custom heat sink will add significant cost to BOM 23

24 Power Design Guide Lines Actual MSC814x/MSC815x/MSC825x power requirements will depend on design/system implementation IO blocks used Algorithmic implementations Power guidelines are given in DSP family design checklist DSP farm power consumption will average down, i.e.: 1x MSC8156 design at 90C rated at 16A 10x MSC8156 design at 90C rated at 130A For exact figures, use the Freescale MSC815x/MSC825x Power Calculator (NDA required) Enable/Disable IO Set Bus Width (64/32-bit DDR, x2,x4 SRIO, etc.) Set device/block frequencies Specify percentage utilization Connect up unused pins as per data sheet recommendations to reduce power 24

25 Power Design Decoupling Good decoupling techniques will maintain power levels and minimize system noise Data sheet decoupling techniques are usually aimed at single devices Can lead to an excessive number of capacitors in a DSP farm Difficult to place decoupling Decoupling not effective Decoupling characteristics are shared across DSPs in a dense farm Power Integrity tools can analyze the decoupling versus the power requirements More effective placement Reduce capacitor BOM Ease layout There are different Power Integrity Analysis Single node simulation (impedance v. frequency) Multi-node simulation (capacitor placement) 25

26 Power Design Single Node Simulation Add Capacitance Capacitance can be reduced Capacitors have less impact at higher frequency 26

27 Power Design Single Node Simulation Add Capacitance Capacitance can be reduced Capacitors less effective at higher frequency 27

28 Power Design Mutli-Node Simulation Multi-Node Simulation Covers multiple planes Capacitor placement Capacitors have an effective radius Single capacitor can decouple multiple devices Consider this during placement Effective Radius Notes: 1. Single Core power plane per 2 DSPs 2. Modular layout on front and back: DSP, DDR and discrete components 3. Capacitors on pins 28

29 Power Design Thermals Carry out board simulation Carry out system simulation Multiple Cards Chassis Air Flow Limited heat sink area Use low profile parts (capacitors) Thermal slips Vary the material Avoid blocking components Keep air passages clear Air Flow 29

30 Session Summary The Freescale AMC ECO-System Estimating DSP Farm Density and Risk DDR3 Design SerDes Design Power Design

31 Freescale Product Longevity Program The embedded market needs long-term product support Freescale has a longstanding track record of providing longterm production support for our products Freescale offers a formal product longevity program for the market segments we serve For the automotive and medical segments, Freescale will make a broad range of program devices available for a minimum of 15 years For all other market segments in which Freescale participates, Freescale will make a broad range of devices available for a minimum of 10 years Life cycles begin at the time of launch A list of participating Freescale products is available at:

32 Session Closing By now, you should be able to: Use Freescale s design collateral to aid your own MSC814x, MSC815x and MSC8125x designs Use the DDR3 and Serdes design guidelines to aid your designs Understand the advantage in Power Integrity simulation in DSP farm designs Understand the unique challenges facing DSP farm design and the solutions to overcome them 32

33 For Further Information MSC825x & MSC815x Design Guidelines ab=documentation_tab MSC8156AMC SA&fsrch=1 P2020-MSC8156AMC MSC8144AMC-S deid= e5f0b35 Jedec DDR Specifications AMC Specifications Contact

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