Ultrasonic Signal Processing Platform for Nondestructive Evaluation

Transcription

1 Ultrasonic Signal Processing Platform for Nondestructive Evaluation (usspnde) Functional Requirements List and Performance Specifications Raymond Smith Advisors: Drs. Yufeng Lu and In Soo Ahn December 9, 2013

2 Project Summary: This project aims to develop an ultrasonic signal processing platform for nondestructive evaluation applications. Specifically a high speed data acquisition system will be implemented. In the system, a Field Programmable Gate Array (FPGA) board is used to interface with an analog to digital converter (ADC) and a digital to analog converter (DAC). In addition, a touch screen LCD board is used for data display. C language and VHDL are chosen for embedded system implementation on FPGA. Reusable and efficient hardware modules are designed for future design extension.

3 Introduction Ultrasonic nondestructive evaluation (NDE) has been widely used in quality assessment and failure analysis for critical structures or components in manufacturing, bridge structure, microelectronic packaging, and composite materials for aircraft structure. Different signal processing algorithms such as chirplet signal decomposition [1], Hilbert Huang transform [2], empirical mode decomposition [3], active noise cancellation [4], and Fractional Fourier transform [5] have been done for ultrasonic NDE application. Besides developing better signal processing algorithms, there is another important aspect of the challenges in ultrasonic industrial applications. That is, how to implement these algorithms efficiently on an embedded system. The major challenges of ultrasonic system implementation are: High speed data acquisition and signal processing It is beneficial and practical to have real time operation and detection with instantaneous results for ultrasonic NDE. The hardware and software components should be able to handle complex computations. Flexibility The system can be modified from time to time to take the advantages of evolving research results such as new processing algorithms. A configurable hardware makes it future proof. A conventional hardware design based on microcontrollers and digital signal processor falls short of meeting the demands of high speed, and adaptability requirements. This necessitates reconfigurable computing devices such as Field Programmable Gate Arrays (FPGA) to implement hardware and software co design for the ultrasonic system. This project aims to develop hardware and software for an ultrasonic signal processing system. The system can acquire ultrasonic data at 100M samples per second. An FPGA board is used to interface with an analog to digital converter (ADC) and a digital to analog converter (DAC). A touch screen LCD board is used to display ultrasonic signals. C language and VHDL are used for hardware/software co design on the FPGA. An EPOCH4 ultrasonic flaw detector is used as a reference to verify the system to be developed. The senior project design with reusable modules will be used as a general research and educational platform for ultrasonic signal processing at Bradley University. Block Diagram

4 The high level block diagram is shown in Figure 1. Figure 1. High Level Block Diagram of USSPNDE

5 Functional Description FPGA Board (Genesys Virtex 5 XC5VLX50T) It mainly communicates with the peripherals such as the DAC board (MAX5874 EVKIT), the ADC board (MAX1213N EVKIT), and the touchscreen display (Amulet STK C). A standalone ultrasonic flaw detector, EPOCH 4, is used to provide an analog signal. Embedded system running on FPGA A 32 bit RISC microprocessor, Microblaze is used in the embedded system. It runs at 100MHz frequency. C APIs are used to communicate with all peripherals at a high level. VHDL is used for low level interface design. A signal processing algorithm can be added to the system. DAC board (MAX5874 EVKIT) The board has the MAX5874 DAC device, which provides a sampling rate up to 200 MSPS. The resolution of DAC device is 14 bit. A oscilloscope is connected to the board for the purpose of displaying data and verification. ADC board (MAX1213N EVKIT) The board has the MAX1213N ADC device. It provides up to 170 MSPS. The resolution is 12 bits. Ultrasonic equipment (EPOCH4 ultrasonic flaw detector) EPOCH4 is a standalone system for ultrasound flaw detection. In this project, it is used as a reference system to verify the project. It also provides an analog signal for the project. LCD touch screen (Amulet STK C) It is a 4.3 capacitive touch screen with the resolution of 480x272. A RS232 port is used to send inputs and outputs in the format of ASCII codes. It is used to display signals before and after the embedded system processes the data.

6 System requirement and specifications Hardware FPGA Board (Genesys Virtex 5 XC5VLX50T) The main board in the system to be developed Interface with DAC and ADC peripherals through Very High Density Connection(VHDC) Interface with the touchscreen LCD board through UART Running under 100 MHz on board system clock Others: 256 Mbyte DDR2 memory, 32 Mbyte flash memory and multiple USB2 ports.[8] DAC board (MAX5874 EVKIT) MAX5874: A 14 bit, high dynamic performance DAC from Maxim Integrated, Inc. [6] Support update rates of 200 M samples per second. Operate under 3.3V and 1.8V supplies provided by the FPGA board and a MAX1536 voltage converter. Controlled by the 100 MHz clock signal from the FPGA board. Output a single ended analog signal between 0 and 2Vpp ADC board (MAX1213N EVKIT) MAX1213N: 12 bit low power ADC from Maxim Integrated, Inc.[7] Support a sampling rate up to 170 M samples per second. Operate under 3.3V and 1.8V supplies provided by the FPGA board and a MAX1536 voltage converter. Controlled by the 100 MHz clock signal from the FPGA board. Accept a single ended analog input signal between 0 and 2Vpp (EPOCH 4 ultrasonic flaw detector provides the analog signal source) Outputs 12 differential LVDS2.5 signals LCD touch screen (Amulet STK C) A LCD touch screen board used in past senior projects.[9] Serial port communication protocol with BAUD rate Used as a peripheral of the embedded system running on the FPGA board. Other specifications: 480 X 272 resolution, refresh rate at 100 Hz. Ultrasounic flaw detector(epoch4) A standalone ultrasonic flaw detector Provide an analog reference to the senior project design The specifications of the analog output are to be investigated.

7 Software Embedded system running on FPGA Use a 32 bit RISC Microblaze processor running at 100MHz. Development environment: Xilinx embedded development kit(edk)/ software development kit(sdk) Save incoming data from ADC to the external DDR memory Accept the inputs from the GUI running on the touchscreen board. Languages to be used: C languages and VHDL VHDL for the logic level hardware implementation of ADC and DAC controllers C language for the drivers of ADC and DAC controllers, the interface of general purpose I/Os and UART, and signal processing algorithms running on the FPGA ADC controller Implement the ADC controller in VHDL Provide C APIs for the ADC driver Accept 12 differential LVDS2.5 inputs from the ADC board Form a single ended data vector for the signal processing algorithm. Include handshaking signals to control the data acquisition Operate at 100 MSPS DAC controller Implement the DAC controller in VHDL Provide C APIs for the DAC driver Output a 14 bit data vector to the DAC board Operate at 100 MSPS Touchscreen controller Implement the controller in C language Output ASCII data to the touchscreen board over RS232 [ starting address in hex] [Upper nibble 1] [Lower nibble 1] [Upper nibble 2] [Lower nibble 2] [Upper nibble N] [Lower nibble N] 0x00 Nibbles are in ASCII so to send hex value 0x80 send 0x38 as the upper nibble and 0x30 as the lower nibble Accept inputs from the touchscreen (ASCII format) Provide APIs for the embedded system running on the FPGA

8 Schedule Weeks of Jan. 13 Feb. 3 Testing of ADC/DAC daughter boards Study system integration and customized IP cores Weeks of Feb. 10 Mar. 3 Integration of LCD and ADC/DAC controllers Weeks of Mar. 10 Mar. 31 Debug, test, and simulate Weeks of Apr. 7 Apr. 28 Prepare report and final presentation

9 Equipment list Part # Quantity Needs to be Purchased Virtex 5 LX110T FPGA 1 no MAX5874 DAC 1 no MAX1213N ADC 1 no MAX1536 Voltage Adapter 1 no EPOCH4 Ultrasonic Flaw Detector 1 no SMA coaxial cable 2 yes Wires with female headers 70 yes (need 50 more) SMA adapter for Epoch 4 1 yes links to parts that need to be purchased: female to female wire connectors BNC to SMA(for EPOCH4) SMA 870 SMA BNC Adapter/dp/B T4 SMA cable male sma male 300 series cable assembly pe300 p.aspx

10 References [1] Y. Lu, R.Demirili, G.Cardoso, and J.Saniie, A successive parameter estimation algorithm for chirplet signal decomposition, IEEE Transaction on Ultrasonics, Ferroelectrics, andfrequency Control, vol. 53, no.11, pp , November [2] Y. Lu, E Oruklu, and J. Saniie, Analysis of Hilbert huang transform for ultrasonic nondestructive evaluation, IEEE International Ultrasonics Symposium 2008, November , Beijing, China. [3] E. Oruklu, Y. Lu, and J. Saniie, Hilbert transform pitfalls and solutions for ultrasonic NDE,IEEE International Ultrasonics Symposium 2009, September , Rome, Italy. [4] D. Monroe, I. S. Ahn, and Y. Lu, Adaptive filtering and target detection for ultrasonic backscattered signal, IEEE International Conference on Electro/Information Technology,May 20 22, 2010, Normal, Illinois. [5] Y. Lu, E. Oruklu, and J. Saniie, Analysis of fractional Fourier transform for ultrasonic nondestructive applications, IEEE International Ultrasonics Symposium 2011, October , Orlando, Florida. [6] MAXIM integrated, MAX5873/MAX5874/MAX5875 Evaluation Kits MAX5874 datasheet, [Revised June 2006]. [7] MAXIM integrated, MAX1213N/MAX1214N Evaluation Kits MAX1213N datasheet, [Revised July 2006]. [8] XILINX ML505/ML506/ML507 Evaluation Platform: User Guide XC5VLX110T datasheet, Nov [Revised May 2011]. [9] Amulet Technologies, User guide, STK480272C datasheet, 2013.