R bit Microcontroller Megafunction

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R0515 bit Microcontroller Megafunction General Description The R0515 is a fast, singlechip, bit microcontroller that executes all ASM51 uctions.

1 R0515 bit Microcontroller Megafunction General Description The R0515 is a fast, singlechip, bit microcontroller that executes all ASM51 uctions. It has the same uction set as the 0C31, but executes operations an average of times faster. The R0515 provides software and hardware interrupts, extra timer features, power management, and finion peripherals support. nchip debugging is an option. The microcodefree, strictly synchronous design was developed for reuse in ASICs and FPGAs. Features Single clock per machine Reduced uction time up to 12 times bit Control Unit bit ArithmeticLogic Unit Multiplication/Division Unit o 16 x 16bit multiplication and division; 32 / 16bit division Four bit put/put ports Alternate port functions such as external interrupts & serial interface are separated, providing extra port pins when compared with the standard 051 Three 16bit Timer/Counters Compare/Capture Unit Two Serial Peripheral terfaces in full duplex mode Four priority/thirteen sources terrupt Controller 15bit Programmable Watchdog Timer ternal Data Memory interface can address up to 256 bytes of Read/Write Data Memory Space External Memory interface o Can address up to 64 K bytes of External Program Memory Space o Can address up to 64K bytes of External Data Memory Space o Demultiplexed address/data bus to allow easy connection to memories o Variable length MVX to access fast/slow RAM or peripherals o Variable length code fetch and MVC to access fast/slow program memory o Dual data pointer for fast data block transfers Special Function Registers interface: serves up to 74 external registers Power Management Unit ptional JTAG debugging CAST, c. March 2004 Page 1

2 R0515 Megafunction Datasheet Applications Embedded microcontroller systems Data computation and transfer Communication systems Professional audio and video Symbol reset clk clkcpu clkcpuo clkper swd in in in cc0 txd1 R0515 pori poro Pin Description Name Type Polarity/ pori poro Description Port 0 bit bidirectional I/ Port 1 bit bidirectional I/ Port 2 bit bidirectional I/ Port 3 bit bidirectional I/ clk Clock clock counters and all synchronous circuits reset Hardware reset Resets the device when this pin is held high for two clock s while the oscillator is running clkcpu Engine clock circuits that are stopped when the R0515 is in the IDLE or STP mode clkcpuo Engine clock output Is the gated clk clock. clkcpuo stays low when the R0515 enters into IDLE or STP mode. The clkcpuo is dedicated to offcore connection to the clkcpu input clkper Peripheral clock circuits that are stopped when the R0515 is in STP mode Peripheral clock output is the gated clk clock. stays low when the R0515 enters into STP mode. The is dedicated to offcore connection to the clkper input CAST, c. Page 2

3 R0515 Megafunction Datasheet Name Type Polarity/ Description swd Start Watchdog Timer A high on this pin during reset starts the watchdog timer immediately after reset is released into in in Low/ Low/ Fall./ Fall./ External terrupts External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 cco rxd1o 16 Compare/Capture Compare/Capture 0 Compare/Capture 1 Compare/Capture 2 Compare/Capture 3 Serial 0 interface Serial 0 receive data Serial 0 transmit data Serial 0 transmit data or receive clock in mode 0 Serial 1 interface Serial 1 receive data Serial 1 transmit data Timer inputs Timer 0 external input Timer 1 external input Timer 2 external input Timer 2 capture trigger External Memory interface Memory data input Memory data output Memory address Program store write Program store read Data Memory write Data Memory read ternal Data Memory interface Data bus input Data bus output Data file address Data file write Data file output Name Type Polarity/ I 7 Description External Special Function Registers interface SFR data bus input SFR data bus output SFR address SFR write SFR output CAST, c. Page 3

4 R0515 Megafunction Datasheet Block Diagram mempsack memack txd1 fetch fetch MEMRY_CNTRL pc dptr dptr1 SERIAL_0 s0rell s0relh SERIAL_1 s1rell s1relh CNTRL_UNIT reg RAM_SFR_CNTRL sp ALU acc b psw MDU s0con s0buf s1con s1buf internal sfrbus TIMER_0_1 tl0 tl1 tf0, ie0 ISR ie0 ie1 ie2 com0,1,2,3 TIMER_2 tl2 crcl ccl1 ccl2 ccl3 ccu_bus PRTS p0 p1 p2 p3 ip0 ip1 th2 crch cch1 cch2 cch3 tf1, ie1 tf2, exf2 ircon con 4 x CCU_PRT WATCHDG_TIMER wdtrel PMU RSTCTRL th0 th1 tcon tmod in in in cc0 por swd clk clkcpu clkcpuo clkper reset md0 md1 md2 md4 md3 md5 arcon CLCK_CNTRL pcon ckcon CAST, c. Page 4

5 R0515 Megafunction Datasheet Verification Methods The R0515 core s functionality was verified by means of a proprietary hardware modeler. The same stimulus was applied to a hardware model that contained the original tel 0C31 and Siemens SAB0C537 chips, and the results were compared with the core s simulation outputs. Device Utilization & Performance Supported Device Utilization Performance Family Tested LEs Memory Memory bits F max Cyclone EP1C M4K 10,240 3 MHz Stratix EP1S M4K 10, MHz StratixII EP2S M4K 10, MHz Notes: 1. ptimized for speed 2. Implemented with 256 bytes of RAM and 1KB of RM Deliverables VHDL or Verilog HDL source code Postsynthesis EDIF netlist (netlist license) Testbench (selfchecking) Vectors for testing the core Place & route scripts (netlist license) Simulation script Synthesis script Documentation Contact formation CAST, c. 11 Stonewall Court Woodcliff Lake, New Jersey USA Phone: Fax: info@castinc.com URL: This megafunction developed by the processor experts at Evatronix SA Copyright CAST, c. 2004, All Rights Reserved. Contents subject to change without notice CAST, c. Page 5

C8051 Legacy-Speed 8-Bit Processor Core

C8051 Legacy-Speed 8-Bit Processor Core C051 Legacy-Speed -Bit Processor Core General Description The C051 processor core is a single-chip, -bit microcontroller that executes all ASM51 instructions and has the same instruction set and timing