Scintillator Data Acquisition System
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1 Scintillator Data Acquisition System Applications in the CALICE AHCAL and ScECAL > AHCAL DAQ Overview > Hardware > LDA > Software > Plan Aliakbar Ebrahimi - DESY AHCAL Testbeam Preparation Hamburg, July
2 DAQ System Architecture > Main DAQ subsystem: PCs and Software Package Clock and Control Card Link and Data Aggregator > Communicate over Ethernet HDMI USB (debugging purposes) > Master of operation is the Run Control PC Initialization Detector configuration Data taking Aliakbar Ebrahimi AHCAL Testbeam Preparation Page 2
3 ZedBoard > Base for CCC and LDA > Zynq Evaluation & Development Board > Xilinx Zynq-7000 SoC Processor Subsyst. (PS): Dual ARM Cortex-A9 Programmable Logic (PL): Xilinx 7 series FPGA 100Gbps interconnect bandwidth (AXI) ARM programmability+fpga flexibility > On board memory 512 MB DDR MB QUAD-SPI > PS is able to run Linux > FPG Mezzanine Connector (FMC) Allows adding custom boards Aliakbar Ebrahimi AHCAL Testbeam Preparation Page 3 FMC
4 DAQ Hardware > Zed-boards 1 Rev. C used as CCC 1 Rev. D used as mini-lda 1 Rev. D used for testing and development > Mezzanine cards ZedBoard and Mezzanine 2 CCC mezzanine 4 mini-lda mezzanine > Mars Module 2 modules Boot problem is fixed > CCC VME Mini-LDA and Mezzanine > Wing-LDA Currently being tested at the university of Mainz Aliakbar Ebrahimi AHCAL Testbeam Preparation Page 4
5 Link and Data Aggregator (x-lda) LDA concept Tx port 9 Tx All modules completed last week Start Tx_busy TxW TxController 16 empty parityerr EOPbit sloww FastCommW All modules are simulated individually empty full Read... RxController RxPin Rx NewWord RXdata16 16 > LDA Software (PS) Preliminary tests done in Mainz Doxygen documentation provided Ready for the first tests with the LDA (Mainz) and PS_ debugging transmitter WriteW PortConfigurationReg...: PortEnable...: ClkEnable...: BusyPropagationEnable...: SaveAcknoledgments...: SaveErrors...: MergePackets...: WaitForACK...: Resends[1..0] PortStatus...: Rx_idle...: Receiving[2..0]...: Transmitting[2..0] Transmitting Broadcast_req Broadcast_command FastCommW 16 Buffer WREN (FIFO w full base addr EOPbit +index) PortErrorReg PortStatusReg PortConfigReg A temporary AXI connection is foreseen for testing puposes To be synthesized, tested and debugged all together reset Tx_pin Read > Firmware (PL) Write64 WAddr 9+log n WRdata64 64 Tx port 0 CCC_ broadcast FIFO CCC_Rx Rx CCC_Rx_pin NewWord FCWord 16 LDAErrorReg LDAStatusReg LDAConfigReg Tx port 9 Tx port 0 sloww 16 Memory& address manager Other TX ports AXI Processor Linux BRAM n*512x64b ASIC 0 ASIC 1 ASIC 3... NewRxPacket PointerAck "pointer" (addr, length, status) 48? RAddr RDEN RDdata64 64 Rx port 9 Rx port 0 Rx port 9 Rx port 0 Packet Queue handler PortErrors (persistent)...: RxPacketFormatError...: RxPacketIDError...: RxPacketOrder...: RxTimeout0Error...: RxTimeout1Error...: RxLengthOverflow...: RxPointerOverwritten...: RxCRCerror...: RxCRCok...: RxPointerSaved]...: TxLengthMismatch...: TxParityError...: TxCRCError Aliakbar Ebrahimi AHCAL Testbeam Preparation Page 5 512MB ddr3 GbE
6 DAQ Interface (DIF) > So far USB connection was used for slow control and data read out and HDMI was used to distribute level signals > To have HDMI-only connection to DIFs, DIF firmware needs to be modified > DIF firmware is converted to block transfer mode All commands and data readout in final format Tested successfully with USB connection More development on LabView/USB setup to be used for debugging purposes > Communication is being change to HDMI Transmitter and receiver modules are ready To be integrated into the DIF firmware this week Aliakbar Ebrahimi AHCAL Testbeam Preparation Page 6
7 AHCAL DAQ Software Package > Multiple tools All could run on the same or multiple PCs > Run Control Software C++ with QT GUI MDI interface Run profiles for quick configuration > Slow Control MySQL database to store and keep record of the configuration for each run > Data taking and storage Receives data Store in appropriate formats > Online monitoring Aliakbar Ebrahimi AHCAL Testbeam Preparation Page 7
8 Computers, network and storage > We have some devices from the physics prototype 1 HP ethernet switch 5 PCs 1 NAS with (approx.) 4TB space > All of them need to be: Cleaned! Checked for old data Re-installed > Should we use the old NAS? Use the whole device as-is. Replace hard-disks Get a new one Aliakbar Ebrahimi AHCAL Testbeam Preparation Page 8
9 DAQ test and commissioning chain Kintex Run Control AXI ASIC DIF LDA PL Tested CCC Slow Control PS Storage Tested partially Not tested Aliakbar Ebrahimi AHCAL Testbeam Preparation Page 9
10 Plan > We have a new test setup in lab 4 > This week we start some system level tests (2-3 weeks) LDA firmware will be put together and synthesized A test software to used to send blocks to a DIF and get acknowledge back via LDA LDA software (PS) will be implemented > Preparing computer equipment > Wing-LDA test and commissioning If hardware is OK, then the KDA firmware should be adopted to the Kintex FPGAs > Software package development Aliakbar Ebrahimi AHCAL Testbeam Preparation Page 10
11 Backup Aliakbar Ebrahimi AHCAL Testbeam Preparation Page 11
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