2016 ELECTRONIC HIGHLIGHTS

Size: px

Start display at page:

Download "2016 ELECTRONIC HIGHLIGHTS"

Jonathan Stewart
5 years ago
Views:

2016 ELECTRONIC HIGHLIGHTS Electronic group :

1 2016 ELECTRONIC HIGHLIGHTS Electronic group : Multi-project: - 4 electronic engineers: Daniel, Stéphane, Yannick - 2 technical assistants: Gaby, Javier CTA electronic engineer: Isaac TT-PET microelectronic engineer: Pier Paolo B-Mind software engineer (short mission): Olivier

2 Activities Engineering activities: PCB design (Schematics / Layout - Cadence) on analog, digital, HF & EMC architectures Analog/Digital ASIC design (Cadence) FPGA Design (VHDL/Verilog, Xilinx/Altera) Analog & Digital Simulation (PSpice/modelsim ) Embedded µc programming (C/C++, real-time) PC programming (C++, C#, VB, SQL) for readout, test benches & database Mechatronics approach with mechanical group Workshop activities: PCB prototypes manufacturing Boards assembly Cabling Bonding Testing & calibration Production programming Database parts creation & stock December 2016 Electronics Highlights 2/10

HERD: Acquisition board VATA I/F Cyclone V FPGA Main characteristics: USB µc VATA interface 2 Trigger inputs, 1 Trigger + 1 Busy output 12-bits 1-ch ADC ALTERA

correctly PC software done by physicists based on Unige C# library Board successfully used during test beam in August Following 2017 : 2 nd version: Improvement

3 HERD: Acquisition board VATA I/F Cyclone V FPGA Main characteristics: USB µc VATA interface 2 Trigger inputs, 1 Trigger + 1 Busy output 12-bits 1-ch ADC ALTERA Cyclone V FPGA Unige USB3 firmware + software interface for readout & slow control Highlights 2016 FPGA Firmware done Hardware corrections VATAs & USB3 I/F works correctly PC software done by physicists based on Unige C# library Board successfully used during test beam in August Following 2017 : 2 nd version: Improvement of the VATA interface faster 12-bits ADC implemented Improvement of the USB interface 2 ASIC interfaces : VATA + new SIPHRA December 2016 Electronics Highlights 3/10

Amplitude [V] NA61: 32-channel DRS4 Acquisition Board Features:

low-power analog Front-End stage 4 DRS4 chips 12-bit 8-channel

0 Microcontroller (lab tests) RJ45 LVDS Interface to high speed

6 100 110 120 130 140 150 0 uncalibrated Time [ns] External Ref.

32-ch Analog Front-End Stage DRS4 (4x) ADC Cyclone V FPGA DDL

9 32-ch Analog Front-End Stage 4x DRS4 12-bit 8-ch ADC FPGA

4 Amplitude [V] NA61: 32-channel DRS4 Acquisition Board Features: 6U VME Form Factor with custom backplane 32 input channels with low-power analog Front-End stage 4 DRS4 chips 12-bit 8-channel ADC Altera Cyclone V FPGA USB 3.0 Microcontroller (lab tests) RJ45 LVDS Interface to high speed DDL Link uncalibrated Time [ns] External Ref. Clock (DRS4 sampling) Trig In Busy out 2x 16-input Connectors 32-ch Analog Front-End Stage DRS4 (4x) ADC Cyclone V FPGA DDL link I/F ch Analog Front-End Stage 4x DRS4 12-bit 8-ch ADC FPGA USB3 I/F DDL link I/F U2 I/F On-Board Voltage and Timing Calibration USB 3.0 Connector External Timing Calibration Connector December 2015 Electronics Highlights USB µc 4/10

CTA: Hardware + firmware Housekeeping board: Monitor the environment inside the

4 x Humidity + Temperature sensors 2 x Atmospheric pressure sensors 16 x Cooling

and maximum sensors limits and logic combinations Provides power to the camera

protection implemented Fully calibrated Others activities: PDP Boards upgrade &

Camera Shutter Driver based on CPLD with motor current limiter & lightning

softcore µblaze processor within Trigger Board FPGA) FAN ctrl I/F 4 x PT-100

Highlights Camera Shutter Driver Prototype 5/10 24V IN CAN PLC RS-422 2 Motorhead

5 CTA: Hardware + firmware Housekeeping board: Monitor the environment inside the camera to assure the camera electronics integrity: 4 x Temperature probes PT x Humidity + Temperature sensors 2 x Atmospheric pressure sensors 16 x Cooling fans rotor locked signal monitoring SW programmable alarm conditions on minimum and maximum sensors limits and logic combinations Provides power to the camera pointing LEDs Integrated CAN bus and safety PLC RS-422 interface Lightning surge protection implemented Fully calibrated Others activities: PDP Boards upgrade & launch for 2 nd camera production (mechanical improvement & lightning protection) Camera Shutter Driver based on CPLD with motor current limiter & lightning protection (2 motors) CAN to UDP Ethernet gateway (embedded firmware for Xilinx softcore µblaze processor within Trigger Board FPGA) FAN ctrl I/F 4 x PT-100 (SM58 shure I/F) 4 x H+T sensor 2 x Pressure sensor December 2015 Electronic Highlights Camera Shutter Driver Prototype 5/10 24V IN CAN PLC RS Motorhead I/F µc Guitar sat limits 2 Limit Switch I/F PLC Alarms CPLD Pointing leds PLC I/F Insulated power supply

TT-PET: Readout ASIC DOUT / CLKOUT / TRIG ASIC Features: ASIC N ASIC 3 ASIC 2 ASIC 1 System

timing acquisition Data I/F to central event-processing unit Input bloc diagram Analog Channel:

Scanner mock-up (Based on Elvis Mic) Digital logic: Incoming data readout with/without trigger

6 TT-PET: Readout ASIC DOUT / CLKOUT / TRIG ASIC Features: ASIC N ASIC 3 ASIC 2 ASIC 1 System overview CLK-SYNC TOWER CONTROL FPGA Photo-current read Conversion to digital pulse Event timing acquisition Data I/F to central event-processing unit Input bloc diagram Analog Channel: BJT input transistor with Kate MOS feedback High gain/ Low noise : 95 mv/fc / e- Peak time: 1.3 ns Small power consumption: 135 µw Small footprint, highly configurable Asic prototype Layout Scanner mock-up (Based on Elvis Mic) Digital logic: Incoming data readout with/without trigger Daisy chain arbiter + common bus cmd read External registers program I/O limited for easier system integration Scalable architecture (# chips, datawords) December 2015 Electronic Highlights 6/10

@ 2.5ns 96-ch 12-bits Lo-Gain + Hi-Gain Analog USB3 readout with VHDL Unige lib.

7 Baby-Mind : FEB FPGA hardware & firmware VHDL Library USB µc Aria V.People FPGA 12-bits ADC Gigabit chain YMCA ASICs Hardware: Improve analog stage (dynamic range) Improve analog power supplies (noise) Firmware: Tests: 2017: TDC (rising & 2.5ns 96-ch 12-bits Lo-Gain + Hi-Gain Analog USB3 readout with VHDL Unige lib. for slow control + 2Gb/s readout and chain mode Successfully tested during 2 beam tests campaign in summer (4 FEB in //, 384-ch) New hardware with VME format for minicrate integration Firmware upgrade for full FEB chain & common clock synchronisation New overall cabling with 32-ch custom connector on coaxial cables Full production (4000-ch, 55 FEB) December 2015 Electronic Highlights 7/10

Unige C# Library: USB3 readout software App: - MainWindow - BoardTab - Menu - Scripting Board: - BoardLink - Protocol - FirmwareUpdate - ReadoutThread - USB.Linux - USB.

Tools JSON HW & GUI descriptor Common USB3 projects library Graphics: - BoardTab - Histogram - Lib Menus - Scripting - Command interpreter Lib Features: Independent of hardware boards Provides all

8 Unige C# Library: USB3 readout software App: - MainWindow - BoardTab - Menu - Scripting Board: - BoardLink - Protocol - FirmwareUpdate - ReadoutThread - USB.Linux - USB.Win - NIRVANA Gui tools - Settings - DaqTools - FPGATools - itunes Scripting Application Config: - Version manager - Config Data - Config Descriptor - Config Utils - JSON converter - XML converter - Tools JSON HW & GUI descriptor Common USB3 projects library Graphics: - BoardTab - Histogram - Lib Menus - Scripting - Command interpreter Lib Features: Independent of hardware boards Provides all config + protocol + GUI + scripting tools Linux & Windows compatibility Based on GTK Application; Described hardware & GUI presentation with JSON descriptor file Used all Lib functionalities No compilation nor code if no specific features Add specific features if required (menu, gui, scripting functions, settings) Used on B-Mind & HERD readout Software architecture (C# on Win7 & Linux using GTK) December 2015 Electronic Highlights 8/10

9 Workshop Machines: New : LPK PCB Plotter for in-house PCB manufacturing 2017 planned : Stencil placer & SMD placement semi-automatic workshop Activities: In-house PCB manufacturing Cabling & boards assembly (CTA, PET, B-Mind, HVCMOS ) Small board design & layout (prototypes, adapters, tests) Functional tests, production programming (CTA) Bonding (HVCMOS, PET) Components stock (database) Reflow oven New PCB Plotter Fine pitch SMD rework Cable printer B-Mind 32-ch coax connector PET bonding CTA shutter driver CTA camera cabling HVCMOS bonding PET HF amplifier December 2015 Electronic Highlights 9/10

10 Coming next in 2017 Projects : Baby Mind: New VME hardware, FPGA firmware & PC software finalization, 4000 coax. on cabling PCBs Full production (55 FEB, 600 cabling PCBs, 4000 SiPM PCBs) for beam tests in June NA61: 32-ch DRS4 acquisition board FPGA firmware with DDL I/F, Clock/trigger board tests Full production (120 DRS4 boards) CTA: 2nd camera production (132 preamplifiers slow control boards) + functional testers upgrade Housekeeping board + shutter board installation, EMC & lightning tests & qualification Trigger board FPGA firmware? HERD: New board for VATA/SIPHRA ASIC qualification ATLAS: PET: SLIM prototypes (Stave flex, End of Stave board, Module adapters with PSPP chip) TDC ASIC design ASIC test boards, HF amplifier, bonding December 2015 Electronic Highlights 10/10

11 Season s greetings Joyeuses Fêtes

PETsys SiPM Readout System

PETsys SiPM Readout System SiPM Readout System FEB/A_v2 FEB/S FEB/I The SiPM Readout System is designed to read a large number of SiPM photo-sensor pixels in applications where a high data rate and excellent time resolution is required.