Sequential Logic. Building a Modern Computer From First Principles.

Transcription

1 Sequential Logic Buildg a Modern Computer From First Prciples Elements of Computg Systems, Nisan & Schocken, MIT Press, Chapter 3: Sequential Logic slide 1

2 Usage and Copyright Notice: Copyright Noam Nisan and Shimon Schocken This presentation accompanies the textbook The Elements of Computg Systems by Noam Nisan & Shimon Schocken, MIT Press, We provide 13 such presentations. Each presentation is designed to support ab 3 hours of classroom or self-study struction. You are welcome to use or edit this presentation as you see fit for structional and noncommercial purposes. If you use our book and course materials, please clude a reference to If you have any questions or comments, please write us at nand2tetris@gmail.com This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License. Elements of Computg Systems, Nisan & Schocken, MIT Press, Chapter 3: Sequential Logic slide 2

3 Sequential VS combational logic Combational devices: operate on data only; provide calculation services (e.g. Nand ALU) Sequential devices: operate on data and a clock signal; as such, can be made to be state-aware and provide storage and synchronization services Sequential devices are sometimes called clocked devices The low-level behavior of clocked / sequential gates is tricky The good news: All sequential chips can be based on one low-level sequential gate, called data flip flop, or DFF The DFF can be constructed from Nand gates Elements of Computg Systems, Nisan & Schocken, MIT Press, Chapter 3: Sequential Logic slide 3

4 Nand Implementation of DFF Elements of Computg Systems, Nisan & Schocken, MIT Press, Chapter 3: Sequential Logic slide 4

5 The Clock HW simulator demo tock tock tock tock clock signal tick tick tick tick cycle cycle cycle cycle In our jargon, a clock cycle = tick-phase (low), followed by a tock-phase (high) In real hardware, the clock is implemented by an oscillator In our hardware simulator, clock cycles can be simulated either Manually, by the user, or Automatically, by a test script. Elements of Computg Systems, Nisan & Schocken, MIT Press, Chapter 3: Sequential Logic slide 5

6 Flip-flop HW simulator demo DFF (t) = (t-1) A fundamental state-keepg device Memory devices are made from numerous flip-flops, all regulated by the same master clock signal Notational convention: sequential chip = (notation) sequential chip clock signal Elements of Computg Systems, Nisan & Schocken, MIT Press, Chapter 3: Sequential Logic slide 6

7 1-bit register (we call it ) Objective: build a storage unit that can: (a) Change its state to a given put (b) Mata its state over time (until changed) load if load(t-1) then (t)=(t-1) else (t)=(t-1) DFF DFF (t) = (t-1) Basic buildg block (t) = (t-1)? (t) = (t-1)? Won t work Elements of Computg Systems, Nisan & Schocken, MIT Press, Chapter 3: Sequential Logic slide 7

8 register (cont.) HW simulator demo Interface load Implementation load MUX DFF if load(t-1) then (t)=(t-1) else (t)=(t-1) o Load bit o Read logic o Write logic Elements of Computg Systems, Nisan & Schocken, MIT Press, Chapter 3: Sequential Logic slide 8

9 Multi-bit register HW simulator demo load load w... w if load(t-1) then (t)=(t-1) else (t)=(t-1) 1-bit register if load(t-1) then (t)=(t-1) else (t)=(t-1) w-bit register o Register s width: a trivial parameter o Read logic o Write logic Elements of Computg Systems, Nisan & Schocken, MIT Press, Chapter 3: Sequential Logic slide 9

10 Random Access Memory (RAM) load HW simulator demo (word) register 0 register 1 register 2. register n-1 (word) address (0 to n-1) RAM n Direct Access Logic o Read logic o Write logic. Elements of Computg Systems, Nisan & Schocken, MIT Press, Chapter 3: Sequential Logic slide 10

11 RAM terface load 16 bits address RAMn 16 bits log 2 n bits Elements of Computg Systems, Nisan & Schocken, MIT Press, Chapter 3: Sequential Logic slide 11

12 RAM anatomy RAM 64 RAM8 RAM 8. 8 Register register. register 8 RAM8... register... Recursive ascent Elements of Computg Systems, Nisan & Schocken, MIT Press, Chapter 3: Sequential Logic slide 12

13 Counter Needed: a storage device that can: (a) set its state to some base value (b) crement the state every clock cycle (c) mata its state (stop crementg) over clock cycles (d) reset its state c load reset w bits PC (counter) w bits If reset(t-1) then (t)=0 else if load(t-1) then (t)=(t-1) else if c(t-1) then (t)=(t-1)+1 else (t)=(t-1) Typical function: program counter Implementation: register chip + some combational logic. Elements of Computg Systems, Nisan & Schocken, MIT Press, Chapter 3: Sequential Logic slide 13

14 Recap: Sequential VS combational logic Combational chip Sequential chip (optional) time delay (optional) comb. logic comb. logic DFF gate(s) comb. logic = some function of () (t) = some function of ((t-1), (t-1)) Elements of Computg Systems, Nisan & Schocken, MIT Press, Chapter 3: Sequential Logic slide 14

15 Time matters tock tock tock tock clock signal tick tick tick tick cycle cycle cycle cycle Durg a tick-tock cycle, the ternal states of all the clocked chips are allowed to change, but their puts are latched At the begng of the next cycle, the puts of all the clocked chips the architecture commit to the new values. a Reg1 Implications: Challenge: propagation delays sel Solution: clock synchronization b Reg2 + Cycle length and processg speed. Elements of Computg Systems, Nisan & Schocken, MIT Press, Chapter 3: Sequential Logic slide 15

16 Perspective All the memory units described this lecture are standard Typical memory hierarchy Registers Access time, Amount Cost SRAM ( static ), typically used for the cache DRAM ( dynamic ), typically used for ma memory Disk (Elaborate cachg / pagg algorithms) But... real memory units are highly optimized, usg a great variety of storage technologies. Elements of Computg Systems, Nisan & Schocken, MIT Press, Chapter 3: Sequential Logic slide 16