Building a Virtual Computer

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Philippa Rodgers
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1 uilding a Virtual Computer From Gates to Operating System Student Researcher: Elisa Elshamy Faculty Mentor: Dr. Victoria Gitman

2 bstract modern computer can carry a plethora of multifaceted computations. Realizing this, one would be led to believe that computer hardware is built to be as complicated as machinery can get. Instead, it turns that the structure of computer hardware is really a sophisticated concatenation of elementary oolean gates. In this project, we used the Hardware Description Language (HDL) together with hardware simulator software to virtually build the components of a simple computer s hardware platform. Using the single fundamental building block NND gate, we started by building chips (concatenations of oolean gates) to carry the most basic logic functions such as ND, OR and NOT. From these chips, we in turn built the LU, RM, CPU and put it all together into a functioning hardware platform. Since the bare bones of computing come down to functions of binary patterns, we implemented the fundamental set of such functions in the LU. The first advanced function we built was multi-bit binary addition. Next, the rithmetic Logic Unit (LU) brought together the elementary oolean logic gates along with the addition function to become the chip that performs all basic binary functions required for program execution. To implement the storage and processing of data, the computer hardware requires an inbuilt clock. It is realized by an oscillator that alternates between two puts, and to signal tick and tock. The synchronization and time delay provided by the clock is exploited for data storage and manipulation by the fundamental Data-Flip-Flop (DFF) gate that implements the time-based behavior (t) = in(t-), where put is the input from the previous time unit. We used the DFF gate to build a basic unit of data storage that remembers a bit of information by constantly cycling its value between input and put until instructed to modify what it stores. These basic chips were glued together to form registers of which the Random ccess Memory (RM) is composed. The master behind computer operation is the Central Processing Unit (CPU). The CPU, which is composed of the LU, several registers and a program counter chip designed to keep track of program execution, synchronizes computer functionality by decoding, executing, and fetching program instructions. The instructions the CPU receives from the instruction memory or ROM (which is identical to the RM memory except it is used to store instructions and not data) are decoded to determine what actions the LU will take to execute each instruction, and where in the RM memory the LU s put will be stored. Upon completion of the CPU, we now have a fully functional computer hardware. We are continuing the project to implement the software end of the computer by writing the assembler, virtual machine, compiler, and operating system programs.

von Neumann rchitecture The stored program concept Memory (data + instructions) CPU rithmetic Logic Unit (LU) Registers Control Input Output Memory continuous array of registers where each cell has a

3 von Neumann rchitecture The stored program concept Memory (data + instructions) CPU rithmetic Logic Unit (LU) Registers Control Input Output Memory continuous array of registers where each cell has a unique address Data Memory Read and written to by programs, assist with program execution Instruction Memory Where high-level and machine language programs that decode high-level instructions are stored CPU Central Processing Unit, executes instructions of current program rithmetic Logic Unit (LU) Performs low-level arithmetic and logic operations Registers Small amount of local memory for quick calculating Control Unit Decodes, executes and fetches instructions Input/Output Screens, keyboards, mice, printers, scanners, network interface cards, and other peripheral Depicted left is the von Neumann architecture. The von Neumann machine is a conceptual blueprint for building many computers today and is best known for using the stored program concept. John von Neumann The stored program 2/28/93 2/8/957 concept is a key element to many computer models, abstract and practical alike. Instead of embedding programs into hardware, programs are stored in the computers memory much like software. This allows for reusability with the hardware and the versatility of loading different programs to instruct the computer to perform different tasks. The von Neumann architecture associated with our platform separates instruction from data memory. Instruction memory holds the program s code and data memory is manipulated as needed to assist with program execution.

uilding locks Logic diagram for NND gate oolean logic for NND gate Hardware Simulator We used the NND gate as a building block to build all the other gates (ND,

The hardware simulator is a software tool that can make a model of any chip as specified by an HDL (Hardware Description Language) program.

4 uilding locks Logic diagram for NND gate oolean logic for NND gate Hardware Simulator We used the NND gate as a building block to build all the other gates (ND, OR, NOT, XOR, etc) Every gate, can be built from a simple NND gate Gates were built virtually, no usage of soldering irons or wires, but a hardware simulator. The hardware simulator is a software tool that can make a model of any chip as specified by an HDL (Hardware Description Language) program. In the real world, hardware designers use simulators much like this one to completely plan chip architecture and perform a series of rigorous testing before any production takes place.

5 Elementary Logic Gates in NOT ND Logic diagram for NOT gate Logic diagram for ND gate OR Logic diagram for OR gate in oolean logic for NOT gate oolean logic for ND gate oolean logic for OR gate CHIP Not { IN in; OUT ; PRTS: Nand(a=in, b=in, =); } NOT gate HDL program CHIP nd { IN a, b; OUT ; PRTS: Nand(a=a, b=b, =nandout); Not(in=nandOut, =); } ND gate HDL program CHIP Or { IN a, b; OUT ; PRTS: Not(in=a, =aout); Not(in=b, =bout); Nand(a=aOut, b=bout, =); } OR gate HDL program

6 Multiplexor Gate The root of conditional logic MUX sel Logic diagram for MUX gate C D 4-way MUX sel[] sel[] Logic diagram for 4-way MUX gate sel sel[] Conditional logic for MUX gate If sel == = ; else = ; sel[] C D Conditional logic for 4-way MUX gate CHIP Mux { IN a, b, sel; OUT ; PRTS: Or(a=a, b=sel, =); Not(in=b, =not); Nand(a=not, b=sel, =2); nd(a=, b=2, =); } MUX gate HDL program The multiplexor gate uses the selector bit to decide which pin to put. We can think of the logic of the multiplexor gate as an conditional if statement. We later built more complicated models such as the 4-way multiplexor shown left. The inputs,, C, and D as well as the put are each 6-bit wide.

7 inary ddition 2 s complement numbers and adder chips inary ddition We add a pair of binary numbers the same way we would its decimal representation. Starting from the right column (Least Significant its) and bringing the carry bit ( or ) to the next column until we reach the leftmost column (Most Significant its). The binary system is founded on base 2. If we are presented a binary string such as, we can convert it to its decimal equivalent as follows: = *2 + *2 + *2 + *2 + *2 = 9 2 s Complement for signed binary numbers To represent signed Positive numbers, we split the bit Numbers (carry) space into two equal 3 subsets. ddition of signed + -4 binary numbers is (-4) = - equivalent to its decimal representation. Half dder sum carry (MS) Half dder Half-dder (left) & Full-dder implementation (right) C (LS) Half dder OR sum carry Negative Numbers s complement for a 3-bit binary system 2 x = n 2 = 2 x 3 if x otherwise 2 = 6 =

8 x y 6 bits rithmetic Logic Unit (LU) zx nx zy ny f no LU zr ng LU Logic Diagram f(x.y) 6 bits zr //True iff = ng //True iff < These bits preset the x input zx if zx then x= nx if nx then x=!x These bits preset the y input zy if zy then y= ny if ny then y=!y f if f then =x+ y else = x&y no if no then =! Resulting LU function = f(x,y)=!x!y x + y y - x x & y LU truth table showing some of the possible logic functions that can be computed based on the first six bits. The complete 6-bit LU table would show sixty-four functions Using careful design, a 6-bit LU can compute 2 6 =64 functions. Which function the LU decides to put is based on a combination of six bits called control bits. The LU is the chip that is constructed to carry all the primitive operations desired in the computer architecture and at the heart of its logic. x y

9 Clocks and Flip-Flops computer clock is much like a see-saw, alternating back and forth between signals ( and ) in DFF (t) = in(t-) Logic diagram of data flip-flop. t the end of each clock cycle, the DFF puts the input value from the previous cycle. Clock Cycles Computers use a master clock to represent the passage of time. This clock is usually implemented from an oscillating device that delivers an infinite alternating train of signals ( and, low and high, tick and tock). computer clock cycle is defined to start at the beginning of a tick and conclude at the end of the subsequent tock. Flip-Flops Flops To build chips which could maintain state, it was essential to have a building block with sequential properties. The data flipflop, or DFF, takes the current clock s signal as input to implement time-based behavior. In other words, the DFF takes advantage the clock and uses it to control the put of data. Memory chips built on top of DFFs remember values by sending put back to the input pin and putting it again until told by a control bit to accept a new value.

10 in load MUX From Registers to RM maintaining state with feedback loops DFF if load(t-) then (t) = in(t-) else (t) = (t-) Logic diagram of -bit data register in IT Registers and Feedback Loops DFF can only put its previous input, (t) = in(t-). register on the other hand, can also put a previous put, (t) = (t-) and thus maintain state. This is accomplished in sequential chips through the formation of feedback loops. feedback loop occurs when the put can be fed back to the input pin of the chip. Sequential chips, such as DFFs have an inherent time delay due to the clock input and allow for the construction of memory devices, such as registers. register stores values according to the control bit (load). If load is, the register reads the value from in and stores it. If load is, it keeps the current value. in load... IT load IT From single to multi-bit registers to Random ccess Memory (RM). in (word) address ( to n-) load Register Register Register n- n RMn direct access logic (word)

11 Random ccess Memory (RM) RM is an array of n w-bit registers. We describe the RM s specs in accordance to the number of registers n and the width of each register w. These components are referred to as the memory s size and width respectively. RM storage and Retrieval of data load RM 64 Read: To read a value from a given register m within the RM, we must put m in the Register RM8 address input. The value in register m will Register be putted to the RM s put pin. in (word) address ( to n-) Register 8 RM8 direct access logic (word).. RM8 Depicted above is the gradual construction of RM. The underlying architecture of RM is nothing more than an array of registers. Write: To write a value d to a given register m within the RM, we must put m in the address input, d in the in input, and signal the load input. The RM s direct access logic will select the register m and use the load bit to enable it for data storage. In the next clock cycle, the value d will be committed to register m and the RM s put pin.

12 Designated Registers for machine language instructions Other than the instruction memory (ROM) and data memory (RM), there is a set of registers in the processor s region. This set of registers is handy when the processor is carrying a list of instructions and must maneuver data and instructions at high speed. M Register Register Local to the processor Value is the address of a register in RM Value may also represent the location of the next instruction that should be executed Can also store data values and constants on the fly For example if we want = //= The proceeding instruction decides how to use the value D Register Local to the processor Stores data values only for quick calculations and comparison testing of conditionals For example if we want //=5 D = //D==5 Not local to the processor n actual memory location in RM ccessed by the value in the register, in other words the value of the register is the address of the M register s location. For example if we want M[56] = //=56 M = 4 //M[56] = 4

13 /C-Instructions machine language specification machine language program is a series of coded instructions written for the computer to perform basic arithmetic and logic functions. The hardware specification and machine language syntax describe how these coded instructions are read. Since binary strings are cryptic to the human brain, assembly language was developed to make low-level programming feasible. ssembly language replaces codes such as to symbols like add which are easier to understand and much more readable. Since program instructions are 6-bits wide and addresses are specified by 5-bits, our computer platform separates operation code from address instructions. In order to distinguish between the two instructions, -Instructions (address code) always have a most significant bit of while C-Instructions (Computation Code) always have a most significant bit of. -Instructions Value (v = or ) v v v v v v v v v v v v v v v Sets the register to a 5-bit value Must be a non-negative decimal value Uses of -Instruction: Enter a constant on the fly Specifies the location of data memory that should be manipulated by the subsequent C-Instruction Specifies the location for the jump destination of the proceeding instruction C-Instructions a c c2 c3 c4 comp dest jump c5 c6 d d2 d3 j j2 j3 The C-Instruction is broken into three fields: Comp Tells the LU which function to compute as predefined by the language specification Dest States which register(s) (, D, or M) should store the computed value Jump Notifies the computer of which instruction to fetch next.

I/O Handling interacting with the screen and keyboard Input/Output Handling Our computer can interact with two peripheral devices: a screen and a keyboard.

14 I/O Handling interacting with the screen and keyboard Input/Output Handling Our computer can interact with two peripheral devices: a screen and a keyboard. The computer platform and these devices talk to each other via memory maps. Drawing pixels on the screen and listening to the keyboard is accomplished by writing to and reading from designated memory segments associated with the peripherals. Screen Our computer uses a black-and-white screen with 256 rows of 52 pixels per row. The screen s memory map begins at RM address 6384 and every row is represented by a 32 6-bit word. To read or write to a pixel on the screen, the corresponding bit in the memory map must be read or written to (=white, =black). Keyboard The keyboard s single-word memory map begins at RM address nytime a key is pressed it s SCII code appears in RM[24576]. If no key is pressed, RM[24576] holds the value. Simulation of the screen and keyboard used with our computer.

15 Central Processing Unit (CPU) Central Processing Unit The CPU is designed to process instructions and is the core of computational logic. Underlying the CPU is the LU, a set of registers, and control logic (i.e. Mux gates) all of which are implemented for assisting with fetching and decoding instructions. CPU s Control Logic Instruction Decoding The 6-bit word in the CPU s input pin can either represent an address or a compute instruction. The CPU decodes the instruction by breaking it into smaller fields. Instruction Executing fter the instruction is broken into smaller fields, the CPU res each part to it s designated chip. For example, a part of the instruction gets sent to the LU where it will determine which function to compute. Next Instruction Fetching s the CPU executes the current instruction, it must also determine which instruction to process next. This is accomplished as a function of the current instruction, the LU put and the program counter. Logical diagram of the CPU. It should be noted that this diagram is intended to give a brief overview and is missing detail such as the CPU s control logic.

The Computer Platform Our computer platform as a logic diagram depicted above. Underlying the computer architecture are memory gates and the CPU chip.

This computer platform is a general-purpose machine, meaning that it is versatile and can switch from running one program to another. The significance of hardware design lies in its performance.

16 The Computer Platform Our computer platform as a logic diagram depicted above. Underlying the computer architecture are memory gates and the CPU chip. elow, a simple sketch of our computer interacting with peripheral devices. Using all the gates and chips mentioned, we built a complete computer platform. This computer platform is a general-purpose machine, meaning that it is versatile and can switch from running one program to another. The significance of hardware design lies in its performance. Issues circumventing performance usually regard memory hierarchies, better access to I/O devices, instruction prefetching, and anything that can allow for faster computation. Our next steps will be to implement the software end of the computer by writing the assembler, virtual machine, compiler, and operating system programs.

CS 31: Intro to Systems Digital Logic

CS 31: Intro to Systems Digital Logic CS 3: Intro to Systems Digital Logic Martin Gagné Swarthmore College January 3, 27 You re going to want scratch papr today borrow some if needed. Quick nnouncements Late Policy Reminder 3 late days total