Zynq Ultrascale+ Architecture
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1 Zynq Ultrascale+ Architecture Stephanie Soldavini and Andrew Ramsey CMPE-550 Dec 2017 Soldavini, Ramsey (CMPE-550) Zynq Ultrascale+ Architecture Dec / 17
2 Agenda Heterogeneous Computing Zynq Ultrascale+ History Architecture Applications Soldavini, Ramsey (CMPE-550) Zynq Ultrascale+ Architecture Dec / 17
3 Problem: Flexibility/Performance Trade Off Flexibility Programmability / General Purpose Processors (GPPs): Selection Factors: Application-Specific Processors (ASPs) Configurable Hardware e.g. FPGAs - Type and complexity of computational algorithms (general purpose vs. Specialized) - Desired level of flexibility - Performance - Development cost - System cost - Power requirements - Real-time constrains Co-Processors Application Specific Integrated Circuits (ASICs) Specialization, Development cost/time Performance/Chip Area/Watt (Computational Efficiency) Software Hardware Performance Soldavini, Ramsey (CMPE-550) Zynq Ultrascale+ Architecture Dec / 17
4 Problem: Flexibility/Performance Trade Off Flexibility Programmability / General Purpose Processors (GPPs): Selection Factors: Application-Specific Processors (ASPs) Configurable Hardware e.g. FPGAs - Type and complexity of computational algorithms (general purpose vs. Specialized) - Desired level of flexibility - Performance - Development cost - System cost - Power requirements - Real-time constrains Solution: Use some of each in a single system Co-Processors Application Specific Integrated Circuits (ASICs) Specialization, Development cost/time Performance/Chip Area/Watt (Computational Efficiency) Software Hardware Performance Soldavini, Ramsey (CMPE-550) Zynq Ultrascale+ Architecture Dec / 17
5 Heterogeneous Computing Combine the use of different devices, for example: Hardware accelerator used to speed up one function in a program Offload matrix calculations to a GPU Cloud system with GPP, GPU, and/or FPGA resources Allows for each part of a task to run on the device it is best suited for Soldavini, Ramsey (CMPE-550) Zynq Ultrascale+ Architecture Dec / 17
6 Zynq Ultrascale+ History Made by Xilinx Microheterogenous Integrates GPP, GPU, FPGA, Co-Proc, & ASIC in one SoC Increases speed by reducing off-chip data transfer Predecessors Kintex-UltraScale and Virtex-UltraScale (20/16nm FPGA fabric) Zynq-7000 (Dual-core ARM Cortex A9 & 28nm FPGA fabric) Soldavini, Ramsey (CMPE-550) Zynq Ultrascale+ Architecture Dec / 17
7 General Architecture Processing System (PS) Application Processing Unit (APU) 64-bit quad-core or dual-core ARM Cortex-A53 Real-time Processing Unit (RPU) 32-bit dual-core ARM Cortex-R5 Graphics Processing Unit (GPU) ARM Mali-400 On-Chip Memory (OCM) 256 kb RAM with Error-Correcting Codes (ECC) Programmable Logic (PL) 16nm FinFET+ programmable logic Configurable Logic Blocks (CLB) 36 kb Block RAMs UltraRAM DSP Blocks Soldavini, Ramsey (CMPE-550) Zynq Ultrascale+ Architecture Dec / 17
8 Processing System (PS) Programmable Logic (PL) Interconnects & I/O Soldavini, Ramsey (CMPE-550) Zynq Ultrascale+ Architecture Dec / 17
9 Application Processing Unit (APU) 64-bit quad-core or dual-core ARM Cortex-A53 Up to 1.5 GHz ARMv8-A Architecture 64-bit mode: A64 instruction set 32-bit mode: A32/T32 instruction set Single/double precision floating point unit (FPU) Cache IL1: 32 kb 2-way set-assoc with parity (independent for each CPU) DL1: 32 kb 4-way set-assoc with ECC (independent for each CPU) L2: 1 MB 16-way set-assoc with ECC (shared between CPUs) Soldavini, Ramsey (CMPE-550) Zynq Ultrascale+ Architecture Dec / 17
10 Real-time Processing Unit (RPU) 32-bit dual-core ARM Cortex-R5 Up to 600 MHz ARMv7-R Architecture: A32/T32 instruction set Single/double precision FPU Caches/Tightly Coupled Memory (TCM) L1: 32 kb 4-way set-assoc with ECC (independent for each CPU) TCM: 128 kb (independent, but can be combined into one 256 kb) Soldavini, Ramsey (CMPE-550) Zynq Ultrascale+ Architecture Dec / 17
11 Graphics Processing Unit (GPU) ARM Mali-400 Up to 667 MHz One geometry processor Two pixel processors Supports OpenGL 1.1 & 2.0, OpenVG 1.1 Advanced anti-aliasing support Cache: L2: 64 kb Soldavini, Ramsey (CMPE-550) Zynq Ultrascale+ Architecture Dec / 17
12 Programmable Logic (PL) 16nm FinFET+ programmable logic Configurable Logic Blocks (CLB) Look Up Tables (LUT) Flip flops (FF) Cascadable adders 36 kb Block RAMs True dual-port Up to 72 bits wide Configurable as dual 18 kb UltraRAM 288 kb 72 bits wide ECC DSP Blocks signed multiply 48-bit adder/accumulator 27-bit pre-adder Soldavini, Ramsey (CMPE-550) Zynq Ultrascale+ Architecture Dec / 17
13 Vivado Design Suite Bright green shows configurable components Soldavini, Ramsey (CMPE-550) Zynq Ultrascale+ Architecture Dec / 17
14 Vivado Design Suite Customize components, for instance the DDR controller Soldavini, Ramsey (CMPE-550) Zynq Ultrascale+ Architecture Dec / 17
15 Applications Data Center: Networked Storage/Service Platform[2] Multimedia, video encoding/decoding[1] Particle physics[4] Automotive driver assistance, driver information, and infotainment. LTE radio and baseband. Medical diagnostics and imaging. Video and night vision equipment. Wireless radio. Single-chip computer. Soldavini, Ramsey (CMPE-550) Zynq Ultrascale+ Architecture Dec / 17
16 Application: Data Center A sample configuration used for a networked storage platform 4.5X performance speed-up & 20X power reduction over x86 implementations Soldavini, Ramsey (CMPE-550) Zynq Ultrascale+ Architecture Dec / 17
17 Questions? Soldavini, Ramsey (CMPE-550) Zynq Ultrascale+ Architecture Dec / 17
18 References [1] Gosain, Y. and A. Gupta Xilinx Advanced Multimedia Solutions with Video Codec/Graphics Engines, Zynq UltraScale+ MPSoC. Xilinx, October papers/wp497-multimedia.pdf [2] Hansen, L Unleash the Unparalleled Power and Flexibility of Zynq UltraScale+ MPSoCs, Zynq UltraScale+ MPSoC. Xilinx, June papers/wp470-ultrascale-pluspower-flexibility.pdf [3] Shaaban, M. Basics of Computer Design. Lecture, CMPE-550, Rochester, NY, August 29, [4] Stamen, R. The Development of the Global Feature extractor (gfex) for the ATLAS Level 1 Calorimeter Trigger at the LHC Presented at TWEPP 2017, Santa Cruz, CA, [5] Xilinx, Overview, Zynq UltraScale+ MPSoC Data Sheet, July sheets/ds891-zynq-ultrascale-plusoverview.pdf [6] Xilinx, Zynq UltraScale+ Device, Technical Reference Manual, November guides/ug1085-zynq-ultrascaletrm.pdf Soldavini, Ramsey (CMPE-550) Zynq Ultrascale+ Architecture Dec / 17
Copyright 2017 Xilinx.
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