First Cortex-M7 MCU, STM32F7. STMicroelectronics
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1 First Cortex-M7 MCU, STM32F7 STMicroelectronics
2 MCUs new families development focus 2 Flash (bytes) 2 M High-performance & Ultra-low-power 32-bit core 1 M 128 K 16 K 2 K Standard voltage & Ultra-low-power STM8S Mainstream STM8A Automotive STM8L Ultra-low-power STM32 F7 - Cortex-M7 STM32 F4 - Cortex-M4 STM32 F3 - Cortex-M4 STM32 F2 - Cortex-M3 STM32 F1 - Cortex-M3 STM32 F0 - Cortex-M0 STM32 L4 - Cortex-M4 STM32 L1 - Cortex-M3 STM32 L0 - Cortex-M0+ 8-bit core Features
3 STM32 DMIPS performance 3 DMIPS MHz
4 A rich & reliable product base and 216 PIN / 2M Flash /320KSRAM 4 Over 600 STM32 Pin-to-pin compatible devices 20 PIN / 16KFlash
5 STM32 F7 : continuity in STM32 portfolio 5 9 product series / 33 product lines High-performance 398 CoreMark 120 MHz 150 DMIPS 608 CoreMark 180 MHz 225 DMIPS 1082 CoreMark 216 MHz 462 DMIPS Mainstream 106 CoreMark 48 MHz 38 DMIPS CoreMark 72 MHz 61 DMIPS CoreMark* 72 MHz 90 DMIPS (*) from CCM-SRAM 1 Ultra-low-power 75 CoreMark 32 MHz 26 DMIPS 93 CoreMark 32 MHz 33 DMIPS 273 CoreMark 80 MHz 100 DMIPS Cortex-M0 Cortex-M0+ Cortex-M3 Cortex-M4 Cortex-M7 number of lines
6 STM32 ecosystem 6 Hardware tools Software tools Embedded software
7 Hardware tools STM32 ecosystem 7 STM32 Nucleo Discovery kits Evaluation boards 3 rd parties Typical use case Extension possibilities Connectivity Flexible prototyping, Community Arduino ST Morpho Prototyping, Creative demos ST Full feature evaluation ST From full evaluation to open hardware
8 Software tools STM32 ecosystem 8 STM32Cube MX Generate Code Partners IDEs Compile & Debug STMStudio Monitor Free IDE
9 Embedded Hardware software tools STM32 ecosystem 9
10 Apps & social media STM32 ecosystem 10 Find more about STM32 products and solutions: ST MCU Finder mobile application Social media ST Forums on microcontrollers facebook.com/stm32 youtube.com/stonlinemedia Mbed.org ARM connected community
11 STM32 F7 block diagram 11 NEW core: ARM Cortex-M7 Up to 216 MHz, 462 DMIPS /1082 CoreMark Twice more DSP performance vs Cortex-M4 core New generation of Peripherals 3xI2S, 4xI2C, USB dedicated supply for 1.8 V operation, CEC, Quad SPI, SPDIF input, 2xSAI(SPDIF output),... Same packages as F429 WLCSP143 LQFP100,144,176,208 BGA 176, 216
12 STM32 F7 portfolio 12 Flash size (byte) 1 M 512 K STM32F756VG STM32F756ZG STM32F756IG STM32F756BG STM32F756NG STM32F746VG STM32F746ZG STM32F746IG STM32F746BG STM32F746NG STM32F756VE STM32F756ZE STM32F756IE STM32F756BE STM32F756NE STM32F746VE STM32F746ZE STM32F746IE STM32F746BE STM32F746NE LQFP100 LQFP144 WLCSP143 LQFP176 UFBGA176 LQFP208 TFBGA216 Pin count Legend: without HW crypto/hash coprocessor with HW crypto/hash coprocessor
13 Key words of STM32 F7 series STM32F756x Technical Training
14 1 First 14 ST is first to sample fully functional Cortex-M7 based 32-bit MCU: STM32 F7 series ST is a lead partner of ARM; ST actively participated to the specification of today s new Cortex -M7 core ST is ready with fully functional samples of the STM32 F7 microcontroller in TFBGA216 The first product of the new F7 series The STM32 F7 product is running several application demonstrations on an STM32 evaluation board. Full functional product today
15 2 Smart Architecture Use case 15 SDRAM, QUADSPI, NOR, NAND Legend: ITCM: Critical Code with deterministic execution DTCM RAM: Critical real time data ( Stack, heap..) System SRAM: Concurrent data transfer CPU or DMA External Memories: Quad SPI, and FMC for data manipulation or code execution
16 3 Record Performance 16 Unleashed by STM32 F7 Silicon Benchmark And : Cortex-M4 ARM data Cortex-M7 Up to twice more DSP performance increase over Cortex-M4 Measured on STM32 F7 Silicon Executing from Embedded Flash CoreMark/MHz DMIPS/MHz ARMv7-M architecture, 100% binary forwards compatibility from Cortex-M4 STM32 F7 runs at F CPU = 216 MHz 5 x CoreMark Executing from External memory
17 CoreMark 3 3/7 Record Performance 17 Fully compatible with the STM32 F4 and fully reuses STM32 Ecosystem Our next step will go for the 2000 CoreMark on the next technology node CoreMark Cortex-M7 ST 90nm eflash Next 2000 CoreMark Cortex-M7 ST next eflash node CoreMark Cortex-M3 ST 90nm eflash 608 CoreMark Cortex-M4 ST 90nm eflash MHz F CPU
18 4 Power Efficient 18 STM32 F7 power efficiency = STM32 F4 power efficiency STM32 F7 Boosts performance, but does not compromise on power efficiency Typ current STM32 F7 7 CoreMark/mW at 1.8 V Low power modes (leakages kept at the same level than STM32 F4) STM32 F4 7 CoreMark/mW at 1.8 V 120µA Wake up time: 105μs 290µA Wake up time: 22μs 2.2µA 3.1µA Wake up time: 318μs <1µA Dynamic : RUN Mode* STOP Mode Standby Mode w/o and w/ RTC V BAT Mode w/o or w/ RTC Legend: Measurements conditions depend on Room temperature *Run mode Conditions: CoreMark executed from Flash, peripherals OFF
19 STM32 F7 Demos 19 Pin-to-pin compatibility, enables demonstrations on the same board for STM32 F4 and STM32 F7 devices. STM32 benchmark demonstration shows (in 2 demos) increase of performance on the F7 vs. F4 series : Multi-tasking benchmark: Manages the HMI frames on the display, the buttons on the board, and shows the STM32 core performance to manage 2 computation intensive tasks (decodes and displays simultaneously two MJPEG files from one single USB mass storage device). Key performance enablers: ART Accelerator, L1 cache, ST Chrom-ART Accelerator and bus matrix to send the picture to the LCD. Recursive FPU computation: Computes and displays the Julia set fractal. Key performance enablers: FPU, ART Accelerator, L1 cache.
20 Multi-tasking benchmark 20 Video Player Frame window Controls Data Processing Storage unit manager Frame Rate 20 fps* Window manager (WM) Video Processing JPEG decoder 13 fps* x1.50 faster GUI core Display process STM32 F4 at 180 MHz STM32 F7 at 200 MHz Requires high CPU resources * : frames per second
21 Recursive FPU computation benchmark 21 Fractal Frame window Controls Julia Algorithm Processing Execution time 787 ms Window manager (WM) GUI core Display process x1.71 faster 459 ms Requires high CPU resources STM32 F4 at 180 MHz STM32 F7 at 200 MHz
22 Cortex-M7 STM32F756x Technical Training
23 Cortex-M7 overview 23 Performance and configurability Six-stage dual-issue pipeline (superscalar, branch prediction) Powerful DSP instructions and SP/DP Floating Point Flexible system and memory interfaces : TCM, AXI and AHB Harvard caches (4kB of I-cache and 4kB of D-cache) Dedicated peripheral and DMA ports Power efficiency Clock gating, support of WIC and Sleep modes same as CM3/CM4 Support of multiple power domains and state retention Safety Memory ECC (SEC-DED), MPU, MBIST, lock-step operation, full data trace, safety manual Debug and Trace ETMv4 instruction and optional data trace support Serial-Wire and JTAG support
24 Core Architecture 24 ITCM (64-bit) D0TCM (32-bit) D1TCM (32-bit) TCU SQ AHBS AHBS (32-bit) MPU NVIC DBG PFU DPU FPU STB LSU AHBP Interrupts AHBP (32-bit) ICU RAM BIU DCU RAM AHBD Cortex-M7 Debug ATB Trace ETM Trace EPPB L2 AXIM (64-bit AXI4)
25 Cortex-M7 Pipeline 25 Load Store #1 Load Store #2 Load Store #3 Load/Store #1 pipeline Prefetch Fetch Decode (1 st Decode) Issue (2 nd Decode) Load Store #1 Execute #1 Load Store #2 Execute #2 Load Store # Write Store Retire Load/Store #2 pipeline ALU #1 pipeline 6-stage Execute #2 Write Store ALU #2 pipeline Superscalar (dual-issue) MAC #1 MAC #2 MAC pipeline In-order Branch prediction Float #1 Float #2 Float #3 Float #4 Execution pipelines Float Pipeline (optional)
26 Memory I/F 26 A Tightly-Coupled interface Unit (TCU) Memory Interface between TCMs and CPU ITCM DTCM All TCMs: Support wait-states Can be used at boot-up 64-bit 32-bit TCU 64-bit 32-bit SQ 64-bit AHBS Fixed base address ITCM : 0x , DTCM : 0x PFU LSU Instruction TCM (ITCM) 64-bit interface single port. Flash connected to this interface needs to be accelerated externally to meet processor fetch bandwidth requirements at expected frequencies Data TCM (DTCM) 2 x 32-bit interface: D0TCM and D1TCM is selected according to addresses bit[2] The upper 32-bits of data is on the D1TCM interface and the lower 32-bits of the data is on the D0TCM interface.
27 Bus Interface Unit (BIU) Memory I/F with a configurable AMBA 4 AXI interface that can support a high-performance L2 memory system. 27 AXI - Interface to L2 system: L2 Caches ( if implemented) On/Off-chip memory Devices & Peripherals Single AXI 64-bit interface Buffers implemented to decouple bus transfer from CPU 2 data linefill buffers 1 instruction linefill buffer 1 store buffer 1 write buffer An extended AHB-Lite interface to support low-latency system peripherals.
28 Memory I/F AHB Limitations & AXI concept 28 AHB : 1 transaction at a time The request MUST be followed by its corresponding data (bus blocked if memory latency) The request can be a read OR a write To allows more transaction in parallel (instruction fetch, data fetch, peripheral accesses etc ) we need several AHB busses Cortex-M4 has 3 AHB busses AXI is decorrelating request and data phase The request is independant from its corresponding data (bus available if memory latency) Equivalent of 1 bus for request &1 for data (& optionally 1 for write acknowledge) Out of ordering is possible if no functional relationship (ex. Ins.Fetch & Data Fetch) AXI is separating read and writes Read bus & Write bus are splitted : a read can be launch in the same cycle than a write Total equivalent of 5 busses: Read Request, Read Data, Write Request, Write Data, Write Acknowledge
29 Caches 29 Harvard architecture for optimum performance I and D both optional, separately configurable sizes (4kB 64kB each) Cache only serve the AXIM region (No caching for the TCMs or AHBP) I-cache 2-way associative, D-cache 4-way associative, Extensions required to the ARMv7E-M system architecture Addition of cache maintenance operations: Add-on of new registers for cache maintenance. System SW will be impacted by cache inclusion
30 ART Accelerator
31 Flash Memory AXIM AHBP DMA_MEM1 DMA_MEM2 DMA_P2 64-bit Bus Matrix ART Flash interfaces 31 3 Main Flash interfaces 64-bits ITCM interface 64-bits AXI/AHB interface 32-bits AHB register interface Cortex-M7 L1-Cache 4KB I/D DMA1 DMA2 ETH DMA USB HS DMA LCD- TFT DMA Chrom- ART 64-bit ITCM Bus Flash Interface AXI to Multi- AHB Flash bus 64-bit AHB Flash register on AHB1 32-bit Bus Matrix
32 ART Accelerator 32 ART Accelerator for F7 series The ART (Adaptive Real-Time) memory accelerator unleashes processing performance equivalent to 0-wait state Flash execution up to 216 MHz for F7 series Core ART Accelerator Flash memory Cortex-M7 CPU 64-bit ITCM it Arbitration and branch management wide embedded Flash memory
33 QuadSPI
34 Overview 34 Communication interface for single/dual/quad SPI flash memories Three operating modes Indirect : all the operations are performed through registers (classical SPI) Status polling : periodical read of the flash status registers (interrrupt generation) Memory mapped : External flash seen as internal for read operations QUADSPI Registers / Control Clock Management QSPI Flash AHB FIFO Shift Register CLK BK1_IO0/SO BK1_IO1/SI BK1_IO2 BK1_IO3 BK1_nCS CLK Q0/SI Q1/SO Q2/nWP Q3/nHOLD ncs
35 Dual-quad mode 35 Access two flashes in parrallel with the same frame format and the same instruction (8-bit per cycle) QUADSPI Registers / Control Clock Management QSPI Flash AHB FIFO CLK BK1_IO0/SO BK1_IO1/SI BK1_IO2 BK1_IO3 BK1_nCS CLK Q0/SI Q1/SO Q2/nWP Q3/nHOLD ncs Shift Register QSPI Flash CLK BK2_IO0/SO BK2_IO1/SI BK2_IO2 BK2_IO3 BK2_nCS Q0/SI Q1/SO Q2/nWP Q3/nHOLD ncs
36 Three functional modes: Indirect Status-polling Memory-mapped Main features 36 Optimized operations Dual-flash mode (8 bits accessing two flash memories in parallel) SDR and DDR support Fully programmable Opcode for both indirect and memory mapped mode Frame format for both indirect and memory mapped mode Integrated FIFO for reception and transmission 8, 16, and 32-bit data accesses are allowed DMA channel for indirect mode operations Interrupt generation on FIFO threshold, timeout, operation complete, and access error
37 Each of the 5 phases is fully configurable Enabled or not Lengh Number of lanes Frame format 37 Exemple of Read configuration Example : read Instruction on 1 lane Address, Alternate & Data on 4 lanes 2 dummy cycles Instruction Address Alt Dummy Data ncs SCLK IO 0 IO 1 IO 2 IO A A 15-8 A 7-0 M 7-0 Byte 1 Byte IO switch from output to input
38 Sony/Philips Digital InterFace receiver ( SPDIF-RX )
39 SPDIF-RX Usage 39 M74HCU04 10 k 10nF k HDMI OUT Video CEC Stream control CEC ARC Signal Adapter (HEAC+, HEAC-) IN1 STM32F7xx CEC SPDIF IN Digital Signal Adapter IN2 SPDIF-RX SPDIF IN Optical IN3 SAI SPDIF-TX TORX173 TORX147 DL313 Output
40 SPDIF Protocol Overview 40
41 SPDIF IEC60958 (1/3) The block structure is used to organize the Channel Status, and User information. 41 Each block contains 192 frames Each frame contains 2 sub-frames Each sub-frame contains 32 bits A preamble allows the detection of the block and sub-frame boundaries Preamble B detects the start of new block, and the start of a Channel A Preamble M detects the start of a Channel A (when it is not a block boundary) Preamble W detects the start of a Channel B X Y Z Y X Y X Y Z Y M Ch A W Ch B B Ch A W Ch B M Ch A W Ch B M Ch A W Ch B B Ch A W Ch B Sub-frame Sub-frame Frame 191 Frame 0 Frame 1 Frame 191 Frame 0 Start of block Start of block
42 Each sub-frame contains The preamble Up to 24-bit data 4 Status bits SPDIF IEC60958 (2/3) 42 V is the validity bit, it means that the current sample can be directly converted into an analog signal. P is the parity bit of the received sub-frame, it is used to check the received sub-frame U: Is the User data channel, each message is composed of 192 bits per sub-frame CS: Is the Channel Status, each message is composed of 192 bits per sub-frame (i.e. sampling rate, sample length.) Sync Preamble D0 D1 D2 D3 D21 D22 D23 V U CS P LSb MSb Synchronization (type B,M or W) Audio sample, up to 24 bits Status bits 28 information bits
43 Biphase-mark data encoding SPDIF IEC60958 (3/3) 43 1 UI 2 UI 3 UI 4 UI 5 UI 6 UI 7 UI 8 UI 9 UI 10 UI 11 UI 12 UI 13 UI 14 UI Bit Clock Source coding Channel coding (Biphase-Mark) Preambles The preambles are violating the biphase-mark code rules Previous half-bit = 0 1 UI 2 UI 3 UI 4 UI 5 UI 6 UI 7 UI 8 UI Previous half-bit = 1 Previous half-bit = 0 Previous half-bit = 1 Preamble B Missing Transitions!!! Preamble M Previous half-bit = 0 Previous half-bit = 1 Preamble W
44 SPDIF-RX Introduction 44 The SPDIF-RX interface (Sony/Philips Digital InterFace) is able to receive an S/PDIF flow compliant with the IEC and IEC Features List: Possibility to select the audio stream from 1 of the 4 inputs Automatic symbol rate detection Stereo Stream up to 192 khz supported Support Audio IEC (i.e. non encoded stereo stream) Support Audio IEC (i.e. encoded audio stream such as Dolby Digital) Support of DMA interface for: Data stream Control stream Interrupt capabilities
45 SPDIF-RX Block Diagram 45 1 to 2 MHz 192 to 432 MHz To Timer x STM32F7xx RCC PLLSRC HSI HSE 2 to 63 M CMP CMP CMP N PLL PLLSAI N PLLI2S N P Q P Q R P Q R spdif_frame_sync 2,4,6,8 Interrupt Request APB bus DMA_SPDIF_RX_DT DMA_SPDIF_RX_CS SPDIF_CLK Interrupt IF APB Interface DMA IF RX-BUF 32 bits data flow control flow SPDIF-SEQ SPDIF-DEC SPDIF-FE CLK-GEN SPDIF-RX SPDIF_IN1 SPDIF_IN2 SPDIF_IN3 SPDIF_IN4
46 Synchronization 46 The receiver must be able to estimate the time interval between two transitions and defines if it is: A part of a 1 symbol A 0 symbol A long pulse (preamble) MIN_CNT MAX_CNT 1 UI 2 UI 3 UI The receiver estimates two thresholds: THLO and THHI in order to distinguish the transition type. SPDIF Signal 1.5 UI 2.5 UI If the time interval between two transition is: Lower than THLO short transition detected Higher than THHI Long transition detected Between THLO and THHI Medium transition detected The synchronization is performed in two steps: Detection of Short Transition Detection of Medium Transition Detection of Long Transition The COARSE SYNC The FINE SYNC TH LO TH HI
47 Chrom-ART Accelerator (DMA2D)
48 Provides hardware acceleration for graphical operations Graphic oriented 2D DMA Planes blending & pixel format conversion Specific modes for anti aliased fonts Chrom-ART 48 Foreground FG FIFO FG PFC Blender Output PFC Output FIFO Output Background BG FIFO BG PFC Chrom-ART FG : Foreground BG : Background PFC : Pixel Format Converter Application benefits Offload CPU for graphical operation One pixel per cycle calculation Integrated pixel format converter & blender Simple integration through graphical stack
49 Rectangle copy 49 Bitmap 1 Bitmap 1 + Bitmap 2 Frame Buffer offset A B offset = A + B Bitmap 2 + < LCD display > < Memory > Foreground FG FIFO FG PFC Blender Output PFC Output FIFO Output Background BG FIFO BG PFC Chrom-ART
50 Pixel Format Conversion 50 Direct Mode ARGB8888, ARGB4444 or ARGB1555 RGB888 or RGB565 (with alpha in register) Alpha can be replaced or modulate Indirect Mode L8 or L4 and a Color Lock Up Table (CLUT) A8 or A4 and a color register (for fonts) Mixed AL88 or AL44 ARGB ARGB L8 Inde x CLUT A R G B... A R G B ARGB8888 A R G B ARGB8888 RGB565 A8 Register ARGB A R G B A R G B
51 Blending 51 Fully hardware blending process Not Blended Blended Hardware Blending Blend Foreground & Background pixels 1 pixel generated per cycle Native ARGB8888 operation Input data are converted into ARGB8888 by their respective PFC Output data has also its own PFC Foreground FG FIFO FG PFC Blender Output PFC Output FIFO Output Background BG FIFO BG PFC Chrom-ART
52 Font Special Modes 52 Efficient support for anti aliased bitmap fonts Using A8 or A4 coding Only the Alpha channel is stored in the memory The ChromART add a programmed color Aliased Anti-aliased Colored
53 Key features 53 2D DMA with graphical oriented features with 4 operating modes register-to-memory memory-to-memory memory-to-memory with PFC memory-to-memory with PFC and blending User programmable sources and destination addresses on the whole memory User programmable sources and destination size and offset User programmable source and destination color format Up to 11 color formats supported from 4-bit up to 32-bit per pixel with indirect or direct color coding Internal memories for CLUT storage in indirect color mode with automatic loading Alpha value can be modified (source value, fixed value or modulated value)
54 STM32F7 Demonstration 54
55 TouchGFX demo Animation* Set of bitmapped image 2. Draggable image* 3. Vector graphics: the drawing is made by the CPU in an offline buffer, and than composed by the hardware accelerator All the image are located in external flash. Graphic library is managed by FreeRTOS The driver for the F7 is not full optimized. * Use Chrom-ART accelerator
56 Hardware & Data flow TouchGFX demo 56 Cortex-M Chrom-ART Accelerator TFT Controller Bus Matrix Internal Flash Internal SRAM External Memory Controller Creation of an object in a memory device by the Chrom-ART Update/Creation of the frame buffer in the external RAM by the Chrom-ART TFT controller data flow
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