Implementing an Ethernet Solution Using Power Architecture Based Processors: An Overview of the etsec, VeTSEC and dtsec IP Blocks Mark Cheng

Transcription

1 August, 2010 Implementing an Ethernet Solution Using Power Architecture Based Processors: An Overview of the etsec, VeTSEC and dtsec IP Blocks NET-F0562 Mark Cheng NMG, AP PowerPC Applications Engineering Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc.

2 Session Introduction This session focuses on the main differences amongst the first generation Enhanced Triple Speed Ethernet Controller (etsec 1.x), the second generation etsec (etsec 2.x or Virtualization etsec referred to as VeTSEC), and the Datapath Triple Speed Ethernet Controller (dtsec). The importance of these differences can greatly reduce the probability of encountering design issues based on the chosen Ethernet Intellectual Property (IP) block. Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 2

3 Session Objectives After completing this session you will have an understanding of: the main differences amongst the etsec, VeTSEC, and dtsec the main changes for interface selection and clocking the changed memory-mapped register space for the IP blocks the transition of certain features to the Fman/Bman/Qman for dtsec the new capability of interrupt grouping with VeTSEC the main differences for external PHY management Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 3

4 Agenda Supported Layers of the Open System Interconnection (OSI) Model Supported Ethernet Interfaces Feature & Architecture Comparisons Typical etsec features Interface and Clocking Selection Block Diagrams etsec s BDs/Buffers vs- dtsec s Qman/Bman Memory Mapped Registers Error/Interrupt Reporting and Handling Hashing Parsing/Filing - QoS and TOE PHY management Summary Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 4

5 Media Layers Host Layers Supported Layers of the Protocol Stack by FSL Ethernet HW OSI Model Layers 7: Application SMTP, ) 6: Presentation decryption 5: Session communication 4: Transport control end use (FTP, encryption & interhost reliability & flow 3: Network / Internet logical addressing 2: Data Link (MAC) physical addressing Media Access Control (MAC) Ethernet Type II Frame L2 header L3 header (IPv4/IPv6) L4 header (TCP/UDP) Preamble SFD DA SA EthType Payload CRC32 IFG 7 bytes 1 byte 6 bytes 6 bytes 2 bytes bytes 4 bytes 12 bytes 1: Physical (PHY) transmission/reception of bits Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 5

6 Agenda Supported Layers of the Open System Interconnection (OSI) Model Supported Ethernet Interfaces Feature & Architecture Comparisons Typical etsec features Interface and Clocking Selection Block Diagrams etsec s BDs/Buffers vs- dtsec s Qman/Bman Memory Mapped Registers Error/Interrupt Reporting and Handling Hashing Parsing/Filing - QoS and TOE PHY management Summary Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 6

7 Supported Ethernet Physical Interfaces INTERFACE SPEED (Mbps) DUPLEX MII (Media Independent Interface) 10 / 100 Full / Half RMII (Reduced MII) 1 10 / 100 Full / Half SMII (Serial MII) 1 10 / 100 Full / Half GMII (Gigabit MII) 2 10 / 100 / 1000 Full RGMII (Reduced GMII) 1 10 / 100 / 1000 Full / Half SGMII (Serial GMII) 1 10 / 100 / 1000 Full / Half XAUI (TEN Attachment Unit Interface) 10,000 Full TBI (Ten Bit Interface) 1000 Full RTBI (Reduced TBI) 1000 Full FIFO (8/16-bit) GMII Style (Platform Clk/4.2) Encoded (Platform Clk/3.2) Full Controllers CPM-FCC (8280,8560), QE-UEC (8360), FEC (880), TSEC (8560), etsec (8572), dtsec (P4080), 10G (P4080), VeTSEC (P1020) (Not all interfaces supported for each controller. Must refer to each products specific documentation.) 1 Half Duplex -10/100 is supported on this interface via encoding methods because there are no physical COL and CRS signals. 2 10/100 supported via fallback mode to MII Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc.

8 Agenda Supported Layers of the Open System Interconnection (OSI) Model Supported Ethernet Interfaces Feature & Architecture Comparisons Typical etsec features Interface and Clocking Selection Block Diagrams etsec s BDs/Buffers vs- dtsec s Qman/Bman Memory Mapped Registers Error/Interrupt Reporting and Handling Hashing Parsing/Filing - QoS and TOE PHY management Summary Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 8

9 Typical etsec Receive and Transmit Features & Options RX FEATURE Wake-On-LAN (Magic Packet OR Filer Rule) Receive Short Frames Exact Match MAC Addresses (15 available) Lossless Flow Control (RxBDs) Custom L2 Header (Layer 2 Offset) 1588 Timestamping Little Endian Descriptor Mode Snooping /Stashing RxBD and/or Rx Buffer Accesses Packet Alignment Padding Event Notifications via maskable /selectable interrupts Control Frame Accept (Capture in Memory) MIB statistics (auto zeroing option) Rx Interrupt Coalescing Broadcast Frame Reject Promiscuous Mode Length Check (Layer 2) Automatic VLAN TAG Extraction Parsing & Filing (single or multi queue) Extended Group Address Hashing (256 -> 512) IP Header Checksum (Layer 3) TCP/UDP Header Checksum (Layer 4) Preamble Accept ( Capture in Memory) Huge Frame Reception TX FEATURE TxBD modes (POLL or WAIT) Custom L2 Header 1588 Timestamping Little Endian Descriptor Mode Snoop TxBD and/or Tx Buffer Accesses Transmit On Demand for TxBD Ring 0 Event Notifications via maskable /selectable interrupts MIB statistics (auto zeroing option) Automatic VLAN TAG Insertion Tx Interrupt Coalescing IP Header Checksum (Layer 3) TCP/UDP Header Checksum (Layer 4) PADDDING and CRC APPENDING options Interpacket Gap Options Hafl-Duplex Options Transmit Half-Duplex Flow Control Transmit & Receive Pause Frames Transmit Ring Scheduling ( Single polled, priority, & modified weighted roundrobin modes) Custom Preamble Huge Frame Transmission Internal Loopback Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc.

10 Agenda Supported Layers of the Open System Interconnection (OSI) Model Supported Ethernet Interfaces Feature & Architecture Comparisons Typical etsec features Interface and Clocking Selection Block Diagrams etsec s BDs/Buffers vs- dtsec s Qman/Bman Memory Mapped Registers Error/Interrupt Reporting and Handling Hashing Parsing/Filing - QoS and TOE PHY management Summary Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 10

11 Interface & Clocking Selection etsec for 83xx platforms use HRCW etsec for 85xx platforms use POR signals VeTSEC for QorIQ platforms use POR configuration signals dtsec for QorIQ platforms use PBL Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 11

12 Agenda Supported Layers of the Open System Interconnection (OSI) Model Supported Ethernet Interfaces Feature & Architecture Comparisons Typical etsec features Interface and Clocking Selection Block Diagrams etsec s BDs/Buffers vs- dtsec s Qman/Bman Memory Mapped Registers Error/Interrupt Reporting and Handling Hashing Parsing/Filing - QoS and TOE PHY management Summary Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 12

13 MPC8536E Block Diagram MPC8536E Perf Mon Timers Gigabit Ethernet SGMII Enhanced Local Bus Gigabit Ethernet SGMII IEEE 1588 SEC SATA SATA e500 core 32 KB D-Cache OpenPIC USB Host/ Device ULPI 32 KB I-Cache SD / MMC USB Host/ Device ULPI Coherency Module USB Host/ Device ULPI 512 KB L2 Cache 8 Lane SERDES SPI DUART 2x I 2 C Async Queue Power Management PCIe 64-bit DDR2 SDRAM Controller + ECC e500v2 core, built on Power Architecture technology, up to 1.5 GHz 512 KB L2 Cache w/ecc 36-bit physical addressing DP-FPU, SPE System Unit 64-/32-bit DDR2/3 up to 667 MHz data rate w/ecc Integrated security engine Triple USB 2.0 high speed host/device SD/MMC flash interfaces SPI and enhanced local bus Dual SATA Dual 10/100/1000 Ethernet controllers High speed interconnect Triple PCI Express PCI Dual SATA IEEE 1588 Advanced Power Management Controller Nap, Doze, Sleep Deep Sleep 35C) Power off to core and cache Wake on LAN/USB/GPIO/timer/external signal Isolated power planes Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 13

14 etsec 1.x Block Diagram MPC8536 Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc.

15 Dual-Core P1020 Block Diagram Power Manage-ment Security Accel XOR TDM 32KB I- Cache e500 Core 3x GE MAC 32KB D- Cache 256KB L2 Coherency Module System System Bus Bus DMA 32KB I- Cache e500 Core 32KB D- Cache On-Chip Network PCI Express x4 SerDes PCI Express DDR2/DDR3, SDRAM Controller Enhanced Local Bus Perf Mon, DUART, MPIC 2x I2C, Timers USB2.0 SPI SD/MMC 32b 16b Dual e500 Power Architecture core MHz 256KB Frontside L2 cache w/ecc, HW cache coherent 36 bit physical addressing, DP-FPU System Unit 32-bit DDR2/DDR3 with ECC to 800MHz datarate Integrated SEC 3.3 Security Engine Open-PIC Interrupt Controller, Perf Mon, 2x I2C, Timers, 16 GPIO s, DUART 16-bit Enhanced Local Bus supports booting from NAND Flash Two USB 2.0Controllers Host/Device support SPI controller supporting booting from SPI serial Flash SD/MMC card controller supporting booting from Flash cards TDM interface Three 10/100/1000 Ethernet Controllers (etsec) w/ Jumbo Frame support, SGMII interface Enhanced features: Parser/Filer, QOS, IP- Checksum Offload, Lossless Flow Control IEEE1588v2 Support Two PCI Express 1.0a Controllers operating at 2.5GHz Power Management Process & Package 45nm SOI 689-pin TePBGAII, 31x31mm Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 15

16 VeTSEC (etsec 2.x) Block Diagram P1020 Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc.

17 VeTSEC main differences Memory Mapped Registers have changed slightly Addition of hashing logic to aid in received packet distribution among queues/cores Improved control and status register access times New Interrupt Grouping (coalescing on a per queue basis) Each RX and TX physical queue pair individually assigned to any core Provides line rate transmission in multi-queue scheduling configurations (Priority or MWRR) Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 17

18 QorIQ DPAA components P KB Backside Power Architecture e500-mc Core L2 Cache 32KB 32KB D-Cache I-Cache 1024KB Frontside L3 Cache 1024KB Frontside L3 Cache 64-bit DDR-2 / 3 Memory Controller 64-bit DDR-2 / 3 Memory Controller eopenpic PreBoot Loader Security Monitor Internal BootROM PAMU PAMU PAMU CoreNet Coherency Fabric PAMU PAMU Peripheral Access Mgmt Unit Power Mgmt SD/MMC SPI elbc Security 4.0 Queue Mgr. Frame Manager Parse, Classify, Distribute Frame Manager Parse, Classify, Distribute RapidIO Message Unit (RMU) 2x DMA Real Time Debug Watchpoint Cross Trigger 2x DUART 4x I 2C 2x USB 2.0/ULPI Test Port/ SAP Pattern Match Engine 2.0 Buffer Mgr. Buffer 1GE 10GE 1GE 1GE 1GE Buffer 1GE 10GE 1GE 1GE 1GE PCIe PCIe SRIO PCIe SRIO Perf Monitor Aurora CoreNet Trace Clocks/Reset GPIO CCSR 18-Lane 5GHz SERDES Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc.

19 dtsec Block Diagram P4080 Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc.

20 dtsec Main differences Parser/Filer functions moved to another block Essentially just a MAC Used in new DPAA Reduced size in FIFOs Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 20

21 Agenda Supported Layers of the Open System Interconnection (OSI) Model Supported Ethernet Interfaces Feature & Architecture Comparisons Typical etsec features Interface and Clocking Selection Block Diagrams etsec s BDs/Buffers vs- dtsec s Qman/Bman Memory Mapped Registers Error/Interrupt Reporting and Handling Hashing Parsing/Filing - QoS and TOE PHY management Summary Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 21

22 etsec and VeTSEC Buffer Descriptors etsec Memory Mapped Registers TxBD Table Base RxBD Table Base Memory TxBD Ring Buffer RxBD Ring Buffer Status/Control Data Length Buffer Pointer Status/Control Data Length Buffer Pointer TxBD RxBD Similar to other PowerQUICC Family Ethernet Controllers BD rings must be contiguous, minimum of 9 BDs per ring for etsec Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 22

23 DPAA Versus Buffer Descriptor rings Core D$ I$ DPAA infrastructure replaces descriptor rings: Queueing is split from buffer management and from the passing of frames to/from cores Queues can be shared by multiple cores Core D$ I$ Core D$ I$ Queue Manager Core D$ I$ Buffer Manager Core D$ I$ Eth Data reception is not throttled by how fast software can service ring entries Data can be stashed into cache just before it is processed Network I/O Eth Eth Eth Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 23

24 2) DPAA Infrastructure: BMan Buffer Manager (BMan) supports: 64 pools of buffer pointers All buffers in a pool are expected to have like characteristics BMan places no restrictions on these characteristics Hardware (and software) acquire and release of buffer pointers from/to pools BMan is primarily intended to reduce the buffer management load on SW Pool depletion thresholds for pool replenishment and lossless flow control All thresholds have hysteresis Buffer Manager (BMan) List Engines Software Portals To Cores Internal stockpile Buffer Descriptors CoreNet Hardware portals Buffer Descriptors PME SEC FMan FMan Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 24

25 Frame Manager Ingress (RX) Timestamp incoming packet (IEEE 1588 representative) Acquisition of right sized buffer based upon Ethernet packet size L2 CRC validation, IPv4 header checksum and TCP/UDP checksum validation L2/L3/L4 protocol parsing (hard and soft examination sequences) Classification based queue distribution Exact match to queue Configurable flow hash to queue Color marked policing decision (RFC2698, RFC4115) Direct hardware enqueue to QMan queue defined via classification Egress (TX) Direct hardware dequeue from QMan IPv4, TCP/UDP checksum update Transmit rate based metering per port Buffer constituting the packet are returned Frame Frame Classifier 10GE QMI BMI MACs DMA IC Shared Memory Buffer Scheduler 1GE 1GE 1GE 1GE Parser Key Gen Policer Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 25

26 Frame Manager Flow Chart MAC BMI Parser Unicast DA match Multicast/Broadcast filter CRC check Transfer Frame to Memory Bulk one s complement checksum Parse/identify common L2-L4 protocols Branch to soft examine sequence for custom protocols Populate parse results for software use Update checksums calculations Policer KeyGen Coarse Classify KeyGen Dual rate tri-color mark frame according to classification Generate FQ ID via programmable mechanism Perform exact match directed queue identification Identify course classification routine from parse results BMI QMI De-allocate buffers, discard packet on drop decision Enqueue description of packet to Queue Manager Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 26

27 Life of an Ingress Packet FMAN receives packets BMI allocates internal buffers retrieves data from MAC acquires a buffer from BMan uses DMA to store data in it Parse+classify+keygen select a queue and policer profile Policer colors and optionally discards frame QMan applies active queue management and enqueues frame Frame is enqueued to one of a pool of cores DDR PKT DDR L2 Cache L2 Cache Power Architecture L2 Cache Power Core Architecture L2 Cache Power Core Architecture D-CachePower I-Cache Core Architecture D-Cache I-Cache Core D-Cache I-Cache D-Cache I-Cache Policer DMA Classifier Frame Manager (FMan) Memory BMI 10GE GE GE GE GE PKT To Memory QMI Keygen (Distribution) Parser DEQ ENQ FD Return Buf Ptr Request Buffer Queue Manager D D D WQ7 WQ6 WQ5 WQ4 WQ3 WQ2 WQ1 WQ0 Buffer Manager Dequeue Enqueue WRED QMI Policer Keygen Classifier Parser BMI MAC Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 27

28 FMan/QMan Ingress Packet Processing 16M Queues (Frame Queues) References to Packet 3 QMan 4 Frontside Cache DDR SDRAM Classification driven enqueue distribution Packet Data written to main memory subsystem Packet Data Stored in H/W managed buffers FMan Packets in process Buffer Acquisition Request Buffer Reference 2 Bman MURAM 10G 1G 1G 1G 1G 1 Packets Arriving Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 28

29 FMan/QMan Ingress Packet Processing 16M Queues (Frame Queues) References to Packet 3 QMan 4 Frontside Cache DDR SDRAM Classification driven enqueue distribution Packet Data written to main memory subsystem Packet Data Stored in H/W managed buffers FMan Packets in process Buffer Acquisition Request Buffer Reference 2 Bman MURAM 10G 1G 1G 1G 1G 1 Packets Arriving Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 29

30 Agenda Supported Layers of the Open System Interconnection (OSI) Model Supported Ethernet Interfaces Feature & Architecture Comparisons Typical etsec features Interface and Clocking Selection Block Diagrams etsec s BDs/Buffers vs- dtsec s Qman/Bman Memory Mapped Registers Error/Interrupt Reporting and Handling Hashing Parsing/Filing - QoS and TOE PHY management Summary Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 30

31 etsec 2.x etsec 1.x etsec Updates - Memory mapping 4k Block 4k Block Group 0 P2020 P1020 Core 0 Core 1 New etsec features introduced to P1 devices P2 and earlier devices have etsec 1.x P1 devices have etsec 2.x etsec 1.x has one common 4k block of common registers which can be used by any core In etsec 2.x, the Ethernet traffic can be categorized in two groups 4k Block for MDIO Core 0 Core 1 Separate 4k block of status & control registers are for each groups. These 4k blocks can be associated to each of the cores 4k Block Group 1 Another 4k block, common to both the core, is available for management Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 31

32 VeTSEC Memory Map Offset & Register Changes Be mindful of the memory map differences when porting code to VeTSEC from etsec 1.x etsec1 MDIO starts at 0x2_4000 address offset etsec2 MDIO starts at 0x2_5000 address offset etsec3 MDIO starts at 0x2_6000 address offset etsec1 group 0 starts at 0xB_0000 address offset etsec2 group 0 starts at 0xB_1000 address offset etsec3 group 0 starts at 0xB_2000 address offset etsec1 group 1 starts at 0xB_4000 address offset etsec2 group 1 starts at 0xB_5000 address offset etsec3 group 1 starts at 0xB_6000 address offset Interrupt Steering Register Group n (ISRGn) - Any bit set in any ISRGn enables multiple-group mode, including per ring interrupt coalescing and MWRR transmit scheduling of ring 0 Group Error Mapping Register (EMAPG) - The error mapping register allows the user to route non- BSY errors to a particular group error interrupt TXICn/RXICn Coalescing control per physical queue IGADDRn/GADDRn Individual/Group Hash and Groups Hash IEVENTGn/IMASKGn Group Interrupt Event and Mask RSTATn/TSTATn Receive/Transmit Status Register Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 32

33 Agenda Supported Layers of the Open System Interconnection (OSI) Model Supported Ethernet Interfaces Feature & Architecture Comparisons Typical etsec features Interface and Clocking Selection Block Diagrams etsec s BDs/Buffers vs- dtsec s Qman/Bman Memory Mapped Registers Error/Interrupt Reporting and Handling Hashing Parsing/Filing - QoS and TOE PHY management Summary Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 33

34 Event and Interrupt Routing for 8 Physical Queues - etsec DDR etsec1 BD Rings 0 thru 7 Tx BD Ring #0 IEVENT RSTAT TSTAT etsec1 Rx Error etsec1 core0 PIC etsec2 BD Rings 0 thru 7 Tx BD Ring #0 IEVENT RSTAT TSTAT etsec2 Rx Error etsec2 core1 Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 34

35 Event and Interrupt Routing for 8 Physical Queues (A) - VeTSEC DDR etsec1 BD Rings 0 thru 3 Tx BD #0 Group 0 IEVENTGn Rx Error 0 BD #4 Group 1 RSTATn TSTATn etsec1 Tx Rx Error 1 etsec1 core0 etsec1 BD Rings 4 thru 7 etsec2 BD Rings 0 thru 3 PIC BD #0 Group 0 IEVENTGn Tx Rx Error 0 BD #4 Group 1 RSTATn TSTATn etsec2 Tx Rx Error 1 etsec2 core1 etsec2 BD Rings 4 thru 7 Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 35

36 Event and Interrupt Routing for 8 Physical Queues (B) - VeTSEC DDR etsec1 BD Rings 0 thru 3 Tx BD #0 Group 0 IEVENTGn Rx Error 0 BD #4 Group 1 RSTATn TSTATn etsec1 Tx Rx Error 1 etsec1 core0 etsec1 BD Rings 4 thru 7 etsec2 BD Rings 0 thru 3 PIC BD #0 Group 0 IEVENTGn Tx Rx Error 0 BD #4 Group 1 RSTATn TSTATn etsec2 Tx Rx Error 1 etsec2 core1 etsec2 BD Rings 4 thru 7 Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 36

37 Agenda Supported Layers of the Open System Interconnection (OSI) Model Supported Ethernet Interfaces Feature & Architecture Comparisons Typical etsec features Interface and Clocking Selection Block Diagrams etsec s BDs/Buffers vs- dtsec s Qman/Bman Memory Mapped Registers Error/Interrupt Reporting and Handling Hashing Parsing/Filing - QoS and TOE PHY management Summary Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 37

38 vtsec Hashing Logic Features Hashing function optimized to provide better worst-case flow distribution than CRCbased hashing algorithms Hash function integrated into existing receive filer Produces a 16-bit hash value Identified by one or more hash rules via direct index or lookup table Identifies a queue (1 of 8) Passed on in RxFCB for software Used as a key into software flow table Hashes together one or more of the following user-selected fields Layer 2: MAC source and destination address 802.1p priority and VLAN id Ethertype Layer 3: IP source and destination address IP TOS/Traffic Class field Next Header protocol Layer 4: TCP/UDP source and destination port numbers Any 4 bytes, including Ethernet preamble, taken from first 64 bytes of L2, L3, or L4 PDU Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc.

39 vtsec RX Frame Control Block (RXFCB) Information VLAN tag recognized, see control word IP header found, see Next Header protocol ID IPv6 header type TCP or UDP header found IPv4 header checksum checked TCP/UDP checksum checked IPv4 header checksum error TCP/UDP checksum error Parse error Packet matched a General Purpose Interrupt file rule Offset +0 VLN IP IP6 TUP CIP CTU EIP ETU PERR GPF Offset +2 RQ PRO Offset +4 HASH RESULT Offset +6 VLCTL Receive Queue Index 802.1Q VLAN Control Word Next Header Protocol Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc.

40 Agenda Supported Layers of the Open System Interconnection (OSI) Model Supported Ethernet Interfaces Feature & Architecture Comparisons Typical etsec features Interface and Clocking Selection Block Diagrams etsec s BDs/Buffers vs- dtsec s Qman/Bman Memory Mapped Registers Error/Interrupt Reporting and Handling Hashing Parsing/Filing - QoS and TOE PHY management Summary Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 40

41 extracted header fields Quality of Service Starts at the etsec Receive Inbound frame parsed and headers extracted. Filer table searched to locate RxBD ring to DMA. Frame rejection supported in rule set. 256-entry filing table field value TCP port # queue #3 priority select queue # Transmit Stack queues frames on 1 of 8 TxBD rings. WRR scheduler allocates MAC bandwidth according to 8-bit queue weights. Priority-based queuing supported. 8 TxBD Queues Frame Parser L2 to L4 10/100/1000 Ethernet MAC Rx FIFO data address BD cache DMA Weighted Round-robin scheduler (1 with priority override) 10/100/1000 Ethernet MAC Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. Slide 41

42 checksum TCP/IP Offload Balances Performance Transmit TCP and UDP checksums of frames up to 9.6kB at DMA rates. IPv4 header checksum and IPv6 header skip. Receive TOE at Gigabit Ethernet or 2.5 Gbps FIFO rates. Frame parser peels encapsulated VLAN, MPLS, PPPoE, LLC, IPv4, IPv6, IP over IP, TCP and UDP headers. Optional word re-alignment of IP header. data payload DMA Add 2kB Rx FIFO: Data + TOE status 8/16bit FIFO Interface 10/100/1000 Ethernet MAC 10kB Tx FIFO: Data w/headers Layers 2 4 Rx Frame Parser fields to QoS filer data checksum TCP/IP Offload Engine CkSm Add CkSm Tx per cycle Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. Slide 42

43 DPAA Parser Determine protocol correctness IP/TCP/UDP checksum Version number check Length field check Frame too short, long Give protocol stack indication to KeyGen and/or software Support for hard and soft parse algorithms Soft parse can detect 3 proprietary/user defined fields and extract offset to Parser Result Soft parse can do classification by e.g. address comparison instructions (limited functionality) Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 43

44 Agenda Supported Layers of the Open System Interconnection (OSI) Model Supported Ethernet Interfaces Feature & Architecture Comparisons Typical etsec features Interface and Clocking Selection Block Diagrams etsec s BDs/Buffers vs- dtsec s Qman/Bman Memory Mapped Registers Error/Interrupt Reporting and Handling Hashing Parsing/Filing - QoS and TOE PHY management Summary Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 44

45 MII Mgmt Interface TSEC 1 MAC TSEC 1 TBI TSEC 2 MAC TSEC 2 TBI MDC/MDIO CPM-FEC MII GMII, TBI GMII, TBI MDC/MDIO PHY 1 PHY 2 PHY X Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc.

46 Agenda Supported Layers of the Open System Interconnection (OSI) Model Supported Ethernet Interfaces Feature & Architecture Comparisons Typical etsec features Interface and Clocking Selection Block Diagrams etsec s BDs/Buffers vs- dtsec s Qman/Bman Memory Mapped Registers Error/Interrupt Reporting and Handling Hashing Parsing/Filing - QoS and TOE PHY management Summary Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 46

47 Session Summary Many options are available for an Ethernet solution There are some distinct differences amongst the IP blocks The newer IP blocks have increased performance Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 47

48 For Further Information Visit Request help at 8536 for etsec P1021 for VeTSEC P4080 for dtsec Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 48

49 Session Closing You should understand The main differences amongst the etsec, VeTSEC, and dtsec The advantage of the new grouping for performance The advantage of the Fman/Bman/Qman for performance How an Ethernet packet is handled by the different IP blocks Where to find more information Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 49

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