$1 1. Cloud Wireless Enterprise. Smart Energy. Transportation. 50B Connected Nodes by 2020* $ Past Today Future

Transcription

1 August 2013

2 1T 100B 50B Connected Nodes by 2020* Computers People Everything $ B Cloud Wireless Enterprise 1B 10M $1 1 Past Today Future *Source Ericsson Factory Automation Smart Energy Transportation 2

3 Innovate Integrate Accelerate Scalable Roadmap Datapath Acceleration 64-bit Processing Core Agnostic Software Enabled Best Price/Performance/ per Watt I/O Flexibility Integrated Switch Altivec Processing Time-to-Market Advantage Software Development Kits Turn-Key Reference Solutions Embedded Board Solutions Third Party Ecosystem Full Development Environment 3

4 Product Overview Portfolio Target Applications QorIQ LS Series Core-agnostic approach to hardware Freescale s unrivaled networking expertise with Arm s expansive ecosystem Networking Industrial Automation Smart Grid QorIQ T Series 1-24 cores, 64-bit, AltiVec technology 6 family members in 2013 Data Center Aerospace and Defense High-End Networking QorIQ Qonverge Platform 1-6 heterogeneous cores 5 family members in 2013 Aerospace and Defense Industrial Wireless Access QorIQ P Series 1-8 cores, data path acceleration, security and pattern matching, hardwareassisted hypervisor 25 family members in production Networking Aerospace and Defense Factory Automation PowerQUICC General purpose MPU 75 family members in production Industrial Smart Grid Networking 4

5 B4xxx Macro & C-RAN users LTE 1.8 Gbps, 3 sectors 8 x 8 MiMO WCDMA - 6 Cells P4080 MSC8156 MSC8157/8 B4860 Pin Compatible Families Metro Users LTE 600Mbps, 2 sectors 4 x 4 MiMO WCDMA 4 cells P3041 MSC8156 MSC8157 B4420 B3xxx Pico/Enterprise Users LTE 300Mbps, 1 sector 2 x 4 MiMO WCDMA 2 cells P2020 MSC8154 BSC9132 B2xxx Home/SMB 8 16 Users LTE 150Mbps, 1 sector WCDMA 1 cell 2 x 2 MiMO BSC9131 P B1xxx 1Q 2Q 3Q 4Q 2Q 3Q 4Q Available Now Production 1Q 1Q 2Q 3Q 4Q Production Execution Planning Proposal Sample 5

6 P1010 P1014 P1024, P1015 P1020, P1011 P2020 P1022 P1023 P1025, P1016 P1021, P1012 P2010 P1013 P1017 e500v2 e500v2 1 to 2 e500v2 1 to 2 e500v2 1 to 2 e500v2 1 to 2 e500v2 1 to 2 e500v2 CPU Up to 800 MHz Up to 800 MHz Up to 667 MHz Up to 800 MHz Up to 1200 MHz Up to 1200 MHz Up to 800 MHz 32K I/D 32K I/D 32K I/D 32K I/D 32K I/D 32K I/D 32K I/D L2 Cache 256 KB 256 KB 256 KB 256 KB 512 KB 256 KB 256 KB DDR I/F DDR3/3L DDR3/3L DDR3 DDR2/3 DDR2/3 DDR2/3 DDR3/3L Type/Width 32/16-bit 16-bit 32-bit 32-bit 32/64-bit 32/64-bit 32-bit 10/100/1000 Ethernet (with IEEE 1588v2) 3 w/(2) SGMII 2 w/(2) SGMII 3 w/(2) SGMII 3 w/(2) SGMII 3 w/(2) SGMII 2 w/(2) SGMII 2 w/(2) SGMII TDM Yes Yes Yes Yes - Yes - A UTOPIA - - In P1025/16 In P1021/ SERDES 6 lanes 4 lanes 4 lanes 4 lanes 4 lanes 6 lanes 4 lanes PCI-Exp 1.0a 2 controllers 2 controllers 2 controllers 2 controllers 3 controllers 3 controllers 3 controllers srio controllers controllers 2 controllers 2 controllers SATA 1.5 or 3 Gbaud 1.5 or 3 Gbaud or 3 Gbaud - USB2.0 1 w/ PHY 1 w/ PHY Memory Card SD/MMC SD/MMC SD/MMC SD/MMC SD/MMC SD/MMC - Other Interfaces SPI, 2xI 2 C, SPI, 2xI 2 C, SPI, SPI, SPI, 2xI 2 C, SPI, SPI, DUART, 2xeCAN DUART 2xI 2 C, DUART 2xI 2 C, DUART DUART 2xI 2 C, DUART 2xI 2 C, DUART Accelerators SEC4.0 w/ DPAA, trusted boot SEC4.0 SEC3.3 SEC3.3 SEC3.1 SEC3.2 SEC 4.2 Package 425 TePBGA 19x19mm 0.8mm 561 TePBGA 23x23mm, 0.8mm 689 TePBGAII 31x31mm 689 TePBGAII 31x31mm 457 TePBGA 19x19mm, 0.8mm Pin-compatible Pin-compatible Pin-compatible Pin-compatible Pin-compatible Audio I 2 S Audio Video LCD (DIU) RAID XOR 6

7 CPU Cache P5040/P5021 P5020/P5010 P4080 P4040 P2040 P3041 Quad and Dual e5500 to 2200 MHz L1: 32K I/D L2: 512 KB BS L3: 2MB FS Dual and Single e5500 to 2000 MHz L1: 32K I/D L2: 512 KB BS L3: 1MB Octal core e500mc to 1500 MHz L1: 32K I/D L2: 128 KB BS L3: 2 MB -FS Quad core e500mc to 1500 MHz L1: 32K I/D L2: 128 KB BS L3: 2 MB -FS Quad e500mc to 1200 MHz L1: 32K I/D CoreNet Cache: 1 MB -FS Quad e500mc to 1500 MHz L1: 32K I/D L2: 128 KB BS L3: 1 MB -FS 10/100/1000 Ethernet (with IEEE 1588v2) 10x GbE, 2 10 GbE 5x GbE, 1 10 GbE (2) Frame managers w/ 4 x1 GbE (SGMII) & 1 10 GbE (XAUI) (2) Frame managers w/ 4 x 1 GbE (SGMII) & 1 10 GbE (XAUI) 5x GbE 4x GbE, 1 10 GbE PCI-Exp X3 gen 2.0 x4 gen 2.0 X3 gen 2.0 X3 gen 2.0 X3 gen 2.0 X3 gen 2.0 srio USB with PHY - SerDes Memory Other interfaces 20 5 GHz DUAL DDR3/3L to 1.6 GHz SPI, 4x I 2 C, 2x DUART, CoreNet SATA 18 5 GHz DDR2/3 to 1.3 GHz SPI, 2xI 2 C, 2x DUART, CoreNet SATA 18 5 GHz DUAL DDR2/3 to 1.3 GHz SPI, 4x I 2 C, 4x UART, CoreNet 18 5 GHz DUAL DDR2/3 to 1.3 GHz SPI, 4x I 2 C, 4x UART, CoreNet 10 5 GHz DDR2/3 to GHz SPI, 2xI 2 C, 4x UART, CoreNet, SATA 12 5 GHz DDR2/3 to 1.3 GHz SPI, 2xI 2 C, 4x UART, CoreNet, SATA Accelerators Data path: SEC 5.2, RAID 5/6 Data path: SEC 4.0, RAID 5/6, PME Data path: SEC 4.0, 10 Gbps IP forwarding, PME Data path: SEC 4.0, 10 Gbps IP forwarding, PME Data path: SEC 4.0, 5 Gbps IP forwarding, PME Package 1295-pin package 1295-pin package 1295 FCPBGA 1295 FCPBGA 783-pin package Data path: SEC 4.0, 5 Gbps IP forwarding, PME 1295 FCPBGA (pin compatible P4040) 7

8 UPDATE P1020, P1011 P1021, P1012 P2020 P2010 T1020 T1022 T1040 T to 2 e500 1 to 2 e500 2 e e e e5500 CPU Up to Up to 800MHz 1200MHz MHz MHz MHz MHz 32K I/D 32K I/D 32K I/D 32K I/D 32K I/D 32K I/D L2 Cache 256KB 512KB 256KB/Core 256KB/Core 256KB/Core 256KB/Core Platform Cache 256KB 256KB 256KB 256KB DDR2/3 DDR2/3 DDR3L/4 DDR3L/4 DDR3L/4 DDR3L/4 DDR I/F Type/Width 16/32-bit, 800MHz 32/64-bit, 800MHz 32/64-bit, 1333MHz 32/64-bit, 1333MHz 32/64-bit, 1333MHz 32/64-bit, 1333MHz 10/100/1000 Ethernet (with IEEE1588v2) 3 x 8-Port GE Switch & 3 x 8-Port GE Switch & 3 x 3 x 10/100/ /100/ /100/ x 10/100/ /100/ x 10/100/1000 TDM Yes - Yes Yes Yes Yes QUICC Engine In P1021/12 - TDM and HDLC TDM and HDLC TDM and HDLC TDM and HDLC SERDES 4 lanes 4 lanes 8 lanes 8 lanes 8 lanes 8 lanes PCI-Exp 2 (Gen-1) 3 (Gen-1) 4 (Gen-2) 4 (Gen-2) 4 (Gen-2) 4 (Gen-2) DIU - - Yes Yes Yes Yes SATA 2 controller 2 controller 2 controller 2 controller or 3Gbaud 1.5 or 3Gbaud 1.5 or 3Gbaud 1.5 or 3Gbaud USB with PHY 2 with PHY 2 with PHY 2 with PHY Memory Card SD/MMC SD/MMC SD/MMC SD/MMC SD/MMC SD/MMC Accelerators Power Management SEC3.3 <5.0W SEC3.1 <8.0W DPAA, PME SEC5.x with Trust Architecture Packet Lossles Deepsleep DPAA, PME SEC5.x with Trust Architecture Packet Lossles Deepsleep DPAA, PME SEC5.x with Trust Architecture Packet Lossles Deepsleep DPAA, PME SEC5.x with Trust Architecture Packet Lossles Deepsleep Package Pin Compatible 8

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10 Closer to Customer Solution Customer Differentiation Reference Solutions Embedded Board Solutions Silicon Application Software Middleware Commercial OS Hardware Development Tools Operating Systems Software Development Tools Application Stacks Middleware Scalable SOC SDOS Processor Expert 10

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12 First 64-bit embedded processor with an integrated GbE switch Reduces system cost, design complexity and power One of the industry s most scalable, pincompatible family of devices Performance scalability with a common architecture Energy efficiency and low power Designed to be compliant to European Code of Conduct, and EnergyStar energy consumption standards Ideal for low- to mid-range networking and industrial connectivity applications QorIQ Processors: Accelerating the Network s IQ 12

13 Performance - Eight Virtual Cores up to 1.8GHz T2081 NEW - Quad-Core up to 1.4GHz - Integrated GbE Switch - Quad-Core up to 1.4GHz T1040 NEW - Dual-Core up to 1.4GHz T1020 NEW T1022 NEW - Dual-Core up to 1.4GHz - Integrated GbE Switch T1042 Scale from dual, quad to eight virtual cores with QorIQ T1/T2 devices Power 13

14 New Improvement of Dual thread Frequency Number DMIPs per Thread X Efficiency X X of Cores 2.4x 1.3x 1.5x IPC Improvements Multithreading Frequency Improvements Multicore 64-bit architecture AltiVec Technology: 240 GFLOPS 1TB physical address Accelerate Hypervisor performance with LRAT Dual Thread Each with separate front end, branch unit and LSU Larger amount of onboard cache per core New process and e6500 core allowing increased frequency Up to 24 virtual cores Large 2 MB shared L2 cache within a cluster of 1 to 4 cores CoreNet Cache-coherent fabric with multiple clusters to scale from 1 to 8 clusters Virtualization Up to 4x Performance Improvement over Previous Generation 14

15 Freescale Multicore Platform L2 Cache e500mc Core Power Architecture Cores L2 Cache e500mc Core L2 Cache e500mc Core L2 Cache e500mc Core SCALE for Performance and Power The Right Cores Processing / watt Vector acceleration Advanced threading The Right SoC Infrastructure The Right Balance Memories On-Demand Acceleration Pattern Matching Crypto Security Table Lookups Data Path Acceleration Resource Management Architecture Decompression / Compression CoreNet Fabric CoreNet Fabric QUICC Engine System Functions Real-Time Debug Advanced Trace Trace /64-bit KB 512 DDR2/3/3L KB 512 KB Connectivity Ethernet etsec Platform Cache Up 64-bit to 1024 DDR3/3L/4 KB L3 PCI Express RapidIO SATA USB Enhanced Virtualization Support Hypervisor with three tier privilege modes SoC memory Interrupts I/O virtualization Advanced Process Technology Multicore Debug Advanced Trace Trust Architecture Customer Driven Features 15

16 Necessary feature if a system is to operate as multiple independent subsystems Application consolidation Customer consolidation Secure applications (e.g. policy modules, rights management) Untrusted software (third party; Sandbox application) System is divided into logical partitions (a virtually independent sub-system) A sub-system each with its own operating system Resources of the system are apportioned among logical partitions Processors, storage, devices, I/O, event mechanisms, etc. Typically, individual operating systems want to own their resources Expect to map the resources into own address space (OWN = ACCESS) Expect to initialize them Expect to have unrestricted access Interpartition protection Subsystems must be protected from each other Computational state Error: Required Performance: Best effort 16

17 Enterprise Routers/Switches Industrial Computing and Networking U Security Appliances The T1/T2 communications processors are architected to provide maximum performance per watt Highest performance CPU cores within a power envelope Advanced integration with multilayer Gigabit Ethernet switch to reduce system cost and design complexity Offload engines encryption/decryption for high performance security Deep packet inspection offload engine enabling U services Data path acceleration architecture (DPAA) for QoS and balanced networking performance Virtualization to support customers and 3 rd party software Small form factor, fanless and convection-cooled designs 17

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19 QorIQ Qonverge Base Station-on-Chip SoC Series Advanced core and acceleration technologies, highlybalanced architectures for baseband processing integration, advanced process technologies users (28 nm) users (45 nm) users (28 nm) Freescale delivering industry s first complete SoC portfolio from home femto to multi-sector macro base stations Software compatibility across different devices Layer-1 and transport software stacks for small cell solutions to further expedite time to market users (45 nm) Adopted by Industry leading base station OEMs Broad portfolio from Femto to Macro with on-time, on-specification release track record Common architecture and software tool sets including CodeWarrior Development Suite Software and tools ecosystem catering for Tier-1 wireless OEMs and broad market customers Rich third-party ecosystem for tools, operating system and application software 19

20 A comprehensive, commercial grade L1, L2, L3 and Transport Software solution integrated and tested on BSC9131/2 and scalable to B-Series QorIQ Qonverge platforms LTE-FDD/TDD and WCDMA (HSPA+) L1 software (licensed by Freescale) L2/L3 software for LTE-FDD/TDD and WCDMA (licensed by Aricent and CCPU/RadiSys) Transport software, including IPsec, QoS backhaul, etc., through Freescale s VortiQa software (licensed by Freescale) Development tools and operating system software (available through Freescale and ecosystem partners) 20

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22 UPDATE Enterprise AP-WLAN Security Appliance Wireless Media Gateway Multiservice Gateway (Media & Voice Gateway) Industrial Gateway DLNA VOD Video-on-Demand NVR Network Video Recorder (Video Surveillance) Networked Smart Gateway Smart Energy Gateway NAS Network Attached Storage 22

23 Key Benefits Kernel Kernel User User UPDATE The next-generation framework for networking applications development Networking Dev (Linux OS) Signaling, Mgmt, Apps VortiQa PSP Framework (Linux OS) Signaling, Mgmt, Apps, TCP Packet processing apps Network services (IP) Packet processing apps VortiQa PSP SW (Network services, Session mgr, Timers, Mem mgr, Stats) Base Support Package (BSP) QorIQ Multicore processor hardware Base Support Package, TCP/IP QorIQ Multicore processor hardware Ease of development Ease of maintenance Copyright protection 23

24 Common Occasional For more partner options, visit freescale.com/partners 2012 Freescale Semiconductor, Inc. SW Dev Tools Runtime Software HW and SW Engineering Services Training Processor Expert Application Specific Software and Solution Integrators (SSI) Middleware Embedded Board Solutions IDH/ODM Training Partners HW Dev Tools Operating Systems Semiconductors/Companion Modules Qonverge Layerscape P series T series Communities 24

25 Qonverge UPDATE for SW Dev Dev Tools Tools Customer Application HW & SW Engineering Services Optima Application Specific FSL VortiQa Mocana One Convergence Bit Defender SSI Training MULTI Middleware Stacks APIs Protocols Codecs Libraries SBC / SOM Emerson Curtiss Wright IDH ODM DELTA NETWORKS LANNER Common Occasional Training Partners ARNEWSH PHOENIX MICRO AC6 Sourcery CodeBench Operating Systems Eurotech Momentics Linux FSL Mercury Computer Advantech GDA Technologies ARICENT TATA ELXSI Processor/Microcontroller/DSP Kontron Interface Masters More Standard More Custom IDE: Integrated Development Environment BDM: Background Debug Module SBC: Single Board Computers SOM: System On Modules IDH: Independent Design House ODM Original Design Manufacturer SSI: Software & Solution Integrators 25

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27 Demands on the network infrastructure continue to grow exponentially 27

28 Evolution of Data Path Acceleration Architecture (DPAA) leveraging HW & SW Architecture Accelerating the Network s IQ Core-agnostic approach to hardware (Power Architecture or ARM) with independent processing of data + control for exceptional efficiency Enables ease of use with common architecture and software, driving a diversified product portfolio Extreme programming flexibility and scale for real-time, soft control over network 28

29 System Interfaces System Control System Visualization (Debug/Tuning) UPDATE GPP Layer APP Layer EPI Layer General-Purpose Processing Layer (GPPL) CPU(s) Caches Mem. Cont. Core-agnostic (Power Architecture or ARM cores) Consistent APIs/libraries with tools abstract hardware changes Single framework for programming for GPPL/APPL Accelerated Packet Processing Layer (APPL) Queue Manager Buffer Manager AIOP Security Engine (SEC) Packet Express Buffer Pattern Match Engine (PME) Data Compress Engine (DCE) Capable of fully autonomous offload Synchronous run to completion model True programmability Bounded determinism with graceful degradation Express Packet I/O Layer (EPIL) Ethernet Interlaken WRIOP 1/10/40/100G SERDES RapidIO PCI-Express Deterministic performance Scalability from 1G-100G Packetized I/O between all interfaces supporting L2 switching Performance insights for real-time network adjustments 29

30 Multicore Infrastructure Network Interface Module Accelerators Autonomous Processing Datapath Programming Model DPAA Queue Manager (Qman), Buffer Manager (Bman) Frame Manager SEC, PME, DCE Limited (Fman) Microcode Layerscape Architecture Queue Manager (Qman), Buffer Manager (Bman) Wire Rate IO Processing (WRIOP) SEC, PME, DCE, Timer Manager (Tman), PCI- Express Manager (PEXMan) Full Advanced IO Processing (AIOP) Open Program Model (C/C++) Core Support Power Power & ARM System Interconnect ECM & CoreNet All 30

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