QorIQ P4080 Software Development Kit
|
|
|
- Morris Long
- 6 years ago
- Views:
Transcription
1 July 2009 QorIQ P4080 Software Development Kit Kelly Johnson Applications Engineering service names are the property of their respective owners. Freescale Semiconductor, Inc
2 QorIQ P4080 Software Development Kit The Software Bundle Hypervisor w/ partition manager U-Boot Linux kernel BMan, QMan, FMan, SEC, PME, SRIO, PCIE drivers Linux applications Standard Open Source Applications FSL Specific Applications Frame Manager Config Tool PME Config Tool Light Weight Executive (LWE) LWE applications LTIB build system GNU tool chain Simulator Functional model - Virtutech Performance model Analysis & visualization Hybrid API CodeWarrior PA10 Multicore debugger Multicore trace and performance analysis tools CodeWarrior Run-Control and Trace Probe service names are the property of their respective owners. Freescale Semiconductor, Inc
3 QorIQ P4080 Software Development Kit (SDK) SDK is delivered in a Linux Target Image Builder Framework (LTIB) LTIB is a tools framework Common to all PowerQUICC and QorIQ development systems Manages, configures, extends and builds Linux software elements Installs P4080 development tools, including GNU tool suite service names are the property of their respective owners. Freescale Semiconductor, Inc
4 QorIQ P4080 Multicore Programming Paradigm Support a variety of customer use-cases Multiple operating systems utilized across cores on a single Proprietary, 3 rd party and Open Source multicore operating systems Symmetric Multi-Processing (SMP) and Asymmetric Multi-Processing (AMP), often running concurrently Often bare-metal, or engineered light-os, used on forwarding/data plane cores Freescale has developed a reference development platform: Freescale Embedded Hypervisor Freescale boot standards, including u-boot Leverage open boot protocol and API standards (e.g. Power.org ) Freescale Light Weight Executive (LWE) for run to completion data plane processing Demonstrate performance and provide reference example for customers Services Forwarding/ Data Plane Control Plane Linux Linux Light Weight Executive (Light RTOS) 3 rd Party AMP AMP SMP L2 Cache L2 Cache L2 Cache L2 Cache L2 Cache L2 Cache L2 Cache L2 Cache Power Architecture Core Power Architecture Core Power Architecture Core Power Architecture Core Power Architecture Core Power Architecture Core Power Architecture Core Power Architecture Core D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache service names are the property of their respective owners. Freescale Semiconductor, Inc
5 Control Plane cores Linux User Space Data Plane cores LWE Reference Apps Linux Kernel Linux Networking Drivers Light Weight Executive FMan Driver BMan/QMan Driver Hypervisor Bootloader (u-boot) FMan MAC/Port Library Platform trust (secure boot) Execution targets (boards, simulators) Tools Software CodeWarrior GNU Tools service names are the property of their respective owners. Freescale Semiconductor, Inc
6 Freescale Embedded Hypervisor service names are the property of their respective owners. Freescale Semiconductor, Inc
7 Freescale Embedded Hypervisor A small hypervisor for embedded systems, featuring : Static partitioning of hardware resources into logical partitions CPUs Memory IO s Partitions protection and isolation MMU PAMU Sharing Virtualization Configuration is fixed until a reconfigure and system reboot, relying on the approach defined in the Power.org epapr specification. service names are the property of their respective owners. Freescale Semiconductor, Inc
8 guest operating system Hypervisor Interfaces instruction emulation hypercalls direct I/O virtual core (e500vcpu) runtime boot Hypervisor gdb stub console vterm hardware service names are the property of their respective owners. Freescale Semiconductor, Inc
9 Hypervisor Interfaces : Boot Services guest operating system instruction emulation hypercalls direct I/O virtual core (e500vcpu) runtime boot Hypervisor gdb stub console vterm hardware service names are the property of their respective owners. Freescale Semiconductor, Inc
10 Hypervisor Interfaces : Boot Services guest operating system instruction emulation hypercalls direct I/O virtual core (e500vcpu) Boot runtime Specified by the Power.org epapr standard which describes: entry point conditions gdb stub boot Hypervisor # of CPU cores Memory (amount and location) Devices console (including virtual s) vterm hardware service names are the property of their respective owners. Freescale Semiconductor, Inc
11 Hypervisor Interfaces : Virtual CPU guest operating system instruction emulation hypercalls direct I/O virtual core (e500vcpu) runtime boot Hypervisor gdb stub console vterm hardware service names are the property of their respective owners. Freescale Semiconductor, Inc
12 Hypervisor Interfaces : Virtual CPU guest operating system instruction emulation hypercalls direct I/O Virtual virtual CPU core runtime 100% compatible with e500mc core (e500vcpu) (minus the hypervisor extensions) supervisor mode software runs unchanged Very similar to an e500v2. Hypervisor Key areas: MMU management Privileged SPRs gdb stub console boot vterm hardware service names are the property of their respective owners. Freescale Semiconductor, Inc
13 Hypervisor Interfaces : Runtime Services guest operating system instruction emulation hypercalls direct I/O virtual core (e500vcpu) runtime boot Hypervisor gdb stub console vterm hardware service names are the property of their respective owners. Freescale Semiconductor, Inc
14 Hypervisor Interfaces : Runtime Services guest operating system instruction emulation hypercalls direct I/O virtual core (e500vcpu) gdb stub Runtime runtime via hypercalls : a special version of the sc instruction (LEVEL=1) Key areas: Interrupt controller Hypervisor hardware boot vterm (character I/O console, debug) Partition management Other shared console platform resources vterm(gpio, timers, perfmon,etc) service names are the property of their respective owners. Freescale Semiconductor, Inc
15 Hypervisor Interfaces : gdb stub guest operating system instruction emulation hypercalls direct I/O virtual core (e500vcpu) runtime boot Hypervisor gdb stub console vterm hardware service names are the property of their respective owners. Freescale Semiconductor, Inc
16 Hypervisor Interfaces : gdb stub guest operating system instruction emulation hypercalls direct I/O virtual core (e500vcpu) runtime gdb stub provides interface to debug guest operating systems uses e500mc core debug resources Hypervisor provides run control and access to virtual CPU state uses gdb standard stub gdb interface console protocol boot vterm hardware service names are the property of their respective owners. Freescale Semiconductor, Inc
17 Hypervisor Interfaces : Debug Console guest operating system instruction emulation hypercalls direct I/O virtual core (e500vcpu) runtime boot Hypervisor gdb stub console vterm hardware service names are the property of their respective owners. Freescale Semiconductor, Inc
18 Hypervisor Interfaces : Debug Console guest operating system instruction emulation hypercalls direct I/O virtual core (e500vcpu) runtime boot gdb stub Hypervisor Debug console Simple command line for console status of hypervisor vterm hardware service names are the property of their respective owners. Freescale Semiconductor, Inc
19 Hypervisor Interfaces : vterm guest operating system instruction emulation hypercalls direct I/O virtual core (e500vcpu) runtime boot Hypervisor gdb stub console vterm hardware service names are the property of their respective owners. Freescale Semiconductor, Inc
20 guest operating system Hypervisor Interfaces : vterm instruction emulation hypercalls direct I/O virtual core (e500vcpu) runtime boot gdb stub Hypervisor vterm Output for byte channels Allows debug consoles for each vterm partition hardware service names are the property of their respective owners. Freescale Semiconductor, Inc
21 Linux Kernel and Linux Drivers Linux kernel (Beta 1.1) supports both SMP and non-smp same kernel binary images can run with and without hypervisor Linux Ethernet driver that makes use of Frame Manager, Buffer Manager and Queue Manager Frame Manager Driver Buffer Manager/Queue Manager driver SEC 4.0 Driver Support for 10G Ethernet ports Support for Frame Manager Configuration Tool service names are the property of their respective owners. Freescale Semiconductor, Inc
22 Light Weight Executive service names are the property of their respective owners. Freescale Semiconductor, Inc
23 Light Weight Executive Concept Set of C-libraries needed to support data plane applications (C++ planned) Run-to-completion software model Processes do not pre-empt each other - the process must run to completion before other processes get a chance to run, as scheduled by the QMan (= implicit work scheduler) IRQs are supported, software responsibility to postpone actual processing using SWI or implement proper protection/sharing mechanism Dependency on Hypervisor Device Trees for LWE configuration Runs in supervisor state Hypercalls used to access Hypervisor functionality Ingress Channel Egress Channel FQ FQ FQ FQ priority FQ Function FQ FQ FQ FQ priority service names are the property of their respective owners. Freescale Semiconductor, Inc
24 Light Weight Executive Scope Application (Hello World, Simple queuing, Bridging, IP and IPSec forwarding) SWI std func Net/ Frame PME SEC IPC Hypervisor Timer Perf. mon FDT read BMan portal Driver QMan Portal driver libc e500mc core DPAA portals service names are the property of their respective owners. Freescale Semiconductor, Inc
25 LWE Hypervisor interaction Boot partman tool for partition start / stop / reset and image download Device address passing Access control MMU and PAMU (peripheral access control) Runtime Peripheral virtualization (e.g. UART, MPIC, GPIO) partition partition partition running App App Linux LWE LWE Hypervisor Multicore System Hardware Shared Cache I/O Interrupt Controller CPU CPU CPU CPU Memory Memory Memory I/O I/O I/O I/O Memory service names are the property of their respective owners. Freescale Semiconductor, Inc
26 LWE Hypervisor interaction Boot partman tool for partition start / stop / reset and image download Device address passing Access control MMU and PAMU (peripheral access control) Runtime Peripheral virtualization (e.g. UART, MPIC, GPIO) partition partition partition running App App Linux stopped App LWE App LWE Hypervisor Multicore System Hardware Shared Cache I/O Interrupt Controller CPU CPU CPU CPU Memory Memory Memory I/O I/O I/O I/O Memory service names are the property of their respective owners. Freescale Semiconductor, Inc
27 LWE Hypervisor interaction Boot partman tool for partition start / stop / reset and image download Device address passing Access control MMU and PAMU (peripheral access control) Runtime Peripheral virtualization (e.g. UART, MPIC, GPIO) partition partition partition running App App Linux stopped App LWE stopped App App LWE Hypervisor Multicore System Hardware Shared Cache I/O Interrupt Controller CPU CPU CPU CPU Memory Memory Memory I/O I/O I/O I/O Memory service names are the property of their respective owners. Freescale Semiconductor, Inc
28 LWE Hypervisor interaction Boot partman tool for partition start / stop / reset and image download Device address passing Access control MMU and PAMU (peripheral access control) Runtime Peripheral virtualization (e.g. UART, MPIC, GPIO) partition partition partition running App App Linux running App LWE running App App LWE Hypervisor Multicore System Hardware Shared Cache I/O Interrupt Controller CPU CPU CPU CPU Memory Memory Memory I/O I/O I/O I/O Memory service names are the property of their respective owners. Freescale Semiconductor, Inc
29 QorIQ P4080 Simics Hybrid Virtual Platform service names are the property of their respective owners. Freescale Semiconductor, Inc
30 Simulation Terminology Primer: A Functional Model A functional model presents an architecturally correct view of the core and system to executing software A functional model is instruction accurate and contains an instruction set simulator (ISS) plus models of all system s A functional model contains no timing or cycle-accurate behaviors CPU0 Memory Map CPUn Memory A functional model can consume application binaries I/O, DMA Data Path Typical speed of a functional model is in the hundreds of millions of instructions per second Network service names are the property of their respective owners. Freescale Semiconductor, Inc
31 Simulation Terminology Primer: A Performance Model A performance model is a model that simulates the exact functionality and performance of a hardware CPU0 Exe Units/BIU CPU0 Exe Units/BIU Performance models are referred to as cycle-accurate or timing models Performance models typically consume application binaries or traces Coherency Module DDRC0 DDRC1 Depending on level of detail and complexity of model part, simulator speed can be between hundreds to hundreds of thousands of instructions per second I/O, DMA Network Data Path Acceleration service names are the property of their respective owners. Freescale Semiconductor, Inc
32 Performance vs. Functional Model Differences Performance model models coherency Out of order execution and speculative misbehavior can be caught Performance issues related to locks and semaphores can be identified and fixed Performance model models caches and cache operations L1 instruction and data, backside L2, and platform (L3) Models cache locking, flushing, and stashing Performance Model provides increased accuracy with respect to deadlocks and race conditions Asynchronous clock domains are modeled bringing controlled and reproducible indeterminism to an application service names are the property of their respective owners. Freescale Semiconductor, Inc
33 Simics P4080 Hybrid Model Definition A hybrid model is a simulator that combines both a functional model with a performance model within the same environment. Users switch from the functional model to the performance model to analyze specific areas of interest in the application lifetime: Workload Phase Functional data for debug Init Boot Warm-up Steady-state Problem Area Functional Model Performance Model CP CP t 0 Performance data for debug t n service names are the property of their respective owners. Freescale Semiconductor, Inc
34 Timing + Function P4080 Modeling Scope Function Only Not modeled Power Architecture 128KB e500-mc Core Backside L2 Cache 32KB 32KB D-Cache I-Cache 1024KB Frontside L3 Cache 1024KB Frontside L3 Cache 64-bit DDR-2 / 3 Memory Controller 64-bit DDR-2 / 3 Memory Controller eopenpic Pre Boot Loader Security Monitor Internal BootROM PAMU CoreNet Coherency Fabric PAMU PAMU PAMU PAMU Peripheral Access Mgmt Unit Power Mgmt SD/MMC SPI 2x DUART 4x I 2C 2x USB 2.0/ULPI elbc Test Port/ SAP Security 4.0 Pattern Match Engine 2.0 Queue Mgr. Buffer Mgr. Frame Manager Frame Manager RapidIO Message Unit (RMU) 2x DMA PCIe PCIe SRIO PCIe SRIO Real Time Debug Watchpoint Cross Trigger Perf CoreNet Monitor Trace Aurora Clocks/Reset GPIO CCSR 18-Lane 5GHz SERDES service names are the property of their respective owners. Freescale Semiconductor, Inc
35 CodeWarrior service names are the property of their respective owners. Freescale Semiconductor, Inc
36 QorIQ P4080 Dedicated Debug Logic Using Nexus QorIQ 4080 Processor Power Architecture 128 KB e500-mc Core Backside L2 Cache 32 KB 32 KB D-Cache I-Cache 1024 KB Frontside L3 Cache 1024 KB Frontside L3 Cache 64-bit DDR-2 / 3 Memory Controller 64-bit DDR-2 / 3 Memory Controller eopenpic PreBoot Loader Security Monitor Internal BootROM CoreNet Coherency Fabric PAMU PAMU PAMU PAMU PAMU Peripheral Access Mgmt Unit Power Mgmt SD/MMC SPI elbiu Security 4.0 Queue Mgr. Frame Manager Parse, Classify, Distribute Frame Manager Parse, Classify, Distribute SRIO Message Unit DMA Real Time Debug Watchpoint Cross Trigger DUART 2x I 2C 2x USB 2.0/ULPI Test Port/ SAP Pattern Match Engine 2.0 Buffer Mgr. 10GE Buffer 1GE 1GE 1GE 1GE 10GE Buffer 1GE 1GE 1GE 1GE PCIe PCIe SRIO PCIe srio Perf CoreNet Monitor Trace Aurora Clocks/Reset GPIO CCSR 18-Lane 5 GHz SerDes service names are the property of their respective owners. Freescale Semiconductor, Inc
37 QorIQ P4080 / P4040 Debug Architecture Overview Instruction Debug Jamming Instruction Registers Debug Jamming Instruction Registers Debug MBIST Jamming Instruction Monitor Registers Debug MBIST Jamming Monitor Registers MBIST CPU Monitor Nexus MBIST CPU Monitor Nexus CPU Nexus CPU Nexus SkyBlue Interface SkyBlue Interface SkyBlue Interface SkyBlue Interface Events SBX Event Processing Unit (EPU) Select Unit OCEAN Debug Interface (OCDI) Sequence Unit Perfmon Counters Action Unit DDR Debug Interface (DDDI) Triggers JTAG S A P CoreNet Coherency Manager (CCM) NXC T A P Data Path (QM/FM) CoreNet Trace (CNDC) DataPath Trace (DPDC) NTC Nexus Port Controller (NPC) Control/ Arbitration NTC 16K Trace Buffer Aurora Interface Aurora Link Layer (NAL) HBDP (SerDeS) Run control is performed via Aurora or JTAG Nexus Port Controller (NPC) manages trace buffer and Nexus trace port Event Processing Unit (EPU) monitors events and generates cross-triggers CoreNet Debug Client, DataPath Debug Client, DDR Client monitor peripherals and memory service names are the property of their respective owners. Freescale Semiconductor, Inc
38 CodeWarrior : Core-based Software Performance Analysis Trace-Based Performance Monitors real time capture and presentation of core function profile service names are the property of their respective owners. Freescale Semiconductor, Inc
39 Example: CodeWarrior DDR Profiling & Performance Analysis service names are the property of their respective owners. Freescale Semiconductor, Inc
40 Q&A Thank you for attending this presentation. We ll now take a few moments for the audience s questions and then we ll begin the question and answer session. service names are the property of their respective owners. Freescale Semiconductor, Inc
41
Performance Analysis with Hybrid Simulation
6 th November, 2008 Performance Analysis with Hybrid Simulation PN111 Matthew Liong System and Application Engineer, NMG owners. Freescale Semiconductor, Inc. 2008. r2 Overview Hybrid Modeling Overview
On-Chip Debugging of Multicore Systems
Nov 1, 2008 On-Chip Debugging of Multicore Systems PN115 Jeffrey Ho AP Technical Marketing, Networking Systems Division of Freescale Semiconductor, Inc. All other product or service names are the property
An Introduction to the QorIQ Data Path Acceleration Architecture (DPAA) AN129
July 14, 2009 An Introduction to the QorIQ Data Path Acceleration Architecture (DPAA) AN129 David Lapp Senior System Architect What is the Datapath Acceleration Architecture (DPAA)? The QorIQ DPAA is a
Leveraging Data Plane Acceleration Techniques on the QorIQ P4080 Processor
June 2010 Leveraging Data Plane Acceleration Techniques on the QorIQ P4080 Processor For High-Performance Network Security Applications (v1.0) John Rekesh Software Architect, Software Products Division
AN133: SEC 4.0: Datapath Security Accelerator on the QorIQ P4080 Processor
July 2009 AN133: SEC 4.0: Datapath Security Accelerator on the QorIQ P4080 Processor Geoff Waters NMG Systems Engineering - Security Agenda Freescale security technology evolution Motivations for a datapath
VortiQa Software with Unified Threat Management for Service Provider Equipment
July 2009 VortiQa Software with Unified Threat Management for Service Provider Equipment Performance Optimization on QorIQ P4080 Multicore Processor Bharat Mota Director of Engineering, Software Products
Frame Manager (FMan) Internals
Frame Manager (FMan) Internals AN130 David Lapp Senior System Architect This session is an introduction to Frame Manager Internals Introduction It is intended to be stand alone but it is helpful to have
QorIQ Based Multicore LTE Layer 2 Software
July 2009 QorIQ Based Multicore LTE Layer 2 Software Keith Shields AC CELE R ATIO N CORENET FABRIC Freescale LTE System Enablement Overview: Software; Devices; AMC boards CONTROL RF PA RF RF PA PA RF Small
Differences Between P4080 Rev. 2 and P4080 Rev. 3
Freescale Semiconductor Application Note Document Number: AN4584 Rev. 1, 08/2014 Differences Between P4080 Rev. 2 and P4080 Rev. 3 About this document This document describes the differences between P4080
Multicore Software Technology Roadmap
November, 2010 Multicore Software Technology Roadmap Jacques Landry and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners.
EUF-NET-T0862. QorIQ P Software Architecture for the P4080 Development System. Peter Van Ackeren Sr. Software FAE Freescale Semiconductor EMEA
May 11, 2010 QorIQ P4080 - Software Architecture for the P4080 Development System EUF-NET-T0862 Peter Van Ackeren Sr. Software FAE Freescale Semiconductor EMEA SDK Release 2.1 Beta for the P4080DS Development
Eclipse-Based CodeWarrior Debugger
July 14-16, 2009 Eclipse-Based CodeWarrior Debugger QorIQ Multicore Linux Kernel Debug Bogdan Irimia CodeWarrior Software Engineer Tool used to develop software running on Freescale Power Architecture
EDGE COMPUTING & IOT MAKING IT SECURE AND MANAGEABLE FRANCK ROUX MARKETING MANAGER, NXP JUNE PUBLIC
EDGE COMPUTING & IOT MAKING IT SECURE AND MANAGEABLE FRANCK ROUX MARKETING MANAGER, NXP JUNE 6 2018 PUBLIC PUBLIC 2 Key concerns with IoT.. PUBLIC 3 Why Edge Computing? CLOUD Too far away Expensive connectivity
Freescale Roadmap for Communications Processors Built on Power Architecture Technology
August, 2010 Freescale Roadmap for Communications Processors Built on Power Architecture Technology NET-F0425 Jeffrey Ho Technical Marketing Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy
P3041 QorIQ Communications Processor Product Brief
Product Brief Document Number: P3041PB Rev. 0, 11/2011 P3041 QorIQ Communications Processor Product Brief This product brief provides an overview of the P3041 QorIQ communications processor features as
RAD55xx Platform SoC. Dean Saridakis, Richard Berger, Joseph Marshall *** *** *** *** *** *** *** photo courtesy of NASA
1 RAD55xx Platform SoC Dean Saridakis, Richard Berger, Joseph Marshall *** *** *** *** *** *** *** photo courtesy of NASA 2 Agenda RAD55xx Platform SoC Introduction Processor Core / RAD750 Processor Heritage
QorIQ P4080 Communications Processor Product Brief
Freescale Semiconductor Product Brief Document Number: P4080PB Rev. 1, 09/2008 QorIQ P4080 Communications Processor Product Brief The QorIQ P4080 Communications Processor combines eight Power Architecture
TechDays property of their respective owners Freescale Semiconductor, Inc..
TM TechDays 2013 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobilegt, PowerQUICC, QorIQ, StarCore and Symphony are trademarks
Weibo? Please use hashtag #FTF2011# Freescale on Kaixin Tag yourself in photos and upload your own!
30 Aug. 2011 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, t he Energy Efficient Solutions logo, mobilegt, PowerQUICC, QorIQ, StarCore and Symphony are trademarks
SMB Appliance. SOHO Appliance
August 2011 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, t he Energy Efficient Solutions logo, mobilegt, PowerQUICC, QorIQ, StarCore and Symphony are trademarks
PC Touchpad Appliance
October 2013 Networks strained by use of smarter, bandwidth-hungry devices need: Multicore platforms performing more intelligently and securely Low-power, low-cost, easy-to-use equipment Scalable platform
KVM on Embedded Power Architecture Platforms
KVM on Embedded Power Architecture Platforms Stuart Yoder Software Architect, Freescale Semiconductor Agenda Background Freescale / Networking Embedded Systems Use Cases KVM on Embedded Power New requirements
Freescale QorIQ Program Overview
August, 2009 Freescale QorIQ Program Overview Multicore processing view Jeffrey Ho Technical Marketing service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009. We
Enabling the Migration to an All-IP Network
July, 2009 Enabling the Migration to an All-IP Network Colin Cureton Product Marketer Enable next generation broadband networking systems to deliver a seamless user experience via processors offering:
FTF-ENT-F0585. August 2011
FTF-ENT-F0585 August 2011 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, t he Energy Efficient Solutions logo, mobilegt, PowerQUICC, QorIQ, StarCore and Symphony
QorIQ P4080 Multicore Processor Software Initialization Steps for the Data Path Acceleration Architecture (DPAA)
June, 2010 QorIQ P4080 Multicore Processor Software Initialization Steps for the Data Path Acceleration Architecture (DPAA) FTF-NET-F0681 Brandon Ade and Srikanth Srinivasan NMG Systems and Applications
Freescale s definition:
October 2013 Freescale s definition: A Trustworthy system is a system which does what its stakeholders expect it to do, resisting attackers with both remote and physical access, else it fails safe. Freescale
High-Performance, Highly Secure Networking for Industrial and IoT Applications
High-Performance, Highly Secure Networking for Industrial and IoT Applications Table of Contents 2 Introduction 2 Communication Accelerators 3 Enterprise Network Lineage Features 5 Example applications
QorIQ P4080 Processor Pre-Boot Loader Image Tool
June 23, 2010 QorIQ P4080 Processor Pre-Boot Loader Image Tool FTF-NET-F0402 Kelley Oswalt Applications Engineer Objective Introduce the PBL Image Tool and describe it s features and use in assisting the
Performance Analysis on SMP and Non-SMP for Multicore Technology
June, 2010 Performance Analysis on SMP and Non-SMP for Multicore Technology FTF-ENT-F0697 TieFei Zang Principle Software Engineer Introduction Multicore in communication processor technology Dual cores
Simplifying the Development and Debug of 8572-Based SMP Embedded Systems. Wind River Workbench Development Tools
Simplifying the Development and Debug of 8572-Based SMP Embedded Systems Wind River Workbench Development Tools Agenda Introducing multicore systems Debugging challenges of multicore systems Development
The QorIQ portfolio The markets we address and the trends there
November 2013 Freescale in Networking The QorIQ portfolio The markets we address and the trends there Product portfolio update what is new Portfolio review: C29x High Performance Tier Mid Performance Tier
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C- Ware, the Energy Efficient Solutions logo, Kinetis,
May 2013 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C- Ware, the Energy Efficient Solutions logo, Kinetis, mobilegt, PEG, PowerQUICC, Processor Expert, QorIQ,
PCD Graphs & PCD Processing Elements. Advanced Data Flows & DPAA Domains
November 2013 As developers of Networking solutions over Multiple-core devices, having a suitable software base is crucial to your success and competiveness. Attending this session, will help you gain
P2040 QorIQ implementation
Course objectives: This course has 6 main objectives: Describing the hardware implementation, particularly the boot sequence and the DDR3 controller Understanding the features of the internal interconnect
Challenges for Next Generation Networking AMP Series
21 June 2011 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, t he Energy Efficient Solutions logo, mobilegt, PowerQUICC, QorIQ, StarCore and Symphony are trademarks
Reference Manual , 01/2016. CodeWarrior Development Studio for Power Architecture Processors Targeting Manual
NXP Semiconductors Document Number: CWPADBGUG Reference Manual 10.5.1, 01/2016 CodeWarrior Development Studio for Power Architecture Processors Targeting Manual Contents Contents Chapter 1 Introduction...11
Implementing an Ethernet Solution Using Power Architecture Based Processors: An Overview of the etsec, VeTSEC and dtsec IP Blocks Mark Cheng
August, 2010 Implementing an Ethernet Solution Using Power Architecture Based Processors: An Overview of the etsec, VeTSEC and dtsec IP Blocks NET-F0562 Mark Cheng NMG, AP PowerPC Applications Engineering
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C- Ware, the Energy Efficient Solutions logo, Kinetis,
April 2013 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C- Ware, the Energy Efficient Solutions logo, Kinetis, mobilegt, PEG, PowerQUICC, Processor Expert, QorIQ,
Migrating Unicore Network Packet Processing Applications to Multicore
August, 2009 Migrating Unicore Network Packet Processing Applications to Multicore Challenges and Techniques (1.0) Wilson Lo Architect, Network Software Division, NMG service names are the property of
An Intelligent NIC Design Xin Song
2nd International Conference on Advances in Mechanical Engineering and Industrial Informatics (AMEII 2016) An Intelligent NIC Design Xin Song School of Electronic and Information Engineering Tianjin Vocational
EMC2. Prototyping and Benchmarking of PikeOS-based and XTRATUM-based systems on LEON4x4
EMC2 Prototyping and Benchmarking of PikeOS-based and XTRATUM-based systems on LEON4x4 Introduction Multi-core architectures will be adopted in the next generations of avionics and aerospace systems. Integrated
FCQ2 - P2020 QorIQ implementation
Formation P2020 QorIQ implementation: This course covers NXP QorIQ P2010 and P2020 - Processeurs PowerPC: NXP Power CPUs FCQ2 - P2020 QorIQ implementation This course covers NXP QorIQ P2010 and P2020 Objectives
RESTRUCTURING DPDK DEVICE-DRIVER FRAMEWORK
RESTRUCTURING DPDK DEVICE-DRIVER FRAMEWORK Expanding DPDK to non-pci, non-virtual devices SHREYANSH JAIN, HEMANT AGRAWAL NXP 21/OCT/2016 About Me... An engineer with NXP s Digital Networking Software team
WS_CCESSH5-OUT-v1.01.doc Page 1 of 7
Course Name: Course Code: Course Description: System Development with CrossCore Embedded Studio (CCES) and the ADI ADSP- SC5xx/215xx SHARC Processor Family WS_CCESSH5 This is a practical and interactive
Effectively describe, at a high level, NetComm Software for DPAA-based devices
Aug. 31 st 2011 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, t he Energy Efficient Solutions logo, mobilegt, PowerQUICC, QorIQ, StarCore and Symphony are trademarks
QorIQ multicore communications platform software introduction Boot loader bring-up Linux bring-up Q&A
Aug. 2011 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, t he Energy Efficient Solutions logo, mobilegt, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of
FPQ6 - MPC8313E implementation
Formation MPC8313E implementation: This course covers PowerQUICC II Pro MPC8313 - Processeurs PowerPC: NXP Power CPUs FPQ6 - MPC8313E implementation This course covers PowerQUICC II Pro MPC8313 Objectives
FPQ9 - MPC8360E implementation
Training MPC8360E implementation: This course covers PowerQUICC II Pro MPC8360E - PowerPC processors: NXP Power CPUs FPQ9 - MPC8360E implementation This course covers PowerQUICC II Pro MPC8360E Objectives
30-Mar What's New in SDK V Highlights
30-Mar-2017 NXP Digital Networking is pleased to announce the release of QorIQ Linux SDK v2.0-1703 supporting our QorIQ family of processors. This release is one of a series of releases based on SDK v2.0
Application Brief. QorIQ P2040/P2041, P3 and P5 Series. High-performance multicore processors. freescale.com/qoriq
QorIQ P2040/P2041, P3 and P5 Series High-performance multicore processors Title here Secondary Title here QorIQ Communications Platform: Scalable Processing Performance Ideal for networking infrastructure,
Himanshu Thapar and Kelly Johnson NPD Applications Engineering
TM Himanshu Thapar and Kelly Johnson NPD Applications Engineering June 2012 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions
Early Software Development Through Emulation for a Complex SoC
Early Software Development Through Emulation for a Complex SoC FTF-NET-F0204 Raghav U. Nayak Senior Validation Engineer A P R. 2 0 1 4 TM External Use Session Objectives After completing this session you
Evaluating Multicore Architectures for Application in High Assurance Systems
Evaluating Multicore Architectures for Application in High Assurance Systems Ryan Bradetich, Paul Oman, Jim Alves-Foss, and Theora Rice Center for Secure and Dependable Systems University of Idaho Contact:
RA3 - Cortex-A15 implementation
Formation Cortex-A15 implementation: This course covers Cortex-A15 high-end ARM CPU - Processeurs ARM: ARM Cores RA3 - Cortex-A15 implementation This course covers Cortex-A15 high-end ARM CPU OBJECTIVES
A Deep Dive on the QorIQ T1040 L2 Switch
A Deep Dive on the QorIQ T1040 L2 Switch FTF-NET-F0007 Suchit Lepcha Application Engineering Manager F e b. 2 1. 2 0 1 4 TM External Use Agenda Overview Switch Functions Software Conclusion External Use
Software Driven Verification at SoC Level. Perspec System Verifier Overview
Software Driven Verification at SoC Level Perspec System Verifier Overview June 2015 IP to SoC hardware/software integration and verification flows Cadence methodology and focus Applications (Basic to
ARM CORTEX-R52. Target Audience: Engineers and technicians who develop SoCs and systems based on the ARM Cortex-R52 architecture.
ARM CORTEX-R52 Course Family: ARMv8-R Cortex-R CPU Target Audience: Engineers and technicians who develop SoCs and systems based on the ARM Cortex-R52 architecture. Duration: 4 days Prerequisites and related
$1 1. Cloud Wireless Enterprise. Smart Energy. Transportation. 50B Connected Nodes by 2020* $ Past Today Future
August 2013 1T 100B 50B Connected Nodes by 2020* Computers People Everything $100 1 2 3 1.0 2.0 3.0 10B Cloud Wireless Enterprise 1B 10M $1 1 Past Today Future 1990 2000 2010 2020 1 2 3 *Source Ericsson
Software Datapath Acceleration for Stateless Packet Processing
June 22, 2010 Software Datapath Acceleration for Stateless Packet Processing FTF-NET-F0817 Ravi Malhotra Software Architect Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions
Tile Processor (TILEPro64)
Tile Processor Case Study of Contemporary Multicore Fall 2010 Agarwal 6.173 1 Tile Processor (TILEPro64) Performance # of cores On-chip cache (MB) Cache coherency Operations (16/32-bit BOPS) On chip bandwidth
WS_CCESBF7-OUT-v1.00.doc Page 1 of 8
Course Name: Course Code: Course Description: System Development with CrossCore Embedded Studio (CCES) and the ADSP-BF70x Blackfin Processor Family WS_CCESBF7 This is a practical and interactive course
Real Safe Times in the Jailhouse Hypervisor Unrestricted Siemens AG All rights reserved
Siemens Corporate Technology Real Safe Times in the Jailhouse Hypervisor Real Safe Times in the Jailhouse Hypervisor Agenda Jailhouse introduction Safe isolation Architecture support Jailhouse application
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
Jeffrey Ho March 2013 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C- Ware, the Energy Efficient Solutions logo, Kinetis, mobilegt, PEG, PowerQUICC, Processor
NetComm Software Errata
NetComm Software Errata Release GA 4.7 Document ID: NCSWErrata Check out our web page for all NetComm Software related updates, at: http://www.freescale.com/netcommsw Freescale Semiconductor, Inc., 2013.
Securing Intelligent Industrial and Networking Devices
Securing Intelligent Industrial and Networking Devices Cost-optimized QorIQ P1010 and P1014 microprocessors Franck Roux Network Processor Channel Marketing Freescale, the Freescale logo, AltiVec, C-5,
QorIQ and QorIQ Qonverge Multicore SoCs and PowerQUICC Processors
QorIQ and QorIQ Qonverge Multicore SoCs and QUICC Processors Selector Guide Designed for Performance. Built to Connect. freescale.com/qoriq Selector Guide Processor Selector Guide QorIQ Number Speed (MHz)
Getting Started with FreeRTOS BSP for i.mx 7Dual
Freescale Semiconductor, Inc. Document Number: FRTOS7DGSUG User s Guide Rev. 0, 08/2015 Getting Started with FreeRTOS BSP for i.mx 7Dual 1 Overview The FreeRTOS BSP for i.mx 7Dual is a Software Development
Migrating from the MPC8360E to the MPC8569E PowerQUICC Processor
August 28, 2009 Migrating from the MPC8360E to the MPC8569E PowerQUICC Processor Overview of the hardware and software differences and concerns (Version 1) Johnson Leung Application Engineering MPC8569E
T4240RDB Quick Start Guide
Freescale Semiconductor Document Number: T4240RDBQS Quick Start Rev 0, 11/2013 T4240RDB Quick Start Guide 1 Introduction The QorIQ T4240 reference system (T4240RDB) is a flexible system that supports the
System Impact of Distributed Multicore Systems December 5th 2012
System Impact of Distributed Multicore Systems December 5th 2012 Software Systems Division & Data Systems Division Final Presentation Days Mathieu Patte (Astrium Satellites) Alfons Crespo (UPV) Outline
Track Three Building a Rich UI Based Dual Display Video Player with the Freescale i.mx53 using LinuxLink
Track Three Building a Rich UI Based Dual Display Video Player with the Freescale i.mx53 using LinuxLink Session 1 How to capture your initial Linux based product requirements and quickly build a custom
Simulation Based Analysis and Debug of Heterogeneous Platforms
Simulation Based Analysis and Debug of Heterogeneous Platforms Design Automation Conference, Session 60 4 June 2014 Simon Davidmann, Imperas Page 1 Agenda Programming on heterogeneous platforms Hardware-based
CodeWarrior U-Boot Debugging
Freescale Semiconductor Application Note Document Number: AN4876 CodeWarrior U-Boot Debugging 1. Introduction This document describes the steps required for U-Boot debugging using the CodeWarrior IDE.
QorIQ T4 Family of Processors. Our highest performance processor family. freescale.com
of Processors Our highest performance processor family freescale.com Application Brochure QorIQ Communications Platform: Scalable Processing Performance Overview The QorIQ communications processors portfolio
Software Quality is Directly Proportional to Simulation Speed
Software Quality is Directly Proportional to Simulation Speed CDNLive! 11 March 2014 Larry Lapides Page 1 Software Quality is Directly Proportional to Test Speed Intuitively obvious (so my presentation
«Real Time Embedded systems» Multi Masters Systems
«Real Time Embedded systems» Multi Masters Systems rene.beuchat@epfl.ch LAP/ISIM/IC/EPFL Chargé de cours rene.beuchat@hesge.ch LSN/hepia Prof. HES 1 Multi Master on Chip On a System On Chip, Master can
Design with the QorIQ T2081 and T1040 Processor Families
Design with the QorIQ T2081 and T1040 Processor Families FTF-NET-F0140 Chun Chang Application Engineer A P R. 2 0 1 4 TM External Use Session Introduction This session is relevant for customers designing
QorIQ Advanced Multiprocessing (AMP) Series
October 2013 T4240/T4160 (28nm) NEW QorIQ Advanced Multiprocessing (AMP) Series Multithreaded cores, advanced fixed function processing integration, power-saving techniques, virtualization, 28nm process
AN147 An Overview of the PowerQUICC III MPC8572
July, 2009 AN147 An Overview of the PowerQUICC III MPC8572 Toby Foster Product Marketing service names are the property of their respective owners. Freescale Semiconductor, Inc. 2009. Agenda Positioning
Performance Optimization for an ARM Cortex-A53 System Using Software Workloads and Cycle Accurate Models. Jason Andrews
Performance Optimization for an ARM Cortex-A53 System Using Software Workloads and Cycle Accurate Models Jason Andrews Agenda System Performance Analysis IP Configuration System Creation Methodology: Create,
QCVS Frame Distributor Wizard User Guide
NXP Semiconductors Document Number: QCVS_FDW_User_Guide User's Guide Rev. 4.x, 02/2017 QCVS Frame Distributor Wizard User Guide Contents Contents Chapter 1 Frame Distributor Wizard...3 1.1 Introduction...
CodeWarrior Development Studio for Power Architecture Processors Getting Started Guide
CodeWarrior Development Studio for Power Architecture Processors Getting Started Guide Document Number: CWPAGS Rev. 10.5.1, 2 Freescale Semiconductor, Inc. Contents Section number Title Page Chapter 1
Designing with NXP i.mx8m SoC
Designing with NXP i.mx8m SoC Course Description Designing with NXP i.mx8m SoC is a 3 days deep dive training to the latest NXP application processor family. The first part of the course starts by overviewing
EMBEDDED SYSTEMS WITH ROBOTICS AND SENSORS USING ERLANG
EMBEDDED SYSTEMS WITH ROBOTICS AND SENSORS USING ERLANG Adam Lindberg github.com/eproxus HARDWARE COMPONENTS SOFTWARE FUTURE Boot, Serial console, Erlang shell DEMO THE GRISP BOARD SPECS Hardware & specifications
Multicore Challenges and Choices: Deciding Which Solution Is Right for You
Multicore Challenges and Choices: Deciding Which Solution Is Right for You Tomas Evensen Chief Technology Officer, Wind River Table of Contents Executive Summary... 1 Business and Technology Trends...
Test and Verification Solutions. ARM Based SOC Design and Verification
Test and Verification Solutions ARM Based SOC Design and Verification 7 July 2008 1 7 July 2008 14 March 2 Agenda System Verification Challenges ARM SoC DV Methodology ARM SoC Test bench Construction Conclusion
Practical Hardware Debugging: Quick Notes On How to Simulate Altera s Nios II Multiprocessor Systems Using Mentor Graphics ModelSim
Practical Hardware Debugging: Quick Notes On How to Simulate Altera s Nios II Multiprocessor Systems Using Mentor Graphics ModelSim Ray Duran Staff Design Specialist FAE, Altera Corporation 408-544-7937
C912 Freescale QorIQ T4 3U VPX SBC
Freescale QorIQ T4 3U VPX SBC Rugged 3U VPX Single-Slot SBC Freescale QorIQ Multicore SOC Processor 8/4 e6500 Dual Thread Cores (T4160/T4080) AltiVec Unit Memory Resources 4 GB DDR3 @ 1600 MT/s with ECC,
QCVS Frame Distributor Wizard User Guide
QCVS Frame Distributor Wizard User Guide Document Number: QCVSFDWUG Rev. 4.3, 07/2015 2 Freescale Semiconductor, Inc. Contents Section number Title Page Chapter 1 Frame Distributor Wizard 1.1 Introduction...5
Linux Device Drivers: Case Study of a Storage Controller. Manolis Marazakis FORTH-ICS (CARV)
Linux Device Drivers: Case Study of a Storage Controller Manolis Marazakis FORTH-ICS (CARV) IOP348-based I/O Controller Programmable I/O Controller Continuous Data Protection: Versioning (snapshots), Migration,
Veloce2 the Enterprise Verification Platform. Simon Chen Emulation Business Development Director Mentor Graphics
Veloce2 the Enterprise Verification Platform Simon Chen Emulation Business Development Director Mentor Graphics Agenda Emulation Use Modes Veloce Overview ARM case study Conclusion 2 Veloce Emulation Use
Introduction to Pre-Boot Loader Supported by QorIQ Processors
Introduction to Pre-Boot Loader Supported by QorIQ Processors FTF-NET-F0152 Zhongcai Zhou Application Engineer A P R. 2 0 1 4 TM External Use Introduction What does Pre-Boot Loader (PBL) do? Device configuration
P1010RDB-PB Quick Start Guide
Freescale Semiconductor P1010RDB-PB Quick Start Guide Document Number: P1010RDBPBQS Rev. 0, 10/2013 P1010RDB-PB Quick Start Guide 1 Introduction to P1010RDB-PB This quick start guide applies to boards
ARM Trusted Firmware: Changes for Axxia
ARM Trusted Firmware: Changes for Axxia atf_84091c4_axxia_1.39 Clean up klocwork issues, Critical and Error only, and only in code added to support Axxia. atf_84091c4_axxia_1.38 Allow non-secure access
Understanding Device Tree Files in Multicore Hypervisor/LWE Implementations
Freescale Semiconductor Application Note Document Number: AN3649 Rev. 0, 10/2008 Understanding Device Tree Files in Multicore Hypervisor/LWE Implementations by Networking and Multimedia Group Freescale
PDK (Platform Development Kit) Getting Started. Automotive Processors
PDK (Platform Development Kit) Getting Started Automotive Processors 1 Agenda PDK Overview PDK Software Architecture PDK Directory structure PDK Pre-requisite and Build instructions Running Examples Important
10 Steps to Virtualization
AN INTEL COMPANY 10 Steps to Virtualization WHEN IT MATTERS, IT RUNS ON WIND RIVER EXECUTIVE SUMMARY Virtualization the creation of multiple virtual machines (VMs) on a single piece of hardware, where
Android OS and Power Architecture
June 24, 2010 OS and Power Architecture FTF-NET-F0677 Phil Brownfield Software Product Manager, NMG Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC,
KeyStone C66x Multicore SoC Overview. Dec, 2011
KeyStone C66x Multicore SoC Overview Dec, 011 Outline Multicore Challenge KeyStone Architecture Reminder About KeyStone Solution Challenge Before KeyStone Multicore performance degradation Lack of efficient