Performance Analysis with Hybrid Simulation

Transcription

1 6 th November, 2008 Performance Analysis with Hybrid Simulation PN111 Matthew Liong System and Application Engineer, NMG owners. Freescale Semiconductor, Inc

2 r2 Overview Hybrid Modeling Overview Capturing Performance Metrics Statistics Observing Events Pipeline tracing and viewing Visualization owners. Freescale Semiconductor, Inc

3 Slide 2 r2 resize text and bold rh120c, 6/6/2005

4 Hybrid Modeling Overview owners. Freescale Semiconductor, Inc

5 Simulation Terminology Primer: A Functional Model A functional model is a model that simulates the exact functionality of a hardware device CPU0 CPUn A functional model is also referred to as instruction accurate or an instruction set simulator (ISS) A functional model contains no timing or cycle-accurate behaviors Memory Map Memory A functional model can consume application binaries I/O, DMA Data Path Typical speed of a functional model is in the hundreds of millions of instructions per second Network owners. Freescale Semiconductor, Inc

6 Simulation Terminology Primer: A Performance Model A performance model is a model that simulates the exact functionality and performance of a hardware device CPU0 Exe Units/BIU CPU0 Exe Units/BIU Performance models are referred to as cycle-based or timing models Performance models typically consume application binaries or traces Coherency Module DDRC0 DDRC1 Depending on level of detail and complexity of model part, simulator speed can be between hundreds to hundreds of thousands of instructions per second I/O, DMA Network Data Path Acceleration owners. Freescale Semiconductor, Inc

7 Simulation Terminology Primer: A Hybrid Model The term hybrid is used to indicate a combination of at least two heterogeneous resources within the same environment A hybrid model is a simulator that combines both a pure functional model with a performance model within the same environment Hybrid Model owners. Freescale Semiconductor, Inc

8 Functional Model Use Spectrum Hardware Software Platform Development Bringup Application Software Microprocessor Development Functional Verification Functional Model Low Level Debugging Library Development Customer Hardware Development Co-Simulation Compiler Technology owners. Freescale Semiconductor, Inc

9 Performance Model Use Spectrum Hardware Software Platform Development System Tradeoffs Application Software Microprocessor Development Performance Bottlenecks Performance Model Performance Tuning Library Development Customer Hardware Development Co-Simulation Compiler Technology owners. Freescale Semiconductor, Inc

10 P4080 Hybrid Model owners. Freescale Semiconductor, Inc

11 Hybrid Simulation Rough Detail Virtutech and Freescale Semiconductor have joined forces to create a hybrid model of the P4080 SoC The hybrid simulator uses Virtutech s fast functional simulation modeling technology combined with Freescale s high fidelity performance modeling technology owners. Freescale Semiconductor, Inc

12 Introducing P Block Diagram P4080 Performance Model Power Architecture 128KB e500-mc Core Backside L2 Cache 32KB 32KB D-Cache I-Cache 1024KB Frontside L3 Cache 1024KB Frontside L3 Cache 64-bit DDR-2 / 3 Memory Controller 64-bit DDR-2 / 3 Memory Controller eopenpic Pre Boot Loader Security Monitor Internal BootROM CoreNet Coherency Fabric PAMU PAMU PAMU PAMU PAMU Peripheral Access Mgmt Unit Power Mgmt SD/MMC SPI elbc Security 4.0 Queue Mgr. Frame Manager Parse, Classify, Distribute Frame Manager Parse, Classify, Distribute RapidIO Message Unit (RMU) 2x DMA Real Time Debug Watchpoint Cross Trigger 2x DUART 4x I 2C 2x USB 2.0/ULPI Test Port/ SAP Pattern Match Engine 2.0 Buffer Mgr. 10GE Buffer 1GE 1GE 1GE 1GE 10GE Buffer 1GE 1GE 1GE 1GE PCIe PCIe SRIO PCIe SRIO Perf CoreNet Monitor Trace Aurora Clocks/Reset GPIO CCSR 18-Lane 5GHz SERDES owners. Freescale Semiconductor, Inc

13 Hybrid Model Layout libsim_p4080.a e500mc (8x) CCSR CHB CCM CHB CHB CHB CHB CPC CDQ DDRC CPC CDQ DDRC PME BMan FMan FMan CAAM QMan Freescale API + Virtutech Glue Code Memory Map Memory eopen PIC, SD/MMC, SPI, DUART, I 2 C, PCIe, SRIO P4080-cca.so Virtutech Functional Model owners. Freescale Semiconductor, Inc

14 Collecting Performance Metrics owners. Freescale Semiconductor, Inc

15 Statistics Can be summarized Can be collected individually using Simics attributes Available for programmatic uses Events Emitted from the performance model Bound to Simics haps Currently supported events (more on the way) Mark points Instruction completion Interrupts Cache events Data path events Collecting Performance Metrics owners. Freescale Semiconductor, Inc

16 Collecting Performance Metrics Obtaining a stats summary owners. Freescale Semiconductor, Inc

17 Collecting Performance Metrics Obtaining individual metrics owners. Freescale Semiconductor, Inc

18 Observing Events Event hap control flow Python Interpreter Simulator owners. Freescale Semiconductor, Inc

19 Observing Events Registering haps owners. Freescale Semiconductor, Inc

20 Observing Events haps output owners. Freescale Semiconductor, Inc

21 Pipeline Tracing and Viewing owners. Freescale Semiconductor, Inc

22 Pipeline Tracing Detailed visibility into the internal state of the SoC Configurable views of stalls, instruction and transaction flows Useful for: Studying traffic flows Discovering bottle-necks Multicore functional debugging Coherency debugging Dead-lock and live-lock detection Performance tuning owners. Freescale Semiconductor, Inc

23 Pipeline Tracing Capturing pipeline traces owners. Freescale Semiconductor, Inc

24 Pipeline Tracing Viewing pipeline traces owners. Freescale Semiconductor, Inc

25 Pipeline Tracing Viewing pipeline traces (cont d) owners. Freescale Semiconductor, Inc

26 Pipeline Viewing LSU pipe owners. Freescale Semiconductor, Inc

27 Pipeline Viewing MSS owners. Freescale Semiconductor, Inc

28 Visualization owners. Freescale Semiconductor, Inc

29 Simics P4080 Hybrid Model User-Level Architecture Serial Console I/O Bridge Component Functional Model DML DML Performance Model DML Hybrid Glue Library Simics MPC8578 Hybrid Model Visualization Plug-in Dump Files Simics Simulator Backplane (Proposed) TCP/IP Telnet Simics Hindsight Pipeline Visualization 3rd Party Hybrid Front End ex. WRS TraceEvent +? (Proposed) Debugger Session w/simulated Agent ex. GDB/DDD User Python Scripts Dump File 3rd Party Software Debugger ex. CodeWarrior, WRS Workbench, GHS MULTI, QNX, GDB/DDD Event Visualization ex. WRS SystemViewer (Proposed) User wxpython GUI owners. Freescale Semiconductor, Inc

30 Demo performance inspection GUI Visualization owners. Freescale Semiconductor, Inc

31 Session Location Online Literature Library Related Session Resources Sessions Session ID Title Demos Pedestal ID Demo Title owners. Freescale Semiconductor, Inc

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