SPEAr: A Customozable MPSoC for Multiprocessor Applications

Transcription

1 SPEAr: A Customozable MPSoC for Multiprocessor Applications STMicroelectronics s.r.l. Italy Via Olivetti 2, Agrate Brianza (MB) 20041, Italy Fabio Mario Scalise Business Development Mailto: Fabio.scalise@st.com

2 SPEAr Embedded empu Family An innovative concept of SoC A flexible solutions offering both: Off-the-shelf Standard Products Structured ASIC Products ARTEMISIA Association Title Presentation -2 2

3 SPEAr at a glance Highly Integrated 32 bit ARM empu cores ARM926 to Cortex A9, 90nm to 40nm CMOS technology) High computation power (starting from 366MIPS ) Full Capability for High end Operating Systems (Linux, VxWORKS, WinCE ) State of the art peripherals/subsystems High speed connectivity, memory interfaces and internal bus systems Dynamic Power savings features Dynamic frequency scaling Clock inhibit feature Power islands Full range ASSP portfolio Multiple Standard products in different Product Lines Evolutionary Roadmap Optional configurable embedded logic block To develop a customized SPEAr solution for a specific application Flexible development kits For full custom-project approach ARTEMISIA Association Title Presentation -3 3

4 MCU + empu + ASIC approaches ASIC MPU MCU SPEAr STM8/32 ASIC 100% dedicated customized blocks dedicated peripherals Embedded MPU (empu) MMU, FPU (SPEAr13xx only) 366 to MIPS range sophisticated peripherals special application IPs and peripherals external memories (DDR1-3 interfaces) MCU (8-Bit.. 32-Bit) target non-os systems up to 150 MIPS comprehensive set peripherals on chip memories entry level prices ARTEMISIA Association Title Presentation -4 4

5 SPEAr Solutions for Many Applications Networking Automation Bar Code Thin Client Instrumentation Voip Access point Docking Station Imaging E-Retail shelf ARTEMISIA Association Title Presentation -5 5

6 SPEAr Applications Range Examples Metering/ Home automation High-end energy meter Metering concentrator Multi utility controller (MUC) Human Machine Interface (HMI) Low end Internet / network gateway Factory automation Programmable Logic Controller (Digital I/O, motor control, field bus management, ) Industrial HMI Network & Audio Consumer applications Audio Media player Internet radio Web browser Media server Security Network Camera MJPEG streaming Web server interface Point of Sales Secured smartcard reader Cryptographic applications Telecom Voice over IP terminal Analog Telephony Adapter And not only ARTEMISIA Association Title Presentation -6 6

7 SPEAr as Structured ASIC Ethernet Flash, SRAM SDRAM, DDR SPEAr 2A9 Cortex A9 MP 500Mhz 1300K gates LEDs, KBD, LVDS Memory Cards Customizable Logic Gates SPEAr SPEAr 2H9 2 x Arm Mhz 600K gates SPEAr H9 Arm Mhz 300K gates Faster TTM Lower NRE Qualified SoC Architecture Note (1): Worst Case ARTEMISIA Association Title Presentation -7 7

8 SPEAr empu Roadmap 2A k gates Dual HD Display, 3x PCIe BGA580 55nm HCMOS LP Performance, Logic Array Gates H k gates BGA420 2H k gates Dual XGA display controller 23x23mm BGA420 90nm HCMOS GP H k gates 15x15mm BGA289 65nm HCMOS LP SPEAr600 General Purpose SPEAr320 Automation SPEAr310 Communication SPEAr300 VoiP, Sec SPEArXXX TBD and beyond = ASSP for Mass Market ARTEMISIA Association Title Presentation -8 8

9 SPEAr 600 architecture ARTEMISIA Association Title Presentation - 9

10 EXPANSION INTERFACE I 81 ACP FPU WD/ TIMER I-cache 32KB A9SM PTM i/f Cortex A9 D-cache 32KB FPU WD/ TIMER I-cache 32KB PTM i/f Cortex A9 D-cache 32KB SPEAr1300 RAS R 80 I SCU GIC ABI L2 cache L2CC (512KB) 1.3 Mgates F G /20 50/55 70/75 30/ MultiLayer Interconnect Matrix 10/100 20/75 40/ / /55/80 30/35/ /100 70/75 20/50 35/ H K J L M N 16/32 (ECC) SDRAM Controller DDR 2/ CFG 300KB LCD C3 MCIF SATA/PCIe 0 C A B D SSP I2C I2S(2) KBD ADC JPGC RAM UART FSMC GMAC UHC (2) Application Low Speed Basic High Speed ARTEMISIA Association Title Presentation - 10 GPT (4) RTC GPIO (2) Misc DMAC DMAC ROM SMI SATA/PCIe 2 SATA/PCIe 1 UOC 30

11 SPEAr : empu Family Overview by Product ARTEMISIA Association Title Presentation 11-11

12 SPEAr empu Main Features General purpose Industrial Automation Telecom Networking SPEAr600 MHz Dual core SPEAr320 MHz Single core SPEAr310 MHz Single core High performances dual core up to 733MIPS DDR1-2, GMII MAC, 3xUSB2.0, AHB bus expansion LCD I/F, I2C, UART, ADC (1MSPS), GPIO, SRAM, Flash High performances single core up to 366MIPS LPDDR2/DDR2, 2xSMII/MII MAC, 3xUSB2.0, Crypto engine LCD I/F touch screen, CAN I/F, I2C, UART, SDIO/MMC I/F High performances single core up to 366MIPS LPDDR2/DDR2, 5xSMII/MII MAC, 3xUSB2.0, Crypto engine HDLC I/F, TDM I/F, I2C, 5xUART VoIP Security camera SPEAr300 MHz Single core High performances single core up to 366MIPS LPDDR2/DDR2, MII MAC, 3xUSB2.0, Crypto engine LCD I/F touch screen, Camera I/F, TDM I/F, Keyboard I/F, SLIC I/F ARTEMISIA Association Title Presentation 12-12

13 SPEAr300 Overview 333 MHz High-performance 8-channel DMA Internal memory: 32 Kbytes ROM up to 57 Kbytes SRAM External Memory: LP-DDR, DDR2, SRAM, NAND/NOR Flash SDIO/MMC Card FPGAs connection Connectivity: USB 2.0 (2 Host, 1 Device) with PHYs Ethernet MAC SPI/I²C (up to 8 Chip selects) I²S UART IrDA TDM BUS Peripherals: Camera interface LCD panel Touchscreen 9 x 9 keyboard Timeslot management Cryptographic engine Miscellaneous functions: Integrated real time clock, Watchdog, System controller JPEG codec accelerator ADC Timers up to 44 GPIOs Package: LFBGA289 (15 x 15 mm, pitch 0.8 mm) ARTEMISIA Association Title Presentation 13-13

14 SPEAr310 Overview 333 MHz High-performance 8-channel DMA Internal memory: 32 Kbytes ROM up to 8 Kbytes SRAM External Memory: LP-DDR, DDR2, SRAM, NAND/NOR Flash FPGAs connection Connectivity: USB 2.0 (2 Host, 1 Device) with PHYs Five Ethernet MAC (MII and 4 x SMII) TDM/HDLC Bus HDLC ports with RS485 support SPI (up to 4 Chip Selects) I²C UARTs IrDA Cryptographic engine Unique in the market with: 6 UARTs 5 Ethernet MAC 3 USB 2.0 ports Crytpo accelerator Miscellaneous functions: Integrated real time clock, Watchdog, System controller JPEG codec accelerator ADC Timers up to 102 GPIOs Package: LFBGA289 (15 x 15 mm, pitch 0.8 mm) ARTEMISIA Association Title Presentation 14-14

15 SPEAr320 Overview 333 MHz High-performance 8-channel DMA Internal memory: 32 Kbytes ROM up to 8 Kbytes SRAM External Memory: LP-DDR, DDR2, SRAM, NAND/NOR Flash SDIO/MMC Card FPGAs connection Connectivity: USB 2.0 (2 Host, 1 Device) with PHYs Dual Ethernet MAC (SMII/MII) Dual CAN Standard parallel port SPI (up to 6 Chip Selects) I²C UARTs IrDA Cryptographic engine Peripherals: LCD panel Touchscreen Miscellaneous functions: Integrated real time clock, Watchdog, System controller JPEG codec accelerator ADC PWM Timers up to 102 GPIOs Package: LFBGA289 (15 x 15 mm, pitch 0.8 mm) ARTEMISIA Association Title Presentation 15-15

16 SPEAr600 Overview Dual 333 MHz High-performance 8-channel DMA Up to 733 DMIPS Internal memory: 32 Kbytes ROM up to 8 Kbytes SRAM External Memory: DDR, DDR2, NAND/NOR Flash Connectivity: USB 2.0 (2 Host, 1 Device) with PHYs Giga-Ethernet SPI I²S UARTs IrDA Peripherals: LCD panel Touchscreen Miscellaneous functions: Integrated real time clock, Watchdog, System controller JPEG codec accelerator ADC Timers up to 10 GPIOs External Local BUS Package: PBGA420 (23 x 23 mm, pitch 1 mm) ARTEMISIA Association Title Presentation 16-16

17 SPEAr : Some specific IPs description ARTEMISIA Association Title Presentation 17-17

18 USB2.0 3x USB2.0 ports 2x host interface 1x device port Multistandard 480 Mbps high-speed (HS) 12 Mbps full-speed (FS) 1.5 Mbps low-speed (LS) Host ports compliances Host port Enhanced Host Controller Interface (EHCI) specification (version 1.0) Open Host Controller Interface (OHCI) specification (version 1.0a) Device port 16 physical endpoints and proper configurations to achieve logical endpoints ARTEMISIA Association Title Presentation - 18

19 Ethernet MAC 10/100Mbps for SPEAr3xx 10/100/1000Mbps for SPEAr600 MII, SMII and GMII PHY interfaces Standard and Jumbo frames supported (up to 16KByte) Half-duplex & full duplex support SPEAr600 offload HW Automatic CRC generation controllable on a per-frame basis SPEAr3xx offload HW Automatic CRC generation controllable on a per-frame basis IP Header checksum check for received frames ARTEMISIA Association Title Presentation - 19

20 Controller Area Network interface Instantiated in SPEAr320 Supports CAN protocol version 2.0 part A and B Bit rates up to 1 MBit/s 32 message objects (136 X 32 message RAM) Each message object has its own identifier mask for Acceptance Filtering of Received Messages Enable/disable automatic retransmission mode Disabled for time triggered CAN applications Optional silent mode can be used to analyze the traffic on a CAN bus without affecting it Programmable loop-back mode for self-test Maskable interrupt External transceiver as physical layer Message Objects & Identifier Masks. Protocol Controller & Rx/Tx Shift Registers Shift registers <> RAM Data transfer control & acceptance filtering ARTEMISIA Association Title Presentation - 20

21 Synchronous Serial Port Master or slave interface for synchronous serial communication Multiple standard compliant Texas Instrument synchronous serial frame Motorola SPI frame formats (4 different modes) National Microwire frame format Up to 41Mbps Programmable operating modes ARTEMISIA Association Title Presentation - 21

22 SPEAr : Documentation, Development Tools and Software ARTEMISIA Association Title Presentation 22-22

23 SPEAr Supporting tools for promotion / evaluation and development Documentation available on o Datasheets o Product Brochures o Application Notes o Evaluation Boards User manual o Software User manual o Software Demos Documentation available on demand o Device User Manual Linux OS suite available o Software download updates on ARTEMISIA Association Title Presentation 23-23

24 SPEAr evaluations kits Evaluation kits are designed to o o o o Speed up the software development/debug process Get quickly familiar with SPEAr MPU features Each evaluation kit offers all of the interfaces that the SPEAr device can manage Act as a starting point for your final application board development EVALSPEAR300 Eval kit SPEAr300 EVALSPEAR320PLC Eval kit SPEAr320 ARTEMISIA Association EVALSPEAR310 Eval kit SPEAr310 EVALSPEAR600 Eval kit SPEAr600 Title Presentation 24-24

25 EVALSPEAr300 evaluation kit Features SPEAr300 embedded MPU Up to 2Gb DDR2 333MHz (std 128MB) Up to 16MB Serial Flash (std 8MB) Up to 2Gb NAND Flash (std 64MB) 4Kb Serial I2C 4Mb SPI Flash memory Two USB2.0 HS host port One USB2.0 HS device port 10/100 Ethernet port One serial port (up to 115Kbaud) Debug ports (JTAG + ETM9) 8 ADC channels (10 bit, 1Msps) 8 GPIOs LCD I/F up to 24 bits-per-pixel SD Card interface In the box SPEAr300 Evaluation Board A/C Adapter (5V) 2 Plug Adapter (USA/EU) Board User Manual ARTEMISIA Association Title Presentation 25-25

26 EVALSPEAr310 evaluation kit Features SPEAr310 embedded MPU Up to 2Gbits DDR2 333MHz (std 128MB) Up to 1.5Gbytes Parallel NOR Flash (std 16MB) Up to 16Mbytes Serial NOR Flash (std 64MB) Up to 2Gbits NAND Flash (std 64MB) 4Kb Serial I2C EEPROM 4Mb SPI Flash memory Two USB2.0 HS host port One USB2.0 HS device port One 10/100 Ethernet port based on MII PHY Four 10/100 Ethernet port based on SMII PHY One E1, 2x BNC/RJ48 (2.048Mbits) Two HDLC RS485 DB9 ports (up to 4MHz) One HDLC-TDM port (8Mb, 128TS) Six Serial ports (up to 115kbaud) 8 ADC channels (10 bit, 1Msps) 6 GPIOs JTAG debug port In the box SPEAr310 Evaluation Board A/C Adapter (5V) 2 Plug Adapter (USA/EU) Board User Manual ARTEMISIA Association Title Presentation 26-26

27 EVALSPEAr320PLC evaluation kit The EVALSPEAR320PLC evaluation board kit consists of two boards o CPU board o MII mode application board SPEAr320 microprocessor is mounted on the CPU board that is plugged on the MII mode application board The application board also includes digital input/output serial/parallel connectors with a pinout compatible with many existing evaluation boards from ST: STEVAL-IFP007V1, STEVAL-IFP004V1, STEVAL-IFP008V1, STEVAL-IFP009V1, STEVAL-IFP002V1, STEVAL-IFP001V1 and STEVAL- IFP006V1 The application board can be powered using a standard DC power supply (7 V to 30V DC) or directly using a 24V DC industrial mains supply ARTEMISIA Association Title Presentation 27-27

28 SPEAr3x0 system prototyping SPEAr320PLC evaluation board is using a stacking board approach that is going to be extended to all SPEAr3x0 family. Future systems will be composed by: o A CPU board o An application board CPU board Supports all SPEAr3x0 devices Includes all common peripherals (DDR2, NOR, USB, RTC, Power supply, ) NOR Power RTC DDR2 JTAG SPEAr UART USB Application board Specific to a Spear3x0 version and to a given application Includes all application specific peripherals and connectors SDIO RS232 2x76pins headers as CPU board socket I2C LED RS232 GPIO Button RS232 ADC Application board example Reset CAN RS485 CAN Ethernet Ethernet Temp. Pot. ARTEMISIA Association Title Presentation 28-28

29 EVALSPEAR600 evaluation kit In the box SPEAr600 Evaluation Board A/C Adapter (12V) 2 Plug Adapter (USA/EU) Board User Manual Features SPEAr600 embedded MPU Up to 2Gb DDR2-333MHz (std 128MB) Up to 16MB Serial Flash (std 8MB) Up to 2Gb NAND Flash (std 64MB) 4Kb Serial I2C Two USB2.0 HS host ports One USB2.0 HS device port 10/100/1000 Ethernet port Two Serial ports (up to 115Kbaud) Debug ports (JTAG + ETM9) 8 ADC channels (10 bit, 1Msps) 10 GPIOs LCD I/F up to 24 bits-per-pixel Additional 112 GPIOs when the external FPGA is used ARTEMISIA Association Title Presentation 29-29

30 SPEAr software deliveries An embedded Linux system generally relies on the following components o Internal RomCode that locates and load from flash the 2 nd loader (known as xloader) o Xloader that configures the DDR + basic system and loads the main boot loader o Uboot which is the main Linux boot loader o Linux Kernel tailored to the application o Linux file systems generally located in Flash ST delivers all these components Linux OS supported by ST Linux kernel full sources, including spear peripheral drivers Boot loading FW: Xloader / Uboot Root file systems + set of user space packages Ready to use Flash binary images for serial NOR Script to rebuild NAND and parallel NOR binary images Cross development toolchain (open source GCC) Demo software source & binaries LSP user manual / software application notes Available through Other OS supported by partners WinCE (*) : Adeneo Integrity : GreenHills VxWorks : Under discussion (*) only SPEAr600 ARTEMISIA Association Title Presentation 30-30

31 Some embedded Linux key points: Single source code tree for all SPEAr targets Based on standard frameworks and APIs wherever defined UART, SPI master, I2C master, CAN, HDLC, ETH, USBH/USBD, flash memories, SD/MMC card, display, audio, DMA, GPIO, RTC, WDT, power management Compliant to Linux coding guidelines Merging to mainline open source kernel ongoing ARTEMISIA Association Title Presentation 31-31

32 SPEAr Linux development flow All Evaluation boards are shipped flashed with up and running kernel + basic filesystem. JTAG equipment (not provided by ST) : mandatory for customer board bring up, recommended for specific low level driver development, Not mandatory for application development : cheap development. A development workstation is composed of: Linux PC (Fedora core 10 minimum) or centralized server, Linux and Toolset downloaded and installed from Application debug through ethernet recommended for easier use: All applications compiled and stored on host PC, are accessed by SPEAr through network. Debugger are runned in native mode on SPEAr, or on the host through a network connection RS232 used for Uboot and Linux console ARTEMISIA Association Title Presentation -32

33 SPEAr : Debug tools & Boot options JTAG port ETM port Standard Development & Test Tools Standard JTAG connection for debug and embedded memory programming JTAG HW & SW tools not provided by ST Not strictly needed for Linux or WinCE Advanced real time debugging Provides higher debugging facilities and precise profiling/code coverage but quite expensive ETM HW & SW tools not provided by ST Not strictly needed for Linux/WinCE Additional ST tools: ST provides USB flashing utility (Windows application). Supports flash memory update (not limited to Linux) from a PC through USB cable. SPEAr devices offers different Boot options: from Serial NOR/ Parallel NAND/ USB from Ethernet/UART/ Parallel NOR All SPEAr SPEAr3xx ARTEMISIA Association Title Presentation 33-33

34 Typical SPEAr600 dualcore utilization ARM cores can run different OSes Typically one CPU for the network and user interface (Linux, WinCE etc.) The second CPU to tightly control the machine HW (RTOS like ThreadX, VxWorks etc.) HW semaphores allow resources sharing OPTION 1 The 2 nd Core can be used as coprocessor TCP/IP offload, Firewall etc. Smart dedicated interprocessor communication allow fast handshake Cores clustering OPTION 2 Embedded Interprocessor Communication Based MPI (Message Passing Interface, suitable for complex algorithms parallel processing) RSH (Remote Shell, for manual distribution of different process among the cores) Available application note with performance comparisons ARTEMISIA Association Title Presentation 34-34

35 SPEAr: Application Examples ARTEMISIA Association Title Presentation 35-35

36 SPEAr core subsystem Minimal SPEAr subsystem is composed of the following elements : SPEAr Power supply Flash for application boot / code / data Main Memory to run the application. Flash : NOR / NAND Main Memory : DDR1, DDR2, MobileDDR Multiple outputs Power supply Vcore (1 or 1.2V) 1V8 2V5 3V3 1V5 Real Time Clock power supply ARTEMISIA Association Title Presentation 36-36

37 Focus on memory support Type Clock Max Data Rate Usual size Supply Comments Types of external memories : SDRAM MHz DDR MHz DDR MHz mobiledd R MHz Mwords/s MWords/s MWords/s MWords/s High latency 256Mbit (32MB) 512Mbit (64MB) 1Gbit (128MB) 3.3V 2.5V Doubles SDRAM datarate 1.8V Same as DDR but with higher frequency 1.8V Similar to DDR, but with lower consumption due to power voltage and bigger latency Type SDRAM64 SDRAM128 DDR128 DDR256 DDR512 DDR2-256 DDR2-512 ~ Price (cent / MB) Current Linux embedded applications usually require between 32 and 128MB RAM. DDR2 RAM subsystem is usually 2 times cheaper than DDR1, and 4 times cheaper than SDR! This is a strategic advantage for SPEAR family. DDR2-1G ARTEMISIA Association Title Presentation - 37

38 Low-end VoIP Phone example Budgetary BOM 30 USD Serial EEPROM (or NAND) LCD 6x6 Keypad 6 6 Notes: BOM may vary by ODM BOM not including: - patent fees for G.72x codecs - case - external AC/DC adapter Handset Handsfree Hook, etc MIC SPI SPKR SPEAr 300 MIC Audio Codec GPIO TDM I2C SPI-CS GPIO MII MDIO 10/100 ETH SWITCH + PHYs PoE PM8800A PC LAN SPKR FSMC NAND Flash DDR I/F DDR2 UART JTAG Debug ports QoS handled here Power & Reset Power Adapter ARTEMISIA Association Title Presentation 38-38

39 VoIP ATA / Router-Firewall example Budgetary BOM 27 USD Display I2C GPIO Buttons Notes: BOM may vary by ODM BOM not including: - patent fees for G.72x codecs - case - external AC/DC adapter Analog Phone Analog Phone or Fax Dual FXS (Note 1) SPI TDM SPEAr 300 MII MDIO 10/100 ETH SWITCH + PHYs (Note 2) WAN SMI Serial NOR Flash DDR I/F DDR2 UART JTAG Debug ports 2-port s expansion mode + L2 QoS Power & Reset PC/LAN Power Adapter ARTEMISIA Association Title Presentation 39-39

40 SPEAr310 Central Offices controller Up to 6 UARTs SPEAr310 UART1 UART2 UART3 UART4 UART5 Alternative UART0 modem F.C. Additional IPs ARM926EJ-s 333MHz 16K+16K I/D CACHE 32KB boot ROM 8kB boot RAM System I/O Memory cntr. SPI Flash mobileddr/ddr2 accelerators JPEG encoder Crypto accelerator Boot NOR flash 16MBytes STE100P DDR2 10/100 Base-T 2 x RS bits data path 28bits add. path LATCH Quad PHY Transceiver local bus (EMI) SMII controls TDM HDLC HDLC GPIOs Alternative to MII Eth. EMI + Flexible Static Memory Controller Quad Ethernet MAC & 125MHz ref. Analog i/f 8x10b 1Msps ADC 4 x 16bit Timer Watchdog Timer 8 x DMA Interrupt cntrl. RTC System USBs PLL Aux PLL System SSGC ETM-9 JTAG Connectivity 10/100 MII Ethernet MAC Double (HS-FS) USB Host UART0 SPI Fast IrDA RX/TX HS USB Device I2C USB PHY USB PHY USB PHY ARTEMISIA Association Title Presentation 40-40

41 SPEAr310 Data Concentrator Functional Diagram USB0 ETH0 UART5 USB1 Eth PHY RS 485 ETH1 10/100 Base-T UART Fast IrDA Local control / access / maintenance 10/100 Base-T UART4 UART3 Eth PHY Modem i/f V90 UART0 GPRS modem Remote control / access UART1 UART2 Proprietary Wireless 16Bits NAND flash up to 4GBytes (FSMC) DDR2-SDRAM Up to 256MBytes (DDR I/F) Local memories Boot NOR flash 16MBytes (SPI) Power Line Communication Modem Power meters ARTEMISIA Association Title Presentation - 41

42 SPEAr320 Thermal printer FSMC (EMI & NAND i/f) LCD cntroller Touchscren (4-wire) SDIO interface 2 x CAN2.0 i/f ARM926EJ-s 333MHz 16K+16K I/D CACHE 32KB boot ROM 8kB boot RAM System I/O Memory cntr. SPI Flash mobileddr/ddr2 accelerators JPEG encoder Crypto accelerator STE100P Ethernet Cable 4 x PWM I2S i/f 2 x SPI i/f 4 x 16bit Timer Watchdog Timer 8 x DMA Connectivity 10/100 MII Ethernet MAC Registered GPIOs I2C i/f 2 x UART Camera i/f SPP Interrupt cntrl. RTC System USBs PLL Double (HS-FS) USB Host HS USB Device USB PHY USB PHY USB PHY MII/SMII MAC SMII MAC Little-Big endian wrapper Aux PLL System SSGC UART IrDA Analog i/f 8x10b 1Msps ADC ETM-9 JTAG SPI I2C ARTEMISIA Association Title Presentation 42-42

43 SPEAr320 Automation application example 1 HMI Human Machine Interface Factory LAN RJ45 RJ45 Fieldbus Graphical LCD with TOUCH Keyb. ctrl Touc h CLCD I2C SMII PHY SMII PHY CAN Transc. Transc. CAN SPEAr320 ARM926EJ-S 333MHz RS232 / 485 Transc. Transc. Transc. DB9 DB9 DB9 Fieldbus Keypad SDIO Serial NOR Flash SMI FSMC Parallel NAND Flash DDR DDR2 JTAG JTAG ARTEMISIA Association Title Presentation - 43

44 SPEAr320 Automation application example 2 IP Expander (allows simple connection of FPGA with customer application specific IP + SRAM/NOR/NAND flash memories) Factory LAN RJ45 Internal System Communication / Fieldbus FPGA PHY Transc. Transc. e.g. Dedicated motor control, communication or other customer specific IP(s) SRAM Parallel NOR / NAND Flash FSMC/EMI 4 x PWM SMII CAN SMI CAN SPEAr320 ARM926EJ-S 333MHz 2 x I2C DDR RS232 / 485 Transc. Transc. Transc. DB9 DB9 DB9 I/O Control / bus Serial NOR Flash DDR2 USB Device Power Supply JTAG USB Host/ Mass Storage ARTEMISIA Association Title Presentation 44-44

45 SPEAr600 empu IP expansion AHB bidirectional bus expansion Glueless FPGA interface FPGA Customer IP M ARTEMISIA Association Title Presentation 45-45

46 SPEAr : empus family Full Feature Set Description ARTEMISIA Association Title Presentation 46-46

47 SPEAr300 Complete Feature Set ARM926EJ-S core runs up to 333 (1) MHz High-performance 8-channel DMA Dynamic power-saving features Configurable peripheral functions muxed on 102 shared I/Os Memory: 32-KB ROM and up to 57-KB internal SRAM LPDDR-333/DDR2-666 interface Flexible static memory controller (FSMC) up to 16-bit data bus width, supporting external SRAM, NAND/NOR Flash and FPGAs Serial SPI Flash interface SDIO/MMC card interface C3 Cryptographic engine AES Channel(up to 256 bit keys) DES/Triple DES Channel Universal HASH (SHA1, MD5, HMAC) Connectivity: 2 USB 2.0 hosts 1 USB 2.0 device Fast Ethernet (MII port) SPI, I 2 C, I 2 S, UART and fast IrDA interfaces Up to 8 additional I 2 C/SPI chip selects TDM bus (512 timeslots) Peripherals supported: Camera interface LCD controller (res. up to 1024 x 768 and up to 24 bpp) Touchscreen support 9 x 9 keyboard controller Miscellaneous functions: Integrated real-time clock, watchdog, and system controller 8-channel 10-bit ADC, 1 MSPS 1-bit DAC JPEG codec accelerator 6 general-purpose 16-bit timers with capture mode and programmable prescaler Up to 44 GPIOs with interrupt capability Package: LFBGA289 (15 x 15 mm, pitch 0.8 mm) Glueless management of up to 8 SLICs/codecs Note: (1) Worst case ARTEMISIA Association Title Presentation 47-47

48 SPEAr310 Complete Feature Set ARM926EJ-S core runs up to 333 (1) MHz High-performance 8-channel DMA Dynamic power-saving features Configurable peripheral functions muxed on 102 shared I/Os Memory: 32-KB ROM and up to 8-KB internal SRAM LPDDR-333/DDR2-666 interface Serial SPI Flash interface Flexible static memory controller (FSMC) up to 16-bit data bus width, supporting NAND Flash External Memory interface (EMI) up to 32-bit data bus width, supporting NOR Flash and FPGAs C3 Cryptographic engine Connectivity: 2 x USB 2.0 Host 1x USB 2.0 Device 1 x Fast Ethernet (MII port) 4 x Fast Ethernet (SMII port) SPI (up to 4 Chip Selects) I2C and fast IrDA interfaces 6 x UART interfaces TDM/E1 HDLC interface with 128/32 timeslots per frame respectively 2 x RS485 HDLC ports C3 Cryptographic engine AES Channel(up to 256 bit keys) DES/Triple DES Channel Universal HASH (SHA1, MD5, HMAC) Miscellaneous functions: Integrated real-time clock, watchdog, and system controller 8-channel 10-bit ADC, 1 MSPS JPEG codec accelerator 6 general-purpose 16-bit timers with capture mode and programmable prescaler Up to 102 GPIOs with interrupt capability Package: LFBGA289 (15 x 15 mm, pitch 0.8 mm) Note: (1) Worst case ARTEMISIA Association Title Presentation 48-48

49 SPEAr320 Complete Feature Set ARM926EJ-S core runs up to 333 (1) MHz High-performance 8-channel DMA Dynamic power-saving features Configurable peripheral functions muxed on 102 shared I/Os Memory: 32-KB ROM and up to 8-KB internal SRAM LPDDR-333/DDR2-666 interface Serial SPI Flash interface SDIO/MMC card interface Flexible static memory controller (FSMC) up to 16-bit data bus width, supporting NAND Flash External Memory interface (EMI) up to 16- bit data bus width, supporting NOR Flash and FPGAs Connectivity: 2 x USB 2.0 hosts 1 x USB 2.0 device 2 x Fast Ethernet (SMII/MII port) 2 x CAN interfaces 3 x SPI ports (up to 6 Chip Selects) 2 x I2C interfaces 3 UART interfaces 1 Standard Parallel Port Fast IrDA interface C3 Cryptographic engine AES Channel(up to 256 bit keys) DES/Triple DES Channel Universal HASH (SHA1, MD5, HMAC) Peripherals supported: LCD controller (resolutions up to 1024 x 768 and up to 24 bpp) Touchscreen support Miscellaneous functions: Integrated real-time clock, watchdog, and system controller 8-channel 10-bit ADC, 1 MSPS 4 x PWM timers JPEG codec accelerator 6 general-purpose 16-bit timers with capture mode and programmable prescaler Up to 102 GPIOs with interrupt capability Package: LFBGA289 (15 x 15 mm, pitch 0.8 mm) Note: (1) Worst case ARTEMISIA Association Title Presentation 49-49

50 SPEAr600 Complete Feature Set Dual ARM926EJ-S up to 333 (1) MHz Each CPU with 16KB I-cache and 16KB D-cache High-performance 8-channel DMA Dynamic power-saving features Up to 733 DMIPS Memory: 32-KBBootROM/ 8KB internal SRAM External DRAM interface: 8/16 bit DDR1-400/DDR2-666 Serial SPI Flash interface Flexible static memory controller (FSMC) supporting NAND Flash memories Serial NOR flash memory interface Connectivity: 2 x USB 2.0 hosts USB 2.0 device Giga- Ethernet GMII (10/100/1000) 3 x SPI ports 3 x I 2 S for audio features 1 x stereo input 2 x stereo outputs 2 x UART interfaces I 2 C and fast IrDA interfaces Peripherals supported: LCD controller (resolutions up to 1024 x 768 and up to 24 bpp) Touchscreen support Miscellaneous functions: Integrated real-time clock, watchdog, and system controller 8-channel 10-bit ADC, 1 MSPS JPEG codec accelerator 10 general-purpose 16-bit timers with capture mode and programmable prescaler 10 GPIOs birectional signals with interrupt capability External 32-bit local BUS Package: PBGA420 (23 x 23 mm, pitch 1 mm) Note: (1) Worst case ARTEMISIA Association Title Presentation 50-50

51 Thank you for your attention We value your opinion and questions