Software Defined Radio (SDR) for Parallel SDR intro in a simple way Satellite Reception in Mobile/Deployable Ground Segments
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1 Software Defined Radio (SDR) for Parallel SDR intro in a simple way Satellite Reception in Mobile/Deployable Ground Segments Small Satellite Conference, Logan, Utah 11/08/ Dr Mark Bowyer & 1 Dr Christopher P. Bridges 1 Surrey Space Centre, University of Surrey, United Kingdom 2 Airbus Space and Defence Ltd., United Kingdom 1
2 Future Work & Conclusions Background & Motivation Conclusion & Future Work 2
3 Future Work & Conclusions 3
4 Future Work & Conclusions FLOCK 1 QB50 STRaND-2 ARReST Frequency Spectrum Ku-band C-band S-band 915MHz Other UHF 437MHz 145 MHz Number of CubeSats Bryan Klofas, CubeSat Communication Systems : A Historical Look," presented at the Nano-satellite Ground Station Workshop, organised by JPL, Feb Problem Statement: There is no generic platform/embedded solution to provide a configurable communication module to support multiple signals from multiple-satellites. 4
5 Future Work & Conclusions Software Defined Radio (SDR) Radio in which some or all of the physical layer functions are software defined Reinhart, R. C., T. J. Kacpura, et al. (2013). "NASA's space communications and navigation test bed aboard the international J. Mitola, "The software radio architecture," Communications Magazine, IEEE, vol. 33, pp.8, space station." Aerospace and Electronic Systems Magazine, IEEE 28(4):
6 Future Work & Conclusions SDR Architecture 6
7 Future Work & Conclusions Test-bed 7
8 Future Work & Conclusions Test-bed Analog Devices 8
9 Future Work & Conclusions Test-bed Encoder Decoder Phil Karn Analog Devices 9
10 Current Work: Initial Results 10
11 Signal Received at Different Data Rates Signal Received at Different Data Rates 1200 bps 2400 bps 4800 bps 9600 bps bps 11 11
12 Util_adc_pack My_DDC_I My_DDC_Q Reference Block Diagram AXI-AD9361 ZYNQ - PS ILA 12
13 Future Work & Conclusions 1. File generated: System.bit; Tool Used: Vivado File generated: First Stage Boot Loader (FSBL.elf); Tool Used: SDK The u-boot.elf(bootloader) 4. File generated: BOOT.BIN; Tool Used: Bootgen in SDK SD Card for Zedboard Boot up (H/w & s/w lines are blurring) 5. File generated: uimage and Devicetree Tool Used: Linux Terminal 6. uenv.txt contains the base address. 13
14 Future Work & Conclusions Original Design (Software DDC) With DDC Block on FPGA Overhead Power: Total On-Chip Power: 2.2 W Dynamic Power : 2.03 W Device Static : 0.17 W Power: Total On-Chip Power: W Dynamic Power : 2.06 W Device Static : W Power: Total On-Chip Power: 1.4% Dynamic Power : 1.47% Device Static : 0.58% Post Implementation: Flip Flop : 19% LUT : 24% Memory LUT : 4% I/O : 61% BRAM : 6% DSP48 : 31% BUFG : 28% MMCM : 50% Post Implementation: Flip Flop : 19% LUT : 24% Memory LUT : 5% I/O : 61% BRAM : 6% DSP48 : 33% BUFG : 28% MMCM : 50% Post Implementation: Flip Flop : 0 LUT : 0 Memory LUT : 1% I/O : 0 BRAM : 0 DSP48 : 2 BUFG : 0 MMCM : 0 Implementation on FPGA Fabric Implementation on FPGA Fabric 14
15 Novelty & Conclusions Digital Down Converter Digital Up Converter 15
16 Novelty & Conclusions 16
17 Spec Spectrum 17
18 Novelty & Conclusions PPPPPPPPPP RRRRRRRRRRRRRRRR EE bb NN oo Variables: Eb = Energy/bit No = Noise Other changes: Gains 18
19 Spec BER v/s Eb/No Ref: M. P. Fitz, Fundamentals of Communications Systems: The McGraw-Hill Companies,
20 Novelty & Conclusions TT = TT RR + mm CCCC vvcccc rrrr DDDDDDDD RRRRRRRR + DDDDDDDDDDDD + TT ww mm = Modulation Scheme CCCC vv CCCC rrrr = Forward Error Correction Codes TT RR, TT ww = Read & Write Time 20
21 Novelty & Conclusions Hardware is Digital Down Converter (DDC) from profiling results 21
22 Novelty & Conclusions Problem statement: Need for an embedded solution to provide a configurable communication module to support multiple signals from multiplesatellites. Proposed solution: SDR with open source hardware & software implemented on low resource embedded systems with a new pipeline architecture. Objectives realised: Implementation of adaptive SDR architecture for different data rates from 1k2 to 19k2. Obtained performance results demonstrate the need to move blocks demanding higher computation capacity. Potential applications: Ground station for multi-satellite communications. Deployable mobile ground station network Distributed satellite systems. 22
23 SDR for Parallel satellite Reception in Mobile/Deployable Ground Segments Surrey Space Centre Website: 23
24 Software Defined Radio (SDR) for Parallel SDR intro in a simple way Satellite Reception in Mobile/Deployable Ground Segments Small Satellite Conference, Logan, Utah 11/08/ Dr Mark Bowyer & 1 Dr Christopher P. Bridges 1 Surrey Space Centre, University of Surrey, United Kingdom 2 Airbus Space and Defence Ltd., United Kingdom 24
25 Profiling - Transmitter Dell Optiplex 745 ODROID XU LITE Processor Intel x86 ARM Cortex A15 & A7 Zedboard ARM Cortex A9 Number of Cores Dual Octa Quad A15 Dual & Quad A7 CPU Frequency 2.13 GHz A GHz 700 MHz A7 1.2 GHz Linux Version System type 64-bit 32-bit 32-bit Application Processor Dell Optiplex 745 ODROID XU LITE Identical Application from Source Zedboard Absolute CPU Consumption - Transmitter 25
26 Profiling Transmitter (Contd..) Profiling Results on Dual Core ARM Cortex A9 Profiling Results on Octa Core ARM Cortex A15 & A7 26 Profiling Results on Dual Core Intel x86
27 Profiling - Receiver Absolute CPU Consumption - Receiver Success Rate Comparison on Different Architectures 27
28 Profiling Receiver (Contd..) Profiling Results on Dual Core Intel x86 Profiling Results on Octa Core ARM Cortex A15 & A7 Dell Optiplex 745 ODROID XU LITE Zedboard C Compiler GCC GCC GCC No. of different Instructions No. of Similar Instructions across the platforms Dominant Instructions (top 5) mov(693) callq(186) add(130) movss(123) cmp(100) 28 add(238) ldr(235) mov(156) movw(146) movt(141) ldr(256) add.w(246) movw(176) add(169) mov(155)
29 Future Work & Conclusions FPAA ADC12D1800 FPGA FunCube Dongle AD 9643 ASIC AD9361/ LMS 7002M ADC08100 Raspberry Pi Simulation: Eldo 29 Simulation: GNURadio
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