Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,

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1 Jeffrey Ho March 2013 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C- Ware, the Energy Efficient Solutions logo, Kinetis, mobilegt, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, the SafeAssure logo, SMAROS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc.

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3 Overview QorIQ Portfolio Overview Market Overview Roadmap Enablement Core Comparison for e500 to e6500 Product Details P5040 T4240 T2080 T1042 Summary 3

4 The industry-leading QorIQ processor portfolio offers advanced multiprocessing solutions for high-performance communications and computing for a smarter, more connected world. Leading performance, power and scalability 4

5 Leading innovation in networking architectures QorIQ: Broadest scalable family of processors in the market Industry-leading integration, performance, power Increasing software investment Innovative Software-aware solutions Industry-leading virtualization support Strong enablement & ecosystem True programmability and Ease of use focus Rich set of reference designs and development platforms Trusted partner Longevity program Global support resources, quality, service 2-24 Core CPU 1-8 Core CPU QorIQ T4240 T2080, T1042 QorIQ P10xx P50xx PowerQUICC Host Processors 5 Service Provider Enterprise Consumer Access Industrial and Aerospace 5

6 Service Provider Core routers RNC Edge routers Central office / broadband access Enterprise/Data Center Multiservice routers WLAN access points Ethernet switches Security / U appliances Industrial & Aerospace Factory & building automation Machine to machine communications Power protection Medical imaging & networks Aerospace communications, radar, sonar SOHO / Consumer Home media distribution Residential gateways Small form-factor control systems 6

7 The Internet of Things is fast becoming real Connected devices = 3x global population Global IP traffic will reach 1.3 zettabytes per year Tremendous growth in mobility 60% of users will generate 1GB+ traffic / month Traffic increase of 10x from 2011 to 2016 Rapid growth in M2M communications Emergence of new nodes Projected 22x traffic increase from 2011 to 2016 Source: Cisco Visual Networking Index (VNI) zettabyte = bytes 7

8 Elastic resources and services Multitenancy support Network optimizations for latency Changing application topology Emergence of specialized servers WAN optimization impacting productivity Growing importance of security Maintain seamless connectivity Ensure IT control & management Guarantee collaboration technologies Mobile Touchpad Appliance GPS Notebook Home Entertainment 8

9 SDKs Biannual releases SDK 1.3 SDK 1.4 SDK 1.5 SDK 1.6 SDK 1.7 High Performance P5040 T4240 LS3xxx P5020/10 P5021 T4160 P4080/40 T2080 Mid Performance P3041 P2041/40 T2081 LS2xxx MPC8569 P2020/10 T1040/42 Value Performance P1023/17 P1022/13 P1021/12 T1020/22 LS1xxx P1020//11 P1010/14 LS1 Family Existing 4Q 1Q 2Q 3Q 4Q 1Q 2012 Production Q 3Q 4Q 1Q 2Q 2014 Next generation Sample 9

10 Partitioning 1.0 Partitioning 1.1 Partitioning 2.0 Platform Partitionable Caches Snoop domains Topaz HV e500mc Hypervisor layer Platform I/O MMU I/O DPAA for multi-core simultaneous access Accelerators DPAA for multi-core simultaneous access I/O Partition-able I/O (SRIO, Interlaken) PCIe EP SRIOv Linux/KVM Linux Containers I/O Partition based buffer allocation (Ethernet, SRIO) 2 x threads = SWP External PCIe/SRIO virtualization Platform Interpartition messaging Dyn resource realloc I/O I/O Partition (Ethernet) Accelerators Inter-partition protection Partition resets Linux/KVM Linux Containers NG Core Virtualized Interrupts SW context-based QoS Guest timers Platform I/O MMUv2 (4k paging) PCIe RC SRIOv Virtualized DMA Virtualization 1.0 Virtualization 1.1 Virtualization 2.0 P4080/P5020/P3041 T4240 Next Gen 10

11 WLAN EAP Security Appliance Factory Automation SmartNIC Multiservice Gateway 11

12 Online Selector Tool Beyond Bits New friendly development tools Power on Tower PX-Series PowerQUICC QorIQ MQX Operating System QorIQ Configuration & Optimization Suites 12

13 e500mc E500v2 enhanced for multi-core Hypervisor, MMU TLB w/64 variable size DP FPU (classic), decorated L/S instructions CoreNet Coherency Fabric (2x snoop BW), L3 cache Up to 8 cores, 1.5GHz nominal L2 Cache e500mc P40xx, P30xx, P204x e500v2 CoreNet L3Cache 32b PPC-E SS, OOO, DI, 7st SPE & EFPU ECM Bus & Platform L2 Up to 2 cores, 1.5GHz nominal DDRC e5500 E500mc plus 64b ISA 2.06, 36b (64GB) per process Extended Branch Predictor Full speed DP FPU (classic) Larger L2 2.2GHz in 45SOI L2 Cache e5500 CoreNet L3Cache P5040, P5021, P5020, T1040 DDRC e6500 e5500 plus Dual SMT Thread 2 load/store per core (1 per thread) 4 issue (2 decode/completion per thread) 2x wide fetch AltiVec Banked L2 2.0GHz in 28nm many core v6 v6 v6 v6 L2 Cache T4240, T2080 CoreNet 2x BW L3Cache L3Cache DDRC DDRC e500 v2 L2 Cache DDRC MPC85xx, P10xx, P202x 13

14 Comp Buffer 14 GPR Complex Integer Unit Instruction Unit Inst Queu e FPR Simple Integer Unit 1 12 Rename Buffers Simple Integer Unit 2 CoreNet Bus Architecture Branch Prediction Unit CTR BTB LR 512 Entry Classic Single / Double FPU Store Queue Fetch Stages Load/Store Unit (64/32 bit) Data Line Fill Branch Buffer Execution Unit Load Miss Queue Data Write Buffer 36-bit Address Bus 128-bit Rd & Wr Data Buses Memory Unit 32-Kbyte I Cache 8-Entry L1 VSP Tags L1 Instruction MMU L2 MMU 64-Entry TLB Array (TLB 1) 8-Entry L1 VSP CoreNet L1 Data MMU Tags 64-Entry L1 TLB 4K 512-Entry TLB Array (TLB 0) 64-Entry L1 TLB 4K 32-Kbyte D Cache Backside L2 128K Tag & Status Arrays Power Architecture compatible Superscalar dual-decode, quad-issue: out-of-order execution/in-order completion 64 TLB SuperPages, 512-entry 4K Pages, 36-bit Physical Address Branch unit with a 512-entry, 4-way set associative Branch Target/History Three integer units: 2 Simple, 1 Complex for integer Multiply, Divide Data Array Embedded Hypervisor support Hypervisor privilege level Allows SMP/AMP operation without OS modifications Cache Enhancements 32-Kbyte Data and Instruction Caches w/ tag and data parity Recovery from single-bit L1 errors w/ Write shadow mode Back Side L2 w/ tag parity and ECC data 64byte cache lines Cache intervention, stashing and MESI cache coherency Cache line locking supported Classic Double Precision FPU Expanded interrupt model HW interrupt ACKs Interprocessor Signaling APU Msgsnd instruction and Doorbell interrupts Decorated Storage APU Lockless Atomic updates of shared counters and statistics Enhanced Debug Capabilities NEXUS Level II ++ Data trace lite Enhanced trace filtering Performance Monitor Watchpoint triggering 14

15 Complex Integer Unit Comp Buffer 14 GPR Simple Integer Unit 1 Inst Queu e 12 FPR Rename Buffers Instruction Unit Simple Integer Unit 2 Branch Execution Unit Fetch Stages Branch Prediction Unit CTR BTB LR 512 Entry Load/Store Unit (64/32 bit) Store Queue Data Line Fill Buffer Load Miss Queue Data Write Buffer Memory Unit 32-Kbyte I Cache L1 VSP Tags L1 Instruction MMU TLB Array (TLB 1) L1 VSP L2 MMU L1 Data MMU Tags 64-Entry L1 TLB 4K 512-Entry TLB Array (TLB 0) 64-Entry L1 TLB 4K 32-Kbyte D Cache 36-bit Address Bus 128-bit Rd & Wr Data Buses CoreNet Superscalar dual-decode, quad-issue: out-of-order execution/in-order completion 64 TLB SuperPages, 512-entry 4K Pages, 36-bit Physical Address Branch unit with a 512-entry, 4-way set associative Branch Target/History Three integer units: 2 Simple, 1 Complex for integer Multiply, Divide 64-bit Power Architecture Embedded hypervisor support Caches 32-Kbyte Data and Instruction Caches w/ tag and data parity Recovery from single-bit L1 errors w/ write shadow mode 512KB Back Side L2 w/ tag parity and ECC data 64byte cache lines Cache intervention, stashing and MESI cache coherency Cache line locking supported Classic Double Precision FPU Faster FPU: 2X faster SP, 4X faster DP over e500mc New Power ISA v.2.06 Instr instructions for byte- and bitlevel acceleration: Parity, population count, bit permute, compare bytes, FPU convert to/from 64-bit integer Enhanced Debug Capabilities 45-nm Technology 2 GHz Implementation point 20% DMIPS/MHz improvement over e500mc 15

16 Each thread: superscalar, seven-issue, out-of-order execution / in-order completion, branch units with a 512-entry, 4-way set associative branch target / history Execution units: 1 load / store unit per thread, 2 simple integer per thread, 1 complex for integer multiply & divide, 1 floating-point unit, AltiVec technology 64 TLB superpages, 1024-entry 4K pages, 36 or 40-bit physical Address 64-bit Power Architecture 28nm technology Superset of e5500 Two threads per core (SMT) Dual load / store units, one per thread Shared L2 in cluster of 4 cores (8 threads per cluster) 2048KB 16-way, 4 banks High-performance elink bus between to Ld/St and instruction fetch units Power Drowsy core and caches Power Mgt Unit Wait-on-reservation instruction Enhanced MP Performance Accelerated atomic operations Optimized barrier instructions Fast intra-cluster sharing AltiVec SIMD Unit CoreNet BIU 256-bit Din and Dout data busses 36/40-bit Real Address 1 Terabyte physical addr. space Hardware Table Walk LRAT Logical to Real Addr. Translation mechanism for improved hypervisor performance 16

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18 Observation: Quad decode / dispatch (2 per thread) Quad completion (2 per thread) 14 issue (7 per thread) 12 execution units 18

19 Compute Functions Networking Functions 19

20 Compute Functions Networking Functions 20

21 Data Center Ethernet Switch Based Fabric Network Services Security Management & Orchestration WAN Optimization Servers Storage ADC/SLB Monitoring 21

22 Requirement Freescale s Approach Data Virtualization Single Address space shared by multiple tenants. Configuration/Run time data on per tenant basis. Support large number of tenants, but no isolation. Process based virtualization Set of processes dedicated to a tenant. Efficient isolation and number of tenants support Container based virtualization Similar to process based virtualization. More isolation (file system, OS tunable, hostname) Decent number of containers Server Virtualization KVM/QEMU based virtualization. OS & Application instantiated for tenants. Very good isolation, but only few VMs are possible Multi Tenancy Hardware (Cores) Core performance still matters Focus on high performance, high IPC Hardware (DPAA) Leveraging data path for traffic management Associations with tenancy Hardware (Accelerators) Access to accelerators with minimal overhead Sharing of resources for performance Software Access to H/W + User space abstraction Efficient use of resources Target: Scalable & Efficient Performance 22

23 High Performance I/O Dual DDR3/3L Dual 10GbE 10x 1GbE PCIe Gen2.0 USB IFC Serial Peripherals 64-bit, 1600MT/s 24Gbps Classify, Parse, Distribute 3x PCIe controllers (5Gbps) Dual with integrated PHY Legacy ASIC connectivity & modern flash controller SATA, USB, UART, SPI, etc 23

24 Enterprise / Service Provider Equipment Fabric Controller Storage Networks Aerospace & Defense The P5040 and P5021 embedded processors were architected to provide maximum benefit for the target markets Balanced Architecture High-performance cores power efficiency Up to 64-bit addressable memory space Up to 2.4GHz with < 35W TDP CoreNet On-chip Fabric Designed to feed the cores Eliminates bus contention Optimizes efficiency of each core High Speed Interconnect PCIe, SGMII, XAUI, SATA, Aurora Tightly Coupled Cache Hierarchy Optimum memory architecture Cores are closer to the data to reduce latency Application-Specific Accelerators Provides optimum performance/power Security, Packet-processing offload, RAID5/6 24

25 Interlaken LA PCIe PCIe PCIe PCIe srio srio SATA 2.0 SATA 2.0 Pre-fetch T1 T2 T1 T2 T1 T2 T1 T2 T1 Power T2 T1 Power T2 T1 Power T2 T1 Power T2 e6500 T1 Power T2 e6500 T1 Power T2 e6500 T1 Power T2 e6500 T1 Power T2 Power e6500 Architecture Power e6500 Architecture Power e6500 Architecture Power e6500 Architecture 32 KB e KB 32 KB e KB 32 KB e KB 32 KB e KB D-Cache 32 KB I-Cache 32 KB D-Cache 32 KB I-Cache 32 KB D-Cache 32 KB I-Cache 32 KB D-Cache 32 KB I-Cache 32 KB D-Cache 32 KB I-Cache 32 KB D-Cache 32 KB I-Cache 32 KB D-Cache 32 KB I-Cache 32 KB D-Cache 32 KB I-Cache 32 KB D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache Security Fuse Processor Security Monitor 2x USB 2.0 w/phy IFC Power Management SD/MMC 2x DUART 2x I 2 C SPI, GPIO DCE 1.0 RMAN Security 5.0 Pattern Match Engine 2.0 2MB Banked L2 2MB Banked L2 2 MB Banked L2 Queue Mgr. Buffer Mgr. PAMU FMan PAMU Parse, Classify, Distribute 1/ 10G 10G 1/ 1G 1G 1G 1G 1G 1G CoreNet Coherency Fabric FMan PAMU Parse, Classify, Distribute HiGig DCB HiGig DCB 1/ 10G 10G 1/ 1G 1G 1G 1G 1G 1G 2xDMA 512KB CoreNet Platform Cache 512KB CoreNet Platform Cache 512KB CoreNet Platform Cache PAMU Peripheral Access Mgmt Unit 64-bit 64-bit DDR2/3 DDR3 Memory Memory Controller Controller 64-bit 64-bit DDR2/3 DDR3 Memory Memory Controller Controller 64-bit DDR2/3 64-bit DDR3 Memory Memory Controller Controller Real Time Debug Watchpoint Cross Trigger Perf CoreNet Monitor Trace Aurora 16-Lane 10 GHz SerDes 16-Lane 10 GHz SerDes 25

26 Virtualization Features Hypervisor Increased System Performance with added Security Cores have an extended address space and a hypervisor privilege mode to provide system security Virtualization Software Core Virtual CPU Allow guest operating systems to perform key operations safely with zero overhead Virtual CPU MMU Allows guest OS MMU management safely with zero overhead SoC Platform I/O MMU (PAMU) DPAA Mechanism to protect the system from unauthorized I/O devices Allows I/O peripherals, hardware accelerators and security devices to be shared 26

27 Tiered APM Hierarchy SoC Cluster Core Cache DDR PMC PMC AltiVec T T e K 32K Run, Doze, Nap Wait AltiVec drowsy Core drowsy (state retention) Dynamic clock gating Thermal Management Unit Die temp sensor U T4240 Die temp sensor 2048KB Banked L2 Run, Nap Dynamic frequency scaling Drowsy cluster Dynamic clock gating Die temp sensor Cascading Power Management DPAA CoreNet FMAN QMAN PMC SoC sleep with state retention Cascading power management Drowsy DDR/ self refresh Dynamic clock gating Energy Efficient Ethernet (EEE) 27

28 Enterprise / Service Provider Equipment Fabric Controller Storage Networks Aerospace & Defense The T4240 and T4160 AMP Processors are architected to provide Best in Class performance within an embedded power envelope Balanced Architecture High-performance dual threaded 64b cores Multicores up to 1.8GHz with 128b AltiVec Power Efficiency 4x performance of P4080 App Accelerators CoreNet On-chip Fabric Designed to efficiently feed the cores Eliminates bus contention High Speed Interconnect Next gen PCIe, Multiple XAUI, Interlaken LA SATA, Aurora Tightly Coupled Cache Hierarchy Optimum banked and tiered memory architecture Cores are closer to the data to reduce latency High-Performance Virtualization Advanced Core and SoC Software solutions designed for AMP 28

29 High Performance Cores and Memory Subsystem Power Architecture e6500 cores Up to 1.8 GHz Dual threaded with 128-bit AltiVec technology 2 MB shared L2 256 KB per thread, low latency 512 KB platform cache Shared DDR3/3L 64 bit + ECC, up to 2.1 GT/s, Memory pre-fetch engine 29

30 Enterprise Routers/Switches U Security Appliances Mobile Backhaul Aerospace & Defense The T2080 embedded processor was designed to provide maximum benefit for mid-range applications Dual-threaded e6500 core offers the highest CoreMark/watt rating Fixed function acceleration engines for application offload Secure Boot prevents box hacking and software IP theft Advanced virtualization for safe partitioning between control and data plane AltiVec engine for DSP-like calculations 30

31 High Performance Core/Caches Power Architecture e5500 core 256 KB/core L2 cache 256 KB platform cache Up to 1.4 GHz Hybrid 32-bit mode for legacy software support Supports up to 64 GB addressability 31

32 Enterprise Routers/Switches Industrial Computing and Networking U Security Appliances The T1042 embedded processor was architected to provide maximum performance per watt Highest performance CPU cores in the power envelop Offload engines industry highest IPSec in its class Deep packet inspection offload engine enabling U applications DPAA for QoS and balanced networking performance Virtualization to support customers and 3rd party software Small form factor, fanless and convection cooled designs 32

33 Increasing Performance P4080 T2080 Lower power 2x performance increase in same power range P3041, P2041 Lower power T1042 P1020 P2020 2x performance in same power range Decreasing Power (Watt) 33

34 Tools and Operating Systems Virtualization Application Software Systems Integration & Services Development Systems 34

35 Freescale is leading innovation in next-generation network infrastructure Best-in-class execution on QorIQ Industry leading reach and transparency. Exciting roadmap for the future Leadership in multicore for the next 10 years. Infrastructure to accelerate your design reference designs, collateral, new exciting products! 35

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