KeyStone C665x Multicore SoC

Transcription

1 KeyStone Multicore SoC Architecture

2 KeyStone C6655/57: Device Features C66x C6655: One C66x DSP Core at 1.0 or 1.25 GHz C6657: Two C66x DSP Cores at 0.85, 1.0, or 1.25 GHz Fixed and Floating Point Operations Backward-compatible with C64x+ and C67x+ cores Local L2 memory per core Multicore Shared Memory Controller () 32-bit DDR3 Interface Hardware Turbo Coprocessor Decoder () 2x Viterbi () Manager (8192 hardware queues) -based DMA Interfaces High-speed Hyperlink bus One 10/100/1000 port 4x Serial RapidIO () Rev 2.1 2x Gen2 2x Multichannel Buffered Serial Ports (McBSP) One Asynchronous Memory Interface (EMIF16) Additional Serials: SPI, C,, GPIO, ART Embedded Trace Buffer (ETB) and System Trace Buffer (STB) HyperLink EMIF16 GPIO C ART SPI McBSP C6655/57 Manager DMA Smart Reflex Enabled 40 nm High-Performance Process

3 KeyStone C6654: Optimized C66x C6654: One DSP Core at 850 MHz Fixed and Floating Point Operations Backward compatible with C64x+ and C67x+ cores C MB Local L2 memory Multicore Shared Memory Controller () 32-bit DDR3 Interface Manager (8192 hardware queues) -based DMA Interfaces One 10/100/1000 port 2x Gen2 2x Multichannel Buffered Serial Ports (McBSP) One Asynchronous Memory Interface (EMIF16) Additional Serials: SPI, C,, GPIO, ART MHz Embedded Trace Buffer (ETB) and System Trace Buffer (STB) Smart Reflex Enabled 40 nm High-Performance Process Manager DMA EMIF16 GPIO C ART SPI McBSP

4 KeyStone : Key HW Variations HW Feature C6654 C6655 C6657 Frequency (GHz) , , 1.0, 1.25 Multicore Shared Memory () No 1024KB DDR3 Maximum Data Rate Serial Rapid I/O Lanes No 4x HyperLink No Yes Viterbi Coprocessor (VCP) No 2x Turbo Coprocessor Decoder () No Yes

5 & AR RT McBS SP & 1 or 66x DSP Cores operating at up to 1.25 GHz Fixed andfloating Point Operations Code compatible with C64x+ and C67x+ L1 Memory Can be partitioned as cache or P per core D per core Error Detection for L1P Memory Protection Dedicated and Shared L2 Memory 1 MB local L2 per core Multicore Shared Memory Controller () 1 MB Multicore Shared Memory () for C6655/57 Error detection/correction for all L2 memory available to all cores and can be either program or data shared dby both thdsp C66x s for two core C Bit DDR3 External Memory Interface DDR (C6654) DDR (C6655/57) DDR (C6655/57) Secure

6 AR RT McBS SP & Multicore Shared Memory Controller () Arbitrates and SoC master access to shared memory Provides a direct connection to the Provides access to coprocessors (C6655/57) andio peripherals Memory protection and address extension to 64 GB (36 bits) Provides multi stream pre fetching capability DDR3 External Memory Interface (EMIF) Support for 1x 16 bit and 1x 32 bit Supports up to 1333 MHz (C6655/57) Supports power down of unused pins Support for 8 GB memory address Error detection and correction EMIF 16 Three modes: Synchronized NAND flash NOR flash Can be used to connect asynchronous memory (e.g., NAND flash) and provides up to 256 MB of address space.

7 AR RT McBS SP & Manager and DMA Low overhead processing and routing of packet traffic Simplified resource management Effective inter processor communications Abstracts physical implementation from application host software Virtualization to enable dynamic load balancing and provide seamless access to resources on different cores 8K hardware queues and 16K descriptors; More descriptors can reside in any shared memory 10 Gbps pre fetching capability

8 External Interfaces AR RT McBS SP & External Interfaces One port supports 10/100/1000 / Mbps Four high bandwidth Serial RapidIO ( V2.1) lanes for inter DSP applications Two Gen II Lanes at 5 Gbps Two Multichannel Buffered Serial Ports (McBSP) SPI for boot operations ART for development/testing Cfor EPROM at 400 Kbps niversal Parallel Port () Two channels of 8 bits or 16 bits Supports SDR and DDR transfers 32 GPIO Pins 16 Bit EMIF

9 Switch Fabric AR RT McBS SP & External Interfaces Switch Fabric is a process controller: Channel Controller Transfer Controller provides a configured way within hardware to manage traffic queues and ensure priority jobs are getting accomplished while minimizing the involvement of the DSP cores. facilitates high bandwidth communications between cores, subsystems, peripherals, and memory.

10 Diagnostic Enhancements AR RT McBS SP & External Interfaces Switch Fabric Diagnostic Enhancements Embedded Trace Buffers (ETB) enhance the diagnostic capabilities of the. CP Monitor enables diagnostic capabilities on data traffic through the switch fabric. Diagnostic functions supported: Automatic statistics collection and exporting (non intrusive) Monitorindividual individual events forbetter debugging Monitor transactions to both memory end point and MMRs (Memory Mapped Registers) Configurable monitor filtering capability based on address and transaction type

11 HyperLink Bus & External Interfaces Switch Fabric Diagnostic Enhancements HyperLink Bus Provides the capability to expand the C66x to include hardware acceleration or other auxiliary processors Four lanes with up to 40 Gbaud per lane AR RT McBS SP

12 Miscellaneous Elements AR RT McBS SP & External Interfaces Switch Fabric Diagnostic Enhancements HyperLink Bus Miscellaneous Elements Public and secure capability 2provides provides atomic accessto shared chip level resources. Eight 64 bit timers Security/ Two on chip s: 1 for s 2 for DDR3

13 For More Information For more information, refer to the C66x Multicore Home Page to locate the data manual for your KeyStone device. View the complete C66x Multicore SOC Online Training for KeyStone Devices, including details on the individual modules. For questions regarding topics covered in this training, visit the support forums at the TI E2E Community website.