QorIQ Advanced Multiprocessing (AMP) Series

Transcription

1 October 2013

2 T4240/T4160 (28nm) NEW QorIQ Advanced Multiprocessing (AMP) Series Multithreaded cores, advanced fixed function processing integration, power-saving techniques, virtualization, 28nm process technology 70+ products 3 products (45nm) 23+ products (45nm) Industry s first comprehensive portfolio of multimode solutions; Digital Signal Processing & Microprocessor fusion Scalable multicore communications processors high fixed function processing integration, 45nm process technology. Power Architecture cores, QUICC engine multiprotocol packet processing and security processing acceleration Broad portfolio with on-time, on-specification release track record Software and tools ecosystem catering for Tier1 and broad market customers Common software tool sets including CodeWarrior Development Suite Open, rich third-party ecosystem for operating system, tools and application software 2

3 Emerging Established The T4 family extends Freescale s market leadership in communications processors #1 in Embedded Microprocessors 45% #1 in Communications Processors 53% Seamless Migration 4x Performance 2x Power Efficiency Service Provider RNC, GW, RAN, Metro Enterprise Router, Switch, eap Aero/Defense Navigation, networking And enables new categories of applications in emerging public and private cloud data center networking Virtualization Internet Acceleration Convergence Data Center Switching, ADC, WOC, Security, Virtualized Smart NIC Storage HBA, Sys Controller Converged Networking Source: Gartner, Inc. Market Share: Semiconductor Applications, Worldwide, March 30,

4 PMC PMC PMC PMC AltiVec T T e K 32K AltiVec T T e K 32K AltiVec CoreNet Interface 40-bit Address Bus 256-bit Rd & Wr Data Busses CoreNet Double Data Processor Port AltiVec T 32K T e6500 2MB 16-way Shared L2 Cache, 4 Banks T T e K 32K 32K High-Performance Industry s highest CoreMark score Industry s best CoreMark per Watt 64-bit Power Architecture core Dual strong threads provide 1.7 times the performance of a single thread Clustered L2 cache allowing strict allocation or full sharing 128b AltiVec SIMD unit 192 GFLOP aggregate Core Performance: Coremark / Watt Benchmark 3x 1.4x T Industry s Best CoreMark Score CoreMark per Watt Large Memory Space 40-bit real address Terabyte physical address Increase Productivity Core Virtualization Hypervisor Logical to Real Address Translation Dual 6 core (12 thread) server 2.266GHz * 32 core 1.5GHz* 12 core (24 thread) 1.8GHz Energy Efficiency 1.4 to 3 times more power efficient than the nearest competition Drowsy: core, cluster, AltiVec CoreMark / Watt 4 *Source:

5 Core Complex High Performance I/O Interconnect Fabric 50Gbps Networking and HW Acceleration T4240 T4160 Core Clusters 3 2 DDR Memory Controllers G Serdes Lanes GbE MAC 4 2 Typical Power (with IO) 30W 25W 5

6 Compress and Decompress traffic across the Internet Protects against internal and external Internet attacks Frees CPU from draining repetitive RSA, VPN and HTTPs traffic Identifies traffic and targets CPU or accelerator Hardware Accelerators FMAN Frame Manager BMAN Buffer Manager QMAN Queue Manager RMAN Rapid IO Manager SEC Security PME Pattern Matching DCE Data Compression 50 Gbps aggregate Parse, Classify, Distribute 64 buffer pools Up to 2 24 queues Seamless mapping srio to DPAA 40Gbps: IPSec, SSL Public Key 25K/s 1024b RSA 10Gbps aggregate 20Gbps aggregate Saving CPU Cycles for higher value work New Enhanced 6

7 Discard Probability Provide sharing of network interfaces and hardware accelerators by multiple cores Reduce software overheads associated with managing and moving work Congestion management and avoidance for higher data rates and distributed processing Hardware acceleration offload for compute-intensive tasks classifying, encryption, content processing The QorIQ Datapath Acceleration Architecture (DPAA) provides this infrastructure Congestion Mgmt Policing Context Pre-fetch L1 Aggregate Q Occupancy CPU MMU L1 QMan Parse FMan Manage Work Q BMan... Frame Manager Parse, Classify, Distribute Buffer 1GE 1GE 1GE 1GE 10GE 10GE 1GE 1GE 1GE 1GE Classify Distribute HW Acceleration SEC PME DCE RMAN 7

8 Line rate 50Gbs Networking Chip to Chip Communication with seamless mapping to DPAA Networking Advance I/O Lower System Cost Quad 10GbE 16x GbE Energy Efficient Ethernet (EEE) Datacenter Bridging 50Gbps Classify, Parse, Distribute IEEE802.3az Priority Flow Control (PFC, IEEE 802.1Qbb) Enhanced Transmission Selection (ETS, IEEE 802.1Qaz) Data Center Bridging Exchange Notification (DCBX) Quality of Service for FCoE in converged data center networking PCIe rev 3.0 with SR-IOV for virtualized x86 server host Interconnect srio PCIe rev 2.0/3.0 PCIe SR-IOV Interlaken-LA1 USB IFC Serial Peripherals Dual, seamless mapping to DPAA Quad PCIe controllers Endpoint IO virtualization External TCAM/ network search engine connectivity Dual with integrated PHY Legacy ASIC connectivity & modern flash controller SATA, USB, UART, SPI, etc New Enhanced 8

9 Virtualization Features Hypervisor Increased System Performance with added Security Cores have an extended address space and a hypervisor privilege mode to provide system security Virtualization Software Core Virtual CPU Allow guest operating systems to perform key operations safely with zero overhead Virtual CPU MMU Allows guest OS MMU management safely with zero overhead SoC Platform I/O MMU (PAMU) DPAA Mechanism to protect the system from unauthorized I/O devices Allows I/O peripherals, hardware accelerators and security devices to be shared 9

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11 Core SoC DMIPS/ MHz e6500 2T comparison MHz Core total DMIPS e6500 2T comparison Product No. of cores in a product Product DMIPS T4240 2T comparison e6500 1T T e6500 2T T e P e500mc P e500v MPC e MPC8641D

12 EEMBC v1 Auto EEMBC v1 Consumer EEMBC v1 Networking Relative Core Performance e500mc 1.5Ghz e GHz ST e GHz DT EEMBC v1 Office EEMBC v1 Telecom EEMBC v2 Networking IPmark ~2.5 x speedup e500mc e6500dt EEMBC v2 Networking TCPmark EEMBC v1 Auto EEMBC v1 Consumer Relative Device Performance P Ghz T GHz ST T GHz DT EEMBC v1 Networking EEMBC v1 Office EEMBC v1 Telecom EEMBC v2 Networking IPmark ~3.7 x speedup P4080 T4240 DT EEMBC v2 Networking TCPmark 12

13 Data Center application and network processing Processing density Power & energy efficiency Virtualization CoreMark Processor AKA Threads Freq (GHz) Temp range Compiler Test method T4240 QorIQ AMP 24:Pthreads C Tj max GCC4.6.0 emulation T4240 QorIQ AMP 24:Pthreads C Tj max GCC4.6.0 emulation Core i *^ Sandy Bridge 12:Pthreads C case max GCC4.4.6 silicon Core i *^ Sandy Bridge 4:Pthreads C case max GCC4.4.5 silicon Watts Power and CoreMark T4240 T4240 Core i7- Tj=105C Tj=75C 3930K TPD Power Core i Score Aggregate CoreMark 200, , ,000 50,000 0 QorIQ Processors implement more than just General purpose processing Integrated networking datapath Hardware acceleration Crypto Reg-ex Compression compute density per blade at equivalent power Dual Socket Server i7 i7 T4240 Quad T4240 Sexuple T4 T4 T4 T4 T4 T4 T4 T4 T4 T4 CoreMark score from coremark.org ^ TPD From ** T4240 power are estimates I7 CPUs 260W => ~300K Coremark T4s 240W** Tj 105C => ~700K Coremark T4s 234W** T j75c=> ~1040K Coremark 13

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15 Power = Dynamic + Static Dynamic power is related to the activity performed and mainly due to: Charging/discharging capacitor load Dynamic hazards switching glitches Short-circuit currents Static power is not activity related and mainly due to: Drain leakage Junction leakage Gate leakage Power = Capacitance x Frequency x Voltage 2 + Current C x Voltage S G D oxide n+ n+ p Dynamic Static 15

16 SoC Cluster Core Cache DDR PMC PMC Tiered APM Hierarchy Thermal Management Unit Altivec T T e K 32K Run, Doze, Nap Wait Altivec drowsy Core drowsy (state retention) Dynamic clock gating Die temp sensor U T4240 Die temp sensor Die temp sensor 2048KB Banked L2 Run, Nap Dynamic frequency scaling Drowsy cluster Dynamic clock gating DPAA CoreNet FMAN QMAN PMC Cascading power management Dynamic clock gating Energy Efficient Ethernet (EEE) Low Power Operation T4240: 30W* T4160: 25W* *Typical application power with IO 16

17 Today: All CPUs in Pool Channel dequeue until all FQs empty. Broadcast notification when work arrives. P0 P1 P2 P3 AMP Series: DPAA uses task queue thresholds to inform CPUs they are not needed. CPUs selectively awakened as needed. P0 P1 P2 P3 Drowsy Drowsy Shared L2 Shared L2 Task Queue T5 T4 T3 T2 T1 Threshold 2 Threshold 1 QMan Active CPUs Day Burst Night 17

18 Product Configuration Power Mode Core Freq (GHz) Plat Freq (MHz) DDR Datarate (GHz) Core + Platform + SVDD Power (W) T4240 Typ (65C) Thermal (105C) Max (105C) Typ (65C) Thermal (105C) Max (105C) Core + Platform + SVDD + IO Power (W) T4160 Typ (65C) Thermal (105C) Max (105C) Typ (65C) Thermal (105C) Max (105C) Power Estimates: reference Datasheet for actual values 18

19 60 T GHz thermal power max estimates Power vs Cores PWR vs Tj Watts (Core+Logic) Watts (Core+Logic) # of Non-Drowsy Cores Tj (Celsius) Power Estimates: reference Datasheet for actual values 19

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21 General Purpose Dev System T4240QDS T4240RDB T4240PCIe T4240 ATCA T4240 VPX Full features development Full features of T4 exposed Extensive system debugging Low Cost 1U development platform Evaluation Linux developer Prototype application Used by typical customer who use T4 in Datacenter applications Evaluation Development Production Wired and Wirelss service provider applications Evaluation Development Production T4 for Aero/Defense designs Evaluation Development Production General Purpose Development System Enterprise and Datacenter appliance Datacenter Telecom Aerospace & Defense System Solutions 21

22 IFC Card NAND ADM NOR NOR PromJet MUX XAUI / HiGig / (Q)SGMII XAUI / HiGig / (Q)SGMII Slot 1: x8 Slot 2: x8 XBAR SD1 DDR1 DDR2 DDR3 DDR3/3LP 240p DDR3/3LP 240p DDR3/3LP 240p DDR3/3LP 240p DDR3/3LP 240p DDR3/3LP 240p XAUI / HiGig / (Q)SGMII / XFI XAUI / HiGig / (Q)SGMII Slot 3: x8 Slot 4: x8 XBAR SD2 GVDD DVDD/ etc. PMBus PWR LDO PWR 1.5V/1.35V PEX / Interlaken PEX / SRIO PEX PEX / SRIO / SATA Slot 5: x16 Slot 6: x8 Slot 7: x16 Slot 8: x8 Aurora XBAR XBAR SD3 SD4 VDD SVDD/ XVDD I2C1 VID 4Φ PWR LDO PWR I2C Route + Volt. Trans PMBus, Slots, Devs, etc. RMT SATA JTAG CCS cfg_xyz IDT IDT IDT 841NT IDT 841NT 841NT 841NT4 SDxCLKx T4240 QIXIS FPGA DDRCLK (option) IDT 840NT4 SYSCLK DDRCLK NET1 NET2 Symmetricom IEEE 1588 IDT 840NT4-01 PHYs 1588_CLKOUT 1588_CLKIN GTX_CLK125x USBCLK TSEC IFC UART SPI ISO SPI SPI XCVR SER1 SER2 USB1 USB2 PROT USB SDHC PROT SDHC emmc 22

23 PHY PHY DDR3/3L Flash DDR3/3L DDR3/3L x64 Status LEDs DC/DC Subsystem UART UART USB USB e6500 e6500 Cluster e6500 Cluster Cluster T4240 3x DDR Controller 10 GbE 10 GbE 10 GbE 10 GbE PME SEC DCE 1 GbE 1 GbE 1 GbE 1 GbE 1 GbE 1 GbE GPIO PCIe x1 PCIe x4 1 GbE 1 GbE minipcie Slot X16 Pcie slot Offline Switcher esdhc SATA SATA 4 XFI 8 SGMII SATA esata Quad SFP+ Quad PHY 10GBaseT PHY 1000BaseT USB USB Front RS232 Link LED Pwr Rear RS232 SD 8x 1000BaseTX 4x SFP+ 4x 10GBaseTX 23

24 Full height, ½ length 2GB e-mmc 1x micro SD slot 2x SATA HDD 3x DIMM Slots - 1G DIMM x8 PCIe connector 1x minipci express slot 24

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26 USB USB Uart 0:4 GPIO IO/Mezzanine Data Plane USB USB Uart 0:4 GPIO Expansion plane PCI-E x4 PCIx Bridge PMC GbE USB UART 10G-KR SGMII IFC FPGA T4240 3x DIMM Memories PCI-E x4 srio x4 srio x4 PCI-E x4 PCI-E PEX8648 srio IDT1848 PCI-E x8 PCI-E x8 srio x4 srio x4 srio x4 srio x4 Ethernet XFI PCI-E 1G Ethernet srio x4 USB UART GbE IFC T4240 3x DIMM srio x4 srio x4 USB UARTS GPIO USB UART SGMII x4 10GbaseKR x 4 26

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