CMOS Inverter & Logic Lab ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING. CMOS Inverter Lab

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1 ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING CMOS Inverter Lab Dr. Lynn Fuller Webpage: 82 Lomb Memorial Drive Rochester, NY Tel (585) MicroE webpage: CMOS_Inv_Logic_Lab.ppt Page 1

2 INTRODUCTION In this lab we will investigate the CMOS Inverter VTC. We will also investigate a CMOS 3 input NAND truth table and VTC. Page 2

3 VIN +V CMOS PMOS VO NMOS CMOS - CALCULATION OF VTC +V First figure out if the transistor is sub-threshold or off, Vgs < Vth and Vgd < Vth non-saturation, Vgs > Vth and Vgd > Vth saturation region, Vgs > Vth and Vgd < Vth 0 VOUT 0 nmos off nmos sat pmos linear nmos & pmos saturation Vthn pmos sat nmos linear V-Vthp pmos off +V VIN Note: Vin Rochester = Institute Vgs, of Vout Technology = Vds, therefore Vgd = Vin-Vout Vth might be +1volt Page 3

4 CMOS INVERTER VOUT VIN +V Idd VOUT +V Voh Imax Slope = Gain VIN VO Idd CMOS VoL 0 0 ViL Vinv NML, Rochester noise Institute of margin Technology low, D0 =ViL-VoL NMH, noise margin high, D1 =VoH-ViH Vih +V VIN Page 4

5 VTC CMOS INVERTER Note: W = 6.5u gives best noise margin Page 5

6 LTSPICE CMOS INVERTER NML, noise margin low, D0 =ViL-VoL = = 1.7 NMH, noise margin high, D1 =VoH-ViH = = 2.0 Page 6

7 COMPARISON OF 10u, 1u AND 100n CMOS INVERTERS VDD = 5 volts VDD = 3.3 volts VDD = 2.5 volts Imax=5.4mA Imax=100uA Imax=21uA Gain=-90 Gain=-33 Gain=-6 RITALDN3/RITALDP3 L=10u W=880u L=10u W=880u RITSUBN7/RITSUBP7 Ln=1u Wn=2u Lp=1u Wp=2u EECMOSN/EECMOSP Ln=180n Wp=200n Ln=180n Wp=200n Page 7

8 VTC FOR 3-INPUT NAND The three NMOS transistors each have different source to substrate voltages which will change the threshold voltage of those transistors and as a result will change the VTC depending on which transistors are switching. This causes a horizontal shift in the VTC. VA VB VC NAND +V VA M2 M3 M1 VOUT VB VC VA VB VC NAND VOUT Page 8

9 3-INPUT NAND Vout2 Vout1 +V VA M1 M2 M3 VOUT VB VC Vout1 has M2 and M3 NMOS on and M1 NMOS switching Vout2 has M1 Rochester and Institute M2 of Technology NMOS on and M3 NMOS switching Other combinations are also possible. Page 9

10 LABORATORY TASKS [ ] Measure the VTC of the CMOS inverter. [ ] Double width of PMOS in the CMOS inverter by connecting two PMOS in parallel. Then measure the VTC. [ ] Verify truth table for 3-input NAND [ ] Obtain the VTC for the 3-input NAND with all inputs tied together. [ ] Obtain the VTC for the 3-input NAND with A and B high and sweep C [ ] Tie all three inputs together and set the voltage to VDD/2 Measure the current (use multi-meter and 10 ohm resistor) Measure the internal node voltages at the source of the three NMOSFETs Page 10

11 SUMMARY This laboratory provides the student an opportunity to evaluate CMOS logic. Specifically the Voltage Transfer Curves (VTC) of the inverter and the three input NAND. Page 11

12 REFERENCES 1. Circuits, Fifth (or Sixth) Edition, Adel Sedra and Kenneth Smith, Oxford University Press, Analysis and Design of Digital Integrated Circuits, Hodges, Jackson and Saleh, McGraw Hill, 3 rd Edition Device Electronics for Integrated Circuits, 2nd Edition, Kamins and Muller, John Wiley and Sons, The Bipolar Junction Transistor, 2nd Edition, Gerald Neudeck, Addison-Wesley, Page 12

13 SPICE MODELS FOR CD4007 MOSFETS *SPICE MODELS FOR RIT DEVICES - DR. LYNN FULLER *LOCATION DR.FULLER'S WEBPAGE - * *Used in Electronics II for CD4007 inverter chip *Note: Properties L=10u W=170u Ad=8500p As=8500p Pd=440u Ps=440u NRD=0.1 NRS=0.1.MODEL RIT4007N7 NMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=4E-8 XJ=2.9E-7 NCH=4E15 NSUB=5.33E15 XT=8.66E-8 +VTH0=1.4 U0= 1300 WINT=2.0E-7 LINT=1E-7 +NGATE=5E20 RSH=300 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-8 MJ=0.5 PB=0.95 +CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5 +CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10) * *Used in Electronics II for CD4007 inverter chip *Note: Properties L=10u W=360u Ad=18000p As=18000p Pd=820u Ps=820u NRS=O.54 NRD=0.54.MODEL RIT4007P7 PMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=5E-8 XJ=2.26E-7 NCH=1E15 NSUB=8E14 XT=8.66E-8 +VTH0=-1.65 U0= 400 WINT=1.0E-6 LINT=1E-6 +NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-8 MJ=0.5 PB=0.94 +CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 pclm=5 +CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10) Page 13

14 SPICE MODELS FOR MOSFETS * From Sub-Micron CMOS Manufacturing Classes in MicroE ~ 1um Technology.MODEL RITSUBN7 NMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=1.5E-8 XJ=1.84E-7 NCH=1.45E17 NSUB=5.33E16 XT=8.66E-8 +VTH0=1.0 U0= 600 WINT=2.0E-7 LINT=1E-7 +NGATE=5E20 RSH=1082 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95 +CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5 +CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10) * *From Sub-Micron CMOS Manufacturing Classes in MicroE ~ 1um Technology.MODEL RITSUBP7 PMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=1.5E-8 XJ=2.26E-7 NCH=7.12E16 NSUB=3.16E16 XT=8.66E-8 +VTH0=-1.0 U0= WINT=2.0E-7 LINT=2.26E-7 +NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-4 MJ=0.5 PB=0.94 +CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 +CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10) Page 14

15 SPICE MODELS FOR MOSFETS * LTSPICE uses Level=8 * From Electronics II EEEE482 FOR ~100nm Technology.model EECMOSN NMOS (LEVEL=8 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=5E-9 XJ=1.84E-7 NCH=1E17 NSUB=5E16 XT=5E-8 +VTH0=0.4 U0= 200 WINT=1E-8 LINT=1E-8 +NGATE=5E20 RSH=1000 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95 +CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5 +CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10) * * LTSPICE uses Level=8 * From Electronics II EEEE482 FOR ~100nm Technology.model EECMOSP PMOS (LEVEL=8 +TOX=5E-9 XJ=0.05E-6 NCH=1E17 NSUB=5E16 XT=5E-8 +VTH0=-0.4 U0= 100 WINT=1E-8 LINT=1E-8 +NGATE=5E20 RSH=1000 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-4 MJ=0.5 PB=0.94 +CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 PCLM=5 +CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10) * Page 15