Micro transductors 08

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1 Micro transductors 8 CMOS Basics Dr.-Ing. Frank Sill Department of Electrical Engineering, Federal University of Minas Gerais, Av. Antônio Carlos 6627, CEP: 327-, Belo Horizonte (MG), Brazil franksill@ufmg.br

2 Announcement Next class: Thursday, 3. March Room 38 CCE Micro transductors 8, CMOS Basics 2

3 Optional Topics Please, choose 2 out of the following 4 topics Final date: 4 th of March. Future trends in VLSI design 2. Basics of Hspice-Simulations 3. Effects in nanometer CMOS circuits 4. Reliability problems in current and future designs Micro transductors 8, CMOS Basics 3

4 Goals Where do we find Integrated Ciruits? History and Trends CMOS: basic ideas Logic gates Delay estimation Sizing Micro transductors 8, CMOS Basics 4

5 Where do we find chips? Computer are the workhorses of the semiconductors industry. % 8% Processors Memory Logic Motivation Performance Flexibility Mobility 6% 4% 2% Analog Discretes Optoelectronics/ Sensors/Bipolar ~ 2 % are processors ~ 6.5 Billion processors per year ~ 4 % of all parts are used in the PC area % Units Revenue Source: WSTS 2 Micro transductors 8, CMOS Basics 5

6 Scenarios Obviously tasks High performance demands Fast execution Micro transductors 8, CMOS Basics 6

7 Scenarios cont d Hidden helper Low performance demands Micro transductors 8, CMOS Basics 7

8 History 96 Semiconductors used to detect radio signals 925 FET concept patent by J. Lilienfeld 94 Z3 by Konrad Zuse first computer 946 ENIAC first electronic computer 947 Transistor Invented AT&T ignores Lilienfeld Bardeen, Brattain and Schockley, AT&T, Nobel Prize in Integrated Circuit Kilby & Noyce (died 99) Kilby - Noble Prize in MOSFET manufactured and patented CMOS logic invented Resistors replaced by transistors Micro transductors 8, CMOS Basics 8

9 History cont d Zuse Z3 First computer* (94) First working programmable, fully automatic computing machine 2, Relays Clock frequency of ~5 - Hz Word length of 22 bits Programmed by punched film stock Addition, Multiplication, Division, Square root * Elected at st International Conference on the History of Computing" in Paderborn, Germany, 998 Micro transductors 8, CMOS Basics 9

10 History cont d ENIAC First electronic computer (946) Electronic Numerical Integrator And Computer At Moore School of Electrical Engineering, University of Pennsylvania 7,468 vacuum tubes, 7,2 diodes (+ ca. 8k resistors & capacitors) 5 Million hand-soldered joints Micro transductors 8, CMOS Basics

11 History cont d Vacuum Tubes in ENIAC Micro transductors 8, CMOS Basics

12 History cont d (a) First transistor (947, Bardeen & Brattain, Bell labs) (b) First integrated circuit (958, Kilby, AT&T) Source: Weste, CMOS VLSI design,23 Micro transductors 8, CMOS Basics 2

13 Moore s Law Prediction by Gordon Moore in 965 Semiconductor technology will double its effectiveness every 8 months Year Micro transductors 8, CMOS Basics Log2 of the Number of Components Per Integrated Function Source: Moore, 665 Log2 of number of components per integrated function

14 Moore s s Law cont d Source: Moore, ISSCC 23 Micro transductors 8, CMOS Basics 4

15 Trend: Cost per function Price of a transistor Micro transductors 8, CMOS Basics 5

16 Trend: Performance MIPS,, Pentium 4 proc 386 Pentium proc TIPS Source: Moore, ISSCC 23 Micro transductors 8, CMOS Basics 6

17 Trend: Power Source: Moore, ISSCC 23 Micro transductors 8, CMOS Basics 7

18 Trend: Power Density Sun s Surface Power Density (W/cm2) Nuclear Reactor Hot Plate Rocket Nozzle P4 Pentium Prescott Pentium Year Source: Moore, ISSCC 23 Micro transductors 8, CMOS Basics 8

19 Dimensions mm cm µm mnm Source: Spektrum der Wissenschaften 65 nm -Transistor Source: Intel Micro transductors 8, CMOS Basics 9

20 The CMOS Technology CMOS = Complementary Metal Oxide Semiconductor Currently most applied logic family Main advantages: Low Power (compared to other technologies) Very good scalability High Speed High packaging density Micro transductors 8, CMOS Basics 2

21 Main Idea: The CMOS Technique cont d Combination of two complementary switches Switches are metal-oxide-semiconductor field-effect transistors (MOSFET) Realization of logic gates (AND, NAND, ) Metal Oxide Semiconductor : Physical structure of MOSFETs (metal gate electrode, oxide insulator, semiconductor material) Today: polysilicon instead of metal Micro transductors 8, CMOS Basics 2

22 What is a transistor? S D Source: Rabaey, Digital Integrated Circuits,995 Micro transductors 8, CMOS Basics 22

23 PMOS and NMOS Source: Rabaey, Digital Integrated Circuits,995 Micro transductors 8, CMOS Basics 23

24 NMOS-Transistor Source Gate Drain Polysilicon SiO 2 n+ p n+ bulk Si S G Body is (commonly) tied to ground ( Body is (commonly) tied to VDD Source: Rabaey, Digital Integrated Circuits,995 Micro transductors 8, CMOS Basics 24

25 NMOS-Transistor (2) polysilicon gate W Gate-width t ox L n+ n+ p-type body SiO 2 gate oxide (good insulator, e ox = 3.9 t ox thickness of oxide layer Gate length Source: Rabaey, Digital Integrated Circuits,995 Micro transductors 8, CMOS Basics 25

26 Cross section of NMOS and PMOS Source: Weste, CMOS VLSI design,23 Micro transductors 8, CMOS Basics 26

27 Layout Mask Set Transistors and wires are defined by masks Cross-section taken along dashed line A Y GND V DD substrate tap nmos transistor pmos transistor well tap Micro transductors 8, CMOS Basics 27

28 I-V V Curves of NMOS I ds V ds V gs Source: Weste, CMOS VLSI design,23 Micro transductors 8, CMOS Basics 28

29 Threshold Voltage V th Transistor characteristic If: Gate-Source -Voltage V gs higher than V th Channel under Gate Current between Drain and Source Source V gs > V th Gate I ds Drain If: V gs lower than V th No current Micro transductors 8, CMOS Basics 29

30 Logic Gates Task (e.g. calculation) Transfer into Logic Gates (Synthesis) Gate characteristics: Delay Power dissipation more... Gates realized by transistors Transistors determine gate characteristics Y = A+B Micro transductors 8, CMOS Basics 3

31 Example: Half-adder adder How do you add the two bits A and B in binary logic? A B Result Carry Sum So called Half-adder: In (A ) In2 (B ) AND XOR Micro transductors 8, CMOS Basics 3

32 CMOS Scheme VDD (supply voltage) PUN Pull-up Network PDN Pull-down Network GND (ground) Micro transductors 8, CMOS Basics 32

33 CMOS Inverter VDD IN (GND) (VDD) OUT (VDD) (GND) GND Micro transductors 8, CMOS Basics 33

34 Transistor as Water-tap tap Micro transductors 8, CMOS Basics 34

35 Transistor as Water-tap tap cont d Voltage (Volt, V) Water pressure (bar) Current (Ampere, A) Water quantity (liter) Volt Volt Volt Volt Volt Volt Volt? Volt Volt Volt? Volt Volt Volt Volt Source: Timmernann, 27 Micro transductors 8, CMOS Basics 35

36 NAND Gate Pull-up Network In In2 PUN PDN Out OFF ON ON OFF ON OFF ON ON Pull-down Network Micro transductors 8, CMOS Basics 36

37 NOR Gate Pull-up Network In In2 PUN PDN Out OFF ON OFF ON OFF ON Pull-down Network ON OFF Micro transductors 8, CMOS Basics 37

38 AND and OR Gate AND In In2 Out AND Out NAND NAND INV OR In In2 Out OR Out NOR NOR INV Micro transductors 8, CMOS Basics 38

39 Delay Definitions V in V out V in input waveform 5% Propagation delay t p t phl t plh t V out output waveform 5% 9% signal slopes t f % t r t Micro transductors 8, CMOS Basics 39

40 RC-Delay Model Simple but effective delay model Use equivalent circuits for MOS transistors Ideal switch Transistor capacitances ON resistance ( = when transistor is conducting (=ON) channel between Drain to Source acts as resistor) Delay t ~ R*C Micro transductors 8, CMOS Basics 4

41 MOSFET capacitances Any two conductors separated by an insulator create a capacitor MOS capacitances have three origins: The basic MOS structure The channel charge The pn-junctions depletion regions Gate Source CGS CGB CGD Drain CSB CDB Bulk Bulk Micro transductors 8, CMOS Basics 4

42 RC-Delay Model: Inverter Rising Slope C P,gate R P,DS C N,gate X C out Micro transductors 8, CMOS Basics 42

43 RC-Delay Model: Inverter Falling Slope C P,gate X C out R N,DS C N,gate Micro transductors 8, CMOS Basics 43

44 RC-Delay Model: Inverter cont d Where does C out come from? Input capacitance (= gate capacitances) of following gate Diffusion capacitances (Drain-Bulk) of PMOS- and NMOS transistors C P,gate C P,DB C N,DB C out C N,gate Micro transductors 8, CMOS Basics 44

45 RC-Delay Model: Width Gate width W can be changed by Designer (L, T ox, V DD are fixed) Capacitance proportional to width: C ~ W Resistance inversely proportional to width: R ~ / W Resistance of NMOS approx. two times smaller than PMOS with same width: N N P N P N C P = 2*C N! Micro transductors 8, CMOS Basics 45

46 RC-Delay Model: Fanout fanout f = C C : load in Micro transductors 8, CMOS Basics 46

47 RC-Delay Model: Rising Slope C P,gate W P =2n XW N =n C N,gate C P,DB RNDS,, RPDS, WN C load C N,DB R = = 2R W C = C W, C = C W NDB, N Ngate, N C = C W, C = C W P, DB P P, gate P P ( ) t = RC = R C + C + C ( C W C W f C ) ( 2 3 ) ( f ) PDS, NDB, PDB, load 2R = + + W P N P in 2R = nc + nc + nfc 2n = 3+ R C Micro transductors 8, CMOS Basics 47

48 RC-Delay Model: Falling Slope C P,gate X W P =2n C N,gate W N =n C P,DB RNDS,, RPDS, WN C load C N,DB R = = 2R W C = C W, C = C W NDB, N Ngate, N C = C W, C = C W P, DB P P, gate P P N ( ) t = RC = R C + C + C ( C W C W f C ) ( 2nC nc 3nfC ) ( f ) NDS, PDB, NDB, load R = + + W R = n + + = 3+ R C P N in Micro transductors 8, CMOS Basics 48

49 RC-Delay Model: Examples Delay of an Inverter with a fanout of 64: t= 3+ f RC ( ) = 3( + 64) R C = 95 RC Micro transductors 8, CMOS Basics 49

50 RC-Delay Model: Examples cont d Chain of Inverters with C load = 92 C and C in =3 C C in =3 C INV INV2 INV3 C load =92 C C f = = 64 = f f f load, chain chain INV 3 INV 2 INV Cin, chain C C C C C C = = C, C, C, C, C, C, load, INV 3 load, INV 2 load, INV load, chain in, INV 3 in, INV 2 in INV 3 in INV 2 in INV in INV 3 in INV 2 in chain t = t + t + t chain INV INV 2 INV 3 [ ] = 3 RC ( + f ) + ( + f ) + ( + f ) INV INV 2 INV 3 Micro transductors 8, CMOS Basics 5

51 RC-Delay Model: Examples cont d Chain of Inverters with C load = 92 C and C in =3 C C in =3 C INV INV2 INV3 C load =92 C f =, f =, f = 64 t INV INV 2 INV 3 chain,,64 = 27 R C f = 4, f = 4, f = 4 t INV INV 2 INV 3 chain4,4,4 = 45 R C Chain of Inverters: Optimum result (for speed) at equal fanout! Micro transductors 8, CMOS Basics 5

52 Chains of Inverters Micro transductors 8, CMOS Basics 52

53 Sizing Increasing Width Resistance get down Increasing current Decreasing delay BUT Capacitance increase too Internal capacitances increase + Output load of previous gates increases Micro transductors 8, CMOS Basics 53

54 Sizing for Performance Sizing (W ) auch interne Kapazität (Cdb,PMOS, Cdb,NMOS) = > größer Effekt von Sizing sinkt! Source: Irwan, PSU, 2 Micro transductors 8, CMOS Basics 54

55 Alpha Power Law Model t t rise fall k' CL VDD = (W / L) (V V ) PMOS NMOS DD DD TH,PMOS k' CL VDD = (W / L) (V V ) TH,NMOS α α In W PMOS W NMOS Out C L Micro transductors 8, CMOS Basics 55

56 Logical Effort Source: Harris 5 Micro transductors 8, CMOS Basics 56

57 Logical Effort (LE) cont d gain= Cout * LE = f * LE C in C in,firstgate Cout LE of the whole circuit: fanout of the whole circuit: f sum = C out / C in,firstgate LE sum allgates = i LE i gain of the whole circuit: gain sum = LE sum * f sum Micro transductors 8, CMOS Basics 57

58 Logical Effort (LE) cont d gain sum = gain sum for every gate (starting at the last gate): C out, gate = gain gate LE C gate in, gate Micro transductors 8, CMOS Basics 58