Preliminary Outline of the IEEE P1500 Scaleable Architecture for Testing Embedded Cores

Transcription

1 Preliminary Outline of the Scaleable Architecture for Testing Embedded Cores Mike Ricchetti and Fidel Muradali VTS99 Dana Point, CA April 28, 1999 Architecture Task Force, 1999

2 Presentation Outline Introduction Active Task Force Members Task Force Mission, Scope and Current Status Overview of Proposed Architecture System Chip with Cores Core Test Requirements Architecture Components Core Test Components Protocol and Behavior Look at some examples Summary & Future Task Force Activities Architecture Task Force, 1999

3 Architecture Task Force Active Task Force Members Lee Whetsel (Task Force Chair) - Texas Instruments Debashis Bhattacharya - TI Dwayne Burek - LogicVision C.J. Clark - Intellitech Mike Collins - Cisco Systems Grady Giles - G 2 Startup.Com Sanjay Gupta - Nortel Alan Hales - Texas Instruments Mark Levitt - Sonics Erik Jan Marinissen - Philips Teresa McLaurin - Motorola Jim Monzel - IBM Fidel Muradali - Hewlett-Packard Janusz Rajski - Mentor Graphics Rochit Rajsuman - Advantest Mike Ricchetti - Synopsys David Stannard - Mentor Jon Udell - Palmchip Prab Varma - Veritable Alex Zamfirescu - ASC Yervant Zorian - LogicVision Architecture Task Force, 1999

4 Architecture Task Force Summary of Task Force Mission and Scope Goals of Standardize a Core Test Architecture which: 1. Defines a core test interface between an embedded core and the system chip. 2. Facilitate test reuse for embedded cores through core access and isolation mechanisms, and provide testability for system chip interconnect and logic. 3. Facilitates core test interoperability, with plug-and-play protocols, in order to improve the efficiency of test between core providers and core users. Scope of Standardize core test mechanisms, for core access and isolation, including protocols and test mode control. System Chip test access mechanism is defined by the system chip integrator. The core test method is defined by the core provider supports, and enables, various different methods (e.g., scan, BIST, I ddq, etc.). Architecture Task Force, 1999

5 Architecture Task Force Current Status of Task Force Activities Agreement on Mission, Scope, and Basic Principles General Agreement on Architecture System Chip view of Core test requirements Core Test Modes and Test Functions at core terminals Architectural view of a Core Key components of the architecture & possible configurations Reaching Behavioral Agreement on Architecture Behavior and protocols of the architectural components Agreements reached via review of proposals and example implementations presented by active task force members! More info at: Architecture Task Force, 1999

6 Overview of Architecture System Chip with Cores TAM-Source User Defined Test Access Mechanism TAM-Sink TAM-In Standard TAM-Out TAM-In Standard TAM-Out Chip Inputs Core 1... Chip Core N Outputs Core Test SO SI Core Test SI Control Standard Access SO System Chip TAM Source/Sink Architecture Task Force, 1999 From chip I/O and from test bus, test rail, BIST, etc. TAM In/Out 0 to n lines for parallel and/or serial test data, or test control Standard Access & Control From chip-level TAP controller, chip I/O, etc.

7 Core Test Requirements Proposed Core Test Modes Normal Allows core to function in its normal system operation Core-Internal Test Allows the internal core logic to be tested via the core test wrapper Core-External Test Allows testing of interconnect wiring and logic between cores via the core test wrapper Isolation Allows the core to be isolated, in a safe state, in order to facilitate testing of other cores and non-core chip logic Architecture Task Force, 1999

8 Core Test Requirements Test Functions at Core Terminals Input Test Functions Output Test Functions Input Observation: Allows logic values applied to core input terminals, from logic external to the core, to be observed. Input Control: Allows test data to be applied to core input terminals, such that it can be propagated into the core internal logic. Input Constraint: Forcing, or constraining, core input terminals to fixed logic values to prevent damage to the core, reducing power consumption, etc. Output Observation: Observation of logic values that have propagated to core outputs terminals from the core s internal logic. Output Control: Allows test data to be applied at core output terminals, such that it can be propagated to logic external to the core. Output Constraint: Constraining appropriate non-three-state core output terminals to fixed logic values to prevent damage to logic external to the core, etc. Output Disable: Allows forcing three-state core outputs to their inactive state to prevent damage to other three-state drivers on the same bus. Architecture Task Force, 1999

9 Architecture Components Cells TAM-In TAM-Out Instruction Register Core Bypass Register Input Control A wrapper contains the following: Output A Instruction Register for providing wrapper mode control Cells to provide test functions at the core terminals An optional Bypass register for a single bit scan bypass through the wrapper A serial interface for providing initialization and communication to the Instruction Register, Cells, and Bypass register Architecture Task Force, 1999

10 Instruction Register Proposed Required Instructions Normal cells allow normal core inputs/outputs to pass through the wrapper for normal system operation Core Test 1 N cells are configured to disable the core s normal mode & connected to TAM and/or wrapper serial input/output for core test Sources & sinks, 1-N, and core test methods are user defined External Test cells are configured to disable the core s normal mode, and are connected serially between the wrapper serial input/output Isolation cells are configured to disable the core s normal mode, and enable setting of appropriate core inputs or outputs to constrained and/or disabled values for core isolation Architecture Task Force, 1999

11 Registers Scan Protocol Behavior Input Capture Shift Selected Register Output Control Update Standard protocol for Registers will provide for: Parallel capture of input data into the selected register shift of the register from serial input to serial output Update scan-in data of register to a parallel update stage Required for Instruction Register and optional for others Architecture Task Force, 1999

12 Registers Standard Scan Path Configuration Cell Register Bypass mux DR Input WIR mux Output Control Control lines enable & perform scan, and select between: Instruction Register (WIR) Or other Data Registers (DRs), e.g. Cell Register, Bypass, etc. Updated WIR then selects between DRs Core Test 1-N instructions permit TAM connection & configuration of DRs, or internal core registers, to be used defined! Architecture Task Force, 1999

13 Connection with JTAG Cell Register Bypass mux Cell Register Bypass mux Input WIR DR mux WIR mux Output TAP Control Protocol Control Interface JTAG Protocol Control Interface is configured by system chip integrator & JTAG inter-operate at wrapper & serial data interfaces Architecture Task Force, 1999

14 Cell Example Dedicated Output Cell with Update Stage & TAM-Out SO TAM-Out Core Output Terminal Cell Input Output Cell Cell Output Output Terminal Instruction & Controls SI Cell behavior in response to Instructions Normal: Cell output connects to Cell input External Test: Cell output is sourced from cell s update stage Isolation: Cell output is appropriately disabled or constrained Core Test 1: TAM-Out is sink & provides output observation for core test Cell behavior for Scan Protocol Architecture Task Force, ) Captures data at cell input 2) Shifts data from scan input (SI) to scan output (SO) 3) Updates shift stage data to update stage

15 Cell Example Dedicated Input Cell with Update Stage & TAM-In TAM-In SO Input Terminal Cell Input Input Cell Cell Output Core Input Terminal Instruction & Controls SI Cell behavior in response to Instructions Normal: Cell output connects to Cell input External Test: Cell input is captured into cell s shift stage Isolation: Cell output is appropriately constrained Core Test 1: TAM-In is source & provides input control for core test Cell behavior for Scan Protocol Architecture Task Force, ) Captures data at cell input 2) Shifts data from scan input (SI) to scan output (SO) 3) Updates shift stage data to update stage

16 TAM Connection Example Core with Parallel Internal Scan Cells Core Logic TAM-In TAM-Out Input Control WIR Output Core internal scan paths & Cell Register are connected in parallel to TAM by a Core Test instruction Many other TAM connections and configurations are possible! Architecture Task Force, 1999

17 Architecture Task Force Summary and Future Activities provides a flexible Core Test Architecture Standardizes a core test interface between embedded cores and the system chip Facilitates core test interoperability & test reuse Also provide testability for system chip interconnect & UDL Improves efficiency of test between core providers & core users Near Term Activities on Task Force Roadmap Complete general Architecture discussions and reach behavioral agreement for Digital Cores Develop a Draft Standard and review with Working Group Finalize Architecture Draft for ballot May also include CTL as a single, merged, draft Architecture Task Force, 1999