VWorks Virtual Platforms for Renesas Processors

Transcription

1 VWorks Virtual Platforms for Renesas Processors Renesas Electronics America Inc.

2 Renesas Technology & Solution Portfolio 2

3 Agenda Overview of VLAB Virtual Platforms Why Use Virtual Platforms? Getting Started With VLAB Lab 1: VLAB Lab 2: FX4/V850E2 Simulation Lab 3: Debugging Lab 4: Working with Virtual Platform Netlists. Summary 3

4 Overview of VLAB Virtual Platforms For embedded software and system developers who use Renesas processors VLAB virtual prototyping solutions can accelerate development! Applications: Automotive Develop and debug software on the VWorks VLAB virtual platform for Renesas processors: Learn advanced techniques using software-based virtual platforms for hardware, embedded software and system simulation Build a simple virtual ECU, and experience the capability of virtual platform technology for development, test and debug with handson use of SystemC based, timed processor models Use VWorks virtual prototype models for Renesas Fx4/V850E2 Leverage capabilities and advanced techniques: Rapidly and interactively prototype different on- and off-chip architectures and system configurations Debug and analyze embedded software: deeply embedded software, driver software, base software and other ECU software Benefit from observability, controllability, repeatability, and programmability Mobile And more. 4

5 Why Use Virtual Platforms? 5

6 Before Hardware Availability Design capture, executable specification Architecture exploration, what if Performance analysis Early verification and validation, test creation Early start to software development Pre-Spec Spec RTL and Physical Design FPG A Si Samples Initial VP Developed VP updates to support Hw design and verification and Sw development 6

7 After Hardware Availability Instantaneous deployment and updates No hardware test-bench devices and real estate Easy to modify and re-configure 7

8 Killer Feature: System-Level Debug Non-intrusiveness Controllability Repeatability Visibility Programmability 8

9 What is VLAB? VLAB is an interactive and programmable environment for: Rich Electronic System Simulation applications Virtual Hardware Platforms 9

10 VLAB Simulation Applications Seamless integration of VLAB Simulation models and objects User scripts and customizations Test scenarios and test infrastructure Target software 10

11 Benefits for Virtual Platform Creators Ease of Adoption Native standard SystemC support No model code changes No vendor lock in Maximize Productivity No rebuilds Write less, do more Detailed instrumentation 11

12 VP as a Model of a Hardware Board Benefits of using a virtual platform May be available prior to hardware availability It is (usually) just software: easy to source and deploy in large numbers Better controllability, visibility, and instrumentation Easy to modify, reconfigure and experiment May offer faster than real-time performance: good for regressions May offer a lower cost solution However, a VP does not behave the same as hardware board Not all peripherals may be modeled Some aspects of hardware behavior may be simplified The timing behavior of a VP may be different 12

13 What can VLAB do? Import and integrate into a platform ASTC supplied, or your own, or 3rd party SystemC models Load a pre-assembled Virtual Platform, e.g. Fx4 Develop, assemble and configure your own new Virtual Platform Modify and re-configure at run time an existing Virtual Platform Create a new derivative SoC platform: extend an existing Virtual Platform Run (simulate) a Virtual Platform Debug and analyze target software running on a VP 13

14 Where is SystemC in VLAB SystemC is at the heart of VLAB VLAB runs native SystemC simulations, no proprietary API Any SystemC model can be used in VLAB with no modifications Any VLAB model can be built and used in another SystemC simulation e.g. OSCI VLAB provides Python scripting interfaces for ease of use and simplicity Complete SystemC API is accessible from Python Value-added features not present in other SystemC-based simulation tools 14

15 Do I need to know Python? VLAB embeds a complete Python interpreter and runtime All VLAB commands are in Python Most of VLAB is implemented in Python Does this mean you have to know Python? You do not have to know Python: all VLAB features are designed to require only basic Python You can choose to implement simulator features in C++ just as you would in the OSCI environment Would I benefit by learning a bit more about Python? Why would I make that investment? Yes, you can benefit this will unlock many possibilities and flexibilities in the tool Python is known to be about 3x more expressive than C++ Python is widely recognized as being very easy to learn 15

16 Software and Hardware Requirements VLAB runs on the following host Operating Systems Microsoft Windows XP SP3, Windows 7 (32-bit) RedHat Enterprise Linux 4.x, 5.x (32-bit, x86 architecture) Ubuntu 8.x, 9.x, (32-bit, x86 architecture) Models have to be built using the following toolchains Microsoft Visual Studio C SP1 or 2010 on Windows GCC 3.4.x on RHEL4 GCC 4.1.x on RHEL5 and Ubuntu Hardware requirements Intel Pentium-M compatible processor (Core 2 Duo recommended) Minimum of 2GB of RAM (4GB recommended) 1 GB of free disk space for VLAB and toolbox installation At least 5GB of free disk space for advanced instrumentation log files 16

17 Documentation VLAB user documentation is available in $VLAB_HOME/doc: VLAB User Manual (PDF) OCE User Manual (PDF) On Windows, the above is accessible via Start->Programs->VWorks->VLAB->doc Documentation for ASTC provided content toolboxes (e.g. Fx4) is also available in $VLAB_HOME/toolbox/<toolboxname>/doc On Windows, one can use Start->Programs->VWorks->Fx4 Toolbox->doc In the rest of this material, all references to the VLAB User Manual refer to version 1.7.5, and may change with future VLAB versions. 17

18 Notation Throughout this training and exercises, the following terminology has been adopted: Anything following VLAB> is a command to be typed into VLAB and will appear in the following font. Note: VLAB> should be omitted. VLAB> In exercises, text preceded by a # is a comment. Text preceded by a > should be typed on the Windows command prompt. Note: > should be omitted 18

19 Getting Started with VLAB 19

20 Starting VLAB Two ways to run VLAB Text Mode > %VLAB_HOME%\vlab VLAB> exit() Graphical Mode > %VLAB_HOME%\vlab --gui VLAB commands are functions thus always end in () and may also take arguments (same as a standard Python interpreter) 20

21 Starting VLAB Text Mode Graphical Mode 21

22 Loading a Simulator Let s load the VLAB Fx4 Toolbox and poke around a bit From the command prompt (in an example test directory) vlab fx4.sim From within VLAB VLAB> load_sim("fx4.sim") Check which VLAB version is running VLAB> version() Show all instances in the simulator VLAB> show_instances() Show all signal ports in the simulator VLAB> show_ports() Show all bus ports (TLM sockets) in the simulator VLAB> show_ports(kind= bus ) 22

23 Running a Simulator Let s see what registers exist in FX4.FCNA0" VLAB> show_registers("fx4.fcna0") We can now run the simulator for a short while (10 ns) VLAB> run(10) We can query the simulation time to check the progress of the simulation VLAB> simulation_time() Pause the simulation VLAB> pause() Add a hardware, software or time even breakpoint VLAB> add_break( ) Log simulation data in either Text, ODA, or VCD formats VLAB> add_trace("fx4 ) 23

24 The VLAB GUI Window 24

25 Graphical Mode in VLAB The VLAB "graphical mode" (GUI) is designed to complement the VLAB command interface All actions available via the GUI have their command counterparts It is possible to automate the manual steps performed via the GUI by using scripts (sequences of commands) The GUI is the preferred mode of learning VLAB Presents information in a logical manner Familiarize yourself with the available menus, panes, and toolbars Discover new functionality Learn new commands by merely interacting with the GUI 25

26 VLAB Sessions VLAB s graphical mode supports multiple simulation sessions Sessions can be started using the Session Toolbar or the File- >New Session menu item New sessions can be started in parallel with an existing session to execute concurrent simulations An existing session can be reloaded using the initial session launch parameters 26

27 The Dashboard: Workspace Pane The workspace pane presents itself upon VLAB GUI startup, and offers quick convenient access to items, including: Favorite scripts, trace files, and VLAB commands Pre-installed toolboxes with related documentation and scripts File system access to VLAB_PATH and local directories 27

28 The Dashboard: System Pane System Pane presents a tree view of the simulated hardware structure to Explore the simulation object hierarchy View and select display format of ports, attributes, and register values Change values of ports and registers Navigate port connectivity Access to advanced feature via context sensitive menus available via a right-click 28

29 The Dashboard: Breakpoints Pane Breakpoints Pane displays the state of the hardware breakpoints in the current session Context menu accessible via right-click Breakpoints can be enabled, disabled, or removed More details on use of breakpoint will be provided later in the training 29

30 The Dashboard: History Pane History pane contains previously executed commands Separate entry for each session Can select one or many commands Commands can be executed through the console, making repetitive tasks easier to manage 30

31 Console and Output Panes Output pane reflect all user interactions, including commands and simulator output Supports text select and copy Unlimited buffer Very fast scrolling Console pane is located directly under the output pane Supports syntax highlighting Grows as needed (e.g. multiline input) Command help and autocompletion 31

32 Working with Port and Register Values Once SystemC elaboration is complete, VLAB provides a mechanism to query the values of ports and registers Ports VLAB> read_port( example.core0.int ) Registers VLAB> read_register( example.sage0.config ) Registers can also be modified VLAB> write_register( example.sage0.config,4) All of the above can be done via the GUI as well 32

33 Accessing Simulation Objects So far, we have always provided hierarchical object names to identify which simulation objects we want to operate on It is often convenient to use scripting variables as references to objects Access a single instance (sc_module object) VLAB> inst1 = get_instance( example.core0 ) Access a group of instances VLAB> insts1 = get_instances( example,recurse=true) Access a single port by name VLAB> port1 = get_port( example.core0.int ) Access a group of ports, as a list VLAB> ports1 = get_ports( example.core0 ) 33

34 Tracing port or instance connectivity It is often required to review/verify the connections of a port or instance in the simulation This feature is available via the System Pane, via right-click > Destinations This is also available via the get_connections command inst = get_instance( example.core0 ) conn = get_connections(inst) We can examine the names of the connections for c in conn: print c However, there is a more direct and user friendly way to inspect connections on the console: show_connections(inst) 34

35 Lab 1: VLAB Quick Overview 35

36 ASTC Virtual Platform Technology and Solutions: Fx4 Toolbox - Introduction 36

37 Fx4 Toolbox - Introductions The Fx4 Toolbox is a content toolbox for VLAB that provides components for simulation of Renesas Fx4 family microcontrollers. The components include peripheral models, cores, memories, buses. Load software images onto core for execution. Hardware analysis and debugging with VLAB tools. Software debugging with Green Hills Multi IDE Supports attachment of external connections via testbenches for: Connection of loopbacks between pins Connection of external stimulus Connection of routers, can buses etc. Configuration of model attributes Setting up tracing and other simulation options 37

38 Hardware Architecture Fx4 Toolbox includes the following components: V850E2R/M Core Interrupt Controller Memories Buses DMA Real Time Clock CSIG & CSIH IO Ports Key Return UARTE Timer A & J Watchdog Timer ADC TAOPA Analog Comparator Random Number Generator Data CRC Clock Monitor PRCCM (Reset/LVI/Clock Module) OS Timer ERAY (FlexRay) Encoder Multi-LIN afcan Digital Filters I2C Ethernet 38

39 Toolbox Architecture 39

40 Modes of Operation SCHEAP Mode (default) Uses cycle accurate CPU sub system (ISS, memories, buses) High accuracy timing simulation Most complete CPU model (protection units etc.) Slower execution speed (~0.17 MIPS), but good for low-level analysis. FastISS Mode (--fastiss) High performance ISS model Functional model with most necessary components Simplified memory and bus models Execution speed (400+ MIPS), for fast loading of complex applications. In both modes, peripheral models (e.g. CAN, timers) have the same accuracy. 40

41 What can you do with the VP? Almost everything you can do with a HW board: Load compiled software Execute applications Connect a software debugger Analyze and inspect software behavior, use SW breakpoints etc. A lot that that you can t do with a HW board: Inspect internal state of the simulation: ports, registers, buses Pause and manipulate time Use hardware breakpoints (ports, buses, register, state changes) Trace detailed logs of execution behavior Inject faults and errors Get warnings on incorrect module usage and info about internal state + much more. 41

42 Lab 2: FX4/V850E2 Simulation 42

43 Exploring connections Run the timera_timerj test with testbench 43

44 Setting HW Breakpoints Right click TAUATINT0" Add a breakpoint: Look at "Breakpoints" 44

45 Testbench Configuration Connecting Port Loopback connect(("fx4","port_p1_0"), ("FX4","Port_P0_12")) Setting Attributes set_attribute("fx4.etha0","input_pcap_filename", "ethernet_input.pcap ) Connection communication lines a loop # Connect CSIG0 to CSIG1 for i in range (0, 32): #CONTROL connect(("fx4","csig0_control%i"%i), ("FX4","CSIG1_CONTROL%i"%i)) #DATA connect(("fx4","csig0_sdo%i"%i),("fx4","csig1_sdi%i"%i)) connect(("fx4","csig1_sdo%i"%i),("fx4","csig0_sdi%i"%i)) 45

46 Testbench Configuration AFCAN Example # Instantiate the CAN bit bus router can_bus_component = component(name="can_bit_bus_router_logic", library="pf3utils") CAN_BUS = instantiate(can_bus_component, "CAN_BUS") # Connect CAN bus to CAN instances 0~4 through GPIOs #RX FCNA0-4 connect(("fx4","port_p0_4"), ("CAN_BUS","RX",0)) connect(("fx4","port_p0_7"), ("CAN_BUS","RX",1)) connect(("fx4","port_p0_9"), ("CAN_BUS","RX",2)) connect(("fx4","port_p0_11"), ("CAN_BUS","RX",3)) connect(("fx4","port_p2_2"), ("CAN_BUS","RX",4)) #TX FCNA0-4 connect(("can_bus","tx"), [("FX4","Port_P0_5"), ("FX4","Port_P0_6"), ("FX4","Port_P0_8"), ("FX4","Port_P0_10"),("FX4","Port_P2_0")]) 46

47 Command Line Parameters Options: --version show program s version number and exit -h, --help show this help message and exit -c FILE, --heap-config=file The filename of the heap configuration file to use. -n cycles, --num-cycles=cycles The number of cycles to execute for. If not supplied, use run() at the vlab prompt. (Do not use -n with the gui) -t FILE, --testbench=file Specifies the testbench file to use. -v, --vcd-trace Turns on vcd tracing of all model ports. -m ELFFILE, --multi=elffile Launches the ghs multi debugger with the specified elf file. Requires the MULTI_ROOT environment variable to be set. --DX4 Initializes the platform in DX4 mode (default is FX4) --DX4H Initializes the platform in DX4H mode (default is FX4) --SX4 Initializes the platform in SX4 mode (default is FX4) --fastiss Use the FastISS core and simplified bus & timing model. -q nanoseconds, --quantum-period=nanoseconds Sets the quantum period in ns to use when in fastiss mode. Default is 1000ns 47

48 Software Debugging Software debugging is supported with Green Hills Multi IDE Compile an elf file (not srecord/hex). In the example this is *.out Set env variable MULTI_ROOT=<path to multi install> Requires a license for the rteserv2 component on Multi Execute with m option show in previous slide. SCHEAP Mode Debugging VLAB has limited updates and accessibility during debugging. FastISS mode debugging Hardware breakpoints will trigger software breaks in Multi Software breakpoints will update VLAB state Hardware breakpoints and pauses/stop will occur at end of qunatum 48

49 Lab 3: Debugging 49

50 Tracing HW State "ODA": OSCAR Data Analyzer Right-click TAUA0 to trace all TimerA trace points: 50

51 Tracing HW State... Use a command to add more trace points: VLAB> add_trace( FX4.TAUA0", sink=trace.sink.oda) Run the simulation: VLAB> run() Use view->trace to show ODA: Events Register Values 51

52 Tracing HW State with VCD Use the System View to VCD trace the TAUA0: Run the simulation: VLAB> run() Wait for the example to complete, then exit and view VCD VLAB> exit() gtkwave fx4sim.vcd 52

53 Lab 4: Working with Virtual Platform Netlists 53

54 Some Terminology A VLAB virtual platform description is the equivalent of an IC integration topsheet It specifies what is in the platform, and how it is connected It also specifies what is the external interface of the VP It may provide mechanisms for configuring the platform in different ways A virtual platform is composed of a hierarchy of component instances. A component may be a composite component (a subsystem) or a leaf component (an individual model). The Python language is used to assemble and configure a virtual platform. The following slide shows an example virtual platform. 54

55 Example Virtual Platform 55

56 Elements of a VP Description A component may be a composite or leaf component. Composite Component is formed by the composition of leaf or other composite components. is composed of instances, connections, exports and assignments. Leaf Component are components that do not contains any sub-components. may be SystemC modules. 56

57 Elements of a VP Description (cont.) Instance An instance of a simulation component, created using vlab.instantiate(). An instance contains simulation state, and may be connected to other instances to create a full simulation. Connections A communicative link between endpoints. In hardware terms, a connection is a signal, wire or net. A connection may be one-toone, one-to-many, many-to-one or many-to-many. A connection is created using vlab.connect(). component() Library instantiate() connect() 57

58 Elements of a VP Description (cont.) Assignments Set a value to some entity within an instance. A common example is the assignment of a value to an instance attribute. Exports An entity from an instance that has been exposed so that it may be accessed from a higher level of the system hierarchy. Examples of entities that may exported from an instance include: ports, bus interfaces and attributes. component() export() Library instantiate() connect() 58

59 Assembling a Virtual Platform The following slides show example VLAB Assembly API code 59

60 Simple SoC Example Description Example SoC The Python module shown here is the description of a fictitious component called SimpleSOC, which is composed of an ARMCore, BusRouter and timer subcomponents. SimpleSOC extbus reset CORE ROUTER TIMER rev:1c 60

61 VLAB "Example Toolbox" Description VLAB Example Toolbox The Python module shown here is the description of the VLAB Example Toolbox. 61

62 Summary: VLAB Virtual Platforms For embedded software and system developers who use Renesas processors VLAB virtual prototyping solutions can accelerate development! Applications: Automotive Develop and debug software on the VWorks VLAB virtual platform for Renesas processors: Learn advanced techniques using software-based virtual platforms for hardware, embedded software and system simulation Build a simple virtual ECU, and experience the capability of virtual platform technology for development, test and debug with handson use of SystemC based, timed processor models Use VWorks virtual prototype models for Renesas Fx4/V850E2 Leverage capabilities and advanced techniques: Rapidly and interactively prototype different on- and off-chip architectures and system configurations Debug and analyze embedded software: deeply embedded software, driver software, base software and other ECU software Benefit from observability, controllability, repeatability, and programmability Mobile And more. 62

63 Questions? 63

64 Renesas Electronics America Inc.