How does the CPU execute programs? Nils Jansen December 5, 2017 (Based on slides by Jeroen Keiren and Niek Janssen)

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1 How does the CPU execute programs? Nils Jansen December 5, 2017 (Based on slides by Jeroen Keiren and Niek Janssen)

2 Overview 2

3 Overview So far Circuits Memory ALU 2

4 Overview So far Circuits Memory ALU Today How are instructions executed? Fetch-decode-execute cycle Data Path RUN1718 CPU - your own processor in the practicum 2

5 Recall: A Six-level Computer 3

6 Recall: A Six-level Computer recall the levels and their meaning 3

7 Recall: A Six-level Computer recall the levels and their meaning humanunderstandable machine language controls data path between ALU and registers ALU (Arithmetic Logic Unit), registers gates get signals 0 or 1, compute output functions (AND, OR), may form memory or even computing engine 3

8 Von Neumann -architecture 4

9 Von Neumann -architecture recall the structure 4

11 Von Neumann -architecture recall the structure How to execute programs? Program Screen Keyboard Memory Tanenbaum, Structured Computer Organization, Fifth Edition, 2006 Pearson Education, Inc. All rights reserved

12 Program Inside the Memory Details next week! Consists of machine code RUN1718 CPU: Each machine code instruction consists of 32 bits Other processors: bits 5

13 Microarchitecture Program Execution Cycle 1.Read instruction (PC) (Fetch) 2.Increase PC 3.Decode instruction (Decode) 4.Execute instruction (Execute) 6

14 Microarchitecture Program Execution Cycle 1.Read instruction (PC) (Fetch) 2.Increase PC 3.Decode instruction (Decode) 4.Execute instruction (Execute) Fetch Decode, Execute 6

15 Microarchitecture Program Execution Cycle 1.Read instruction (PC) (Fetch) 2.Increase PC 3.Decode instruction (Decode) 4.Execute instruction (Execute) Fetch Decode, Execute 6

21 Decode-phase what is done in the decode phase? Instruction Program Memory Screen Keyboard Tanenbaum, Structured Computer Organization, Fifth Edition, 2006 Pearson Education, Inc. All rights reserved

22 Decode-phase what is done in the decode phase? Next week: READ: WRITE: Instruction Program Memory Screen Keyboard Tanenbaum, Structured Computer Organization, Fifth Edition, 2006 Pearson Education, Inc. All rights reserved

24 Execute-phase: Computation what is done during a computation? Program Memory Screen Keyboard Tanenbaum, Structured Computer Organization, Fifth Edition, 2006 Pearson Education, Inc. All rights reserved

25 Execute-phase: Computation what is done during a computation? operands Program Memory Screen Keyboard Tanenbaum, Structured Computer Organization, Fifth Edition, 2006 Pearson Education, Inc. All rights reserved

26 Execute-phase: Computation what is done during a computation? flags operands result Program Memory Screen Keyboard Tanenbaum, Structured Computer Organization, Fifth Edition, 2006 Pearson Education, Inc. All rights reserved

29 Execute-phase: Write what is done during writing? WRITE Program Memory Screen Keyboard WRITE Tanenbaum, Structured Computer Organization, Fifth Edition, 2006 Pearson Education, Inc. All rights reserved

30 Data Path (MIPS processor) Read address Instruction Instruction Register Readreg. 1 Read data1 Readreg. 2 Writereg. Write data Read data2 Registers Address Read data Write data Data Memory 12

31 Data Path (MIPS processor) Read address Instruction Instruction Register Readreg. 1 Read data1 Readreg. 2 Writereg. Write data Read data2 Registers Address Read data Write data Data Memory ADD R1, R2, R2 (R2 := R1 + R2) 12

32 Data Path (MIPS processor): Fetch Read address Instruction Instruction Register Readreg. 1 Read data1 Readreg. 2 Writereg. Write data Read data2 Registers Address Read data Write data Data Memory ADD R1, R2, R2 (R2 := R1 + R2) 13

33 Data Path (MIPS processor): Decode Read address Instruction Instruction Register Readreg. 1 Read data1 Readreg. 2 Writereg. Write data Read data2 Registers Address Read data Write data Data Memory ADD R1, R2, R2 (R2 := R1 + R2) 14

34 Data Path (MIPS processor): Execute Read address Instruction Instruction Register Readreg. 1 Read data1 Readreg. 2 Writereg. Write data Read data2 Registers Address Read data Write data Data Memory ADD R1, R2, R2 (R2 := R1 + R2) 15

35 Data Path (MIPS processor): Execute Read address Instruction Instruction Register Readreg. 1 Read data1 Readreg. 2 Writereg. Write data Read data2 Registers Address Read data Write data Data Memory ADD R1, R2, R2 (R2 := R1 + R2) 15

36 The Practicum: RUN1718 CPU Nils Jansen December 5, 2017 (Based on slides by Jeroen Keiren)

37 Finite automaton Fetch-D+Execute Cycle Fetch Decode+ Execute 17

38 Finite automaton Fetch-D+Execute Cycle What is a finite automaton? Fetch Decode+ Execute 17

39 How to construct the RUN1718 CPU 3 phases: 18

40 How to construct the RUN1718 CPU 3 phases: 1. Fetch read instructions 18

41 How to construct the RUN1718 CPU 3 phases: 1. Fetch read instructions 2. Test preconditions satisfied? 18

42 How to construct the RUN1718 CPU 3 phases: 1. Fetch read instructions 2. Test preconditions satisfied? 3. D(ecode) + Execute decoding only combinatorial 18

43 Finite automaton for RUN1718 CPU Fetch CLK CLK Test Pause CLK [TEST_SUCCEEDS=1] Decode+ Execute CLK 19

44 Finite automaton for RUN1718 CPU Fetch CLK CLK Test CLK [TEST_SUCCEEDS=0] Pause CLK [TEST_SUCCEEDS=1] Decode+ Execute CLK 19

45 Run of the finite automaton clock pulse 20

46 Run of the finite automaton clock pulse 20

47 Run of the finite automaton clock pulse Fetch 20

48 Run of the finite automaton clock pulse Test Fetch 20

49 Run of the finite automaton clock pulse Test Fetch Decode+ Execute 20

50 Run of the finite automaton clock pulse Test Pause Fetch Decode+ Execute 20

51 Run of the finite automaton clock pulse Test Pause Fetch Decode+ Execute Fetch 20

52 Run of the finite automaton clock pulse Test Pause Test Fetch Decode+ Execute Fetch 20

53 Run of the finite automaton clock pulse Test Pause Test Fetch Decode+ Execute Fetch Fetch 20

54 Run of the finite automaton clock pulse Test Pause Test Test Fetch Decode+ Execute Fetch Fetch 20

55 Finite automaton for RUN1718 CPU Reset Test Fetch Decode+ Execute Pause Halted 21

56 Finite automaton for RUN1718 CPU Reset Test Fetch Decode+ Execute Pause Halted 21

57 Finite automaton for RUN1718 CPU Reset Test Fetch Decode+ Execute Pause Halted 21

58 Structure of the RUN1718 CPU 22

59 Structure of the RUN1718 CPU ALU 22

60 Structure of the RUN1718 CPU ALU registerbank 22

61 Structure of the RUN1718 CPU ALU registerbank control unit flag register bank tester timer instruction decoder with instruction register 22

62 Structure of the RUN1718 CPU (Overview) 23

63 Structure of the RUN1718 CPU (Overview) 23

64 How do I start? 24

65 How do I start? 1. Data Path: How do the components interact? 24

66 How do I start? 1. Data Path: How do the components interact? during the fetch phase? 24

67 How do I start? 1. Data Path: How do the components interact? during the fetch phase? during the test phase? 24

68 How do I start? 1. Data Path: How do the components interact? during the fetch phase? during the test phase? during the execution phase? 24

69 How do I start? 1. Data Path: How do the components interact? during the fetch phase? during the test phase? during the execution phase? 2. Interfaces for each component 24

70 How do I start? 1. Data Path: How do the components interact? during the fetch phase? during the test phase? during the execution phase? 2. Interfaces for each component based on given information 24

71 How do I start? 1. Data Path: How do the components interact? during the fetch phase? during the test phase? during the execution phase? 2. Interfaces for each component based on given information 3. Combined data path 24

72 How do I start? 1. Data Path: How do the components interact? during the fetch phase? during the test phase? during the execution phase? 2. Interfaces for each component based on given information 3. Combined data path necessary connections (and multiplexers) 24

73 How do I start? 1. Data Path: How do the components interact? during the fetch phase? during the test phase? during the execution phase? 2. Interfaces for each component based on given information 3. Combined data path necessary connections (and multiplexers) 24

74 How do I start? 1. Data Path: How do the components interact? during the fetch phase? during the test phase? during the execution phase? 2. Interfaces for each component based on given information 3. Combined data path necessary connections (and multiplexers) Afterwards: design your own parts. 24

75 How do I start? 1. Data Path: How do the components interact? during the fetch phase? during the test phase? during the execution phase? 2. Interfaces for each component based on given information 3. Combined data path necessary connections (and multiplexers) Afterwards: design your own parts. (HADES is no design tool) 24

76 Summary Finite automaton Reset Fetch Test (Decode+Execute) Pause Halted Data path: which data is required when for execution of instruction? Start working on the processor, plan carefully! 25

Processors. Nils Jansen and Kasper Brink. (based on slides from Jeroen Keiren, Marc Seutter and David N. Jansen)

Processors. Nils Jansen and Kasper Brink. (based on slides from Jeroen Keiren, Marc Seutter and David N. Jansen) Processors Nils Jansen and Kasper Brink (based on slides from Jeroen Keiren, Marc Seutter and David N. Jansen) https://ocw.cs.ru.nl/nwi-ipc006 Student Assistants Jordi Riemens Jasper Haasdijk Niek Janssen