! Design Methodologies. " Hierarchy, Modularity, Regularity, Locality. ! Implementation Methodologies. " Custom, Semi-Custom (cell-based, array-based)

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1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 23: April 12, 2016 VLSI Design and Variation Lecture Outline Design Methodologies Hierarchy, Modularity, Regularity, Locality Implementation Methodologies Custom, Semi-Custom (cell-based, array-based) Design Quality Variation Packaging 2 Three Domain View of VLSI Design Flow at One Level Y-Chart FUNCTIONAL DESIGN Verilog/Spectre Verilog/Cadence Verilog/Spectre Extract Parasitic Elements SPICE Spectre (Spectre) LAYOUT VERIFICATION 1. Design Rule Check (DRC) 2. Layout Versus Schematic (LVS) Check 3. Post layout simulation (PLS) Cadence (Virtuoso) PLS 3 4 Design Strategies Structured Design Strategies Metrics for Design Success: Performance Specs logical function, speed, power, area Time to Design engineering cost and schedule Ease of Test Generation and Testability engineering cost, manufacturing cost, schedule Design is a continuous tradeoff to achieve performance specs with adequate results in the other metrics Strategies common for complex hardware and software projects Hierarchy: Subdivide the design in several levels of submodules Modularity: Define sub-modules unambiguously and well defined interfaces Regularity: Subdivide to max number of similar submodules at each level Locality: Max local connections, keeping critical paths within module boundaries 5 6 1

2 Modularity Hierarchical & Modular 4-bit Adder Adds to the hierarchy and regularity Unambiguous functions Well defined beahvioural, structural, and physical interfaces Enables modules to be individually designed and evaluated Eg. 4b Adder add add4 add add add b a c a b c b a c + co s s co 7 nand nor nand nor nand nor nand inor n v 8 Hierarchical & Modular Layout Floorplanning: Map Structural into Physical b[3:0] a[3:0] c0 + add co3 s[3:0] b[3] a[3] b[2] a[2] b[1] a[1] b[0] a[0] (0,0) c0 add[3] add[2] add[1] add[0] co3 (100,400) s[3] (100,300) s[2] (100,200) s[1] (100,100) s[1] (0,100) (0,75) (0,25) (0,0) add1 Cell (50,100) b[i] c[i] add[i] s[i] a[i] co[i] (50,0) (100,100) (100,50) (100,0) Unused die area -> inefficient layout Structural Hierarchy 1 mapped poorly into Physical Hierarchy. Better mapping add4 Module Miss-mappings between Structural and Physical Hierarchies usually avoided by using automatic layout system Regularity Locality (Physical) Design the chip reusing identical modules, circuits, devices. Regularity can exist at all levels of the design hierarchy Circuit Level: Uniform transistor sizes rather than manually optimizing each device Logic Level: Identical gate structures rather than customize every gate Architecture Level: construct architectures that use a number of identical sub-structures TIME LOCALITY: modules are synchronized by common clock. Critical timing paths are kept within module boundaries Place modules to minimize large or global inter-module signal routes Take care to realize robust clock generation and distribution Signal routes between modules with large physical separation need sufficient time to traverse route Replicate modules, if necessary, to alleviate delay issues caused by long intermodule signal routes

3 Implementation Methodologies CMOS Chip Design Options Digital Circuit Implementation Approaches Custom Semicustom Design Time and Cost Decreasing (for a given application) Cell-based Array-based Standard Cells Compiled Cells Ma cro Cells Pre-diffused (Gate Arrays) Pre-wired (FPGA's) Performance Increasing, Die Area Decreasing, Power Dissipation Increasing (for a given application) 14 Prewired Arrays Array-Based Programmable Logic I 5 I 4 I 3 I 2 I 1 I 0 Programmable OR array I 3 I 2 I 1 I 0 Programmable OR array I 5 I 4 I 3 I 2 I 1 I 0 Fixed OR array Categories of prewired arrays (or field-programmable devices): Fuse-based (program-once) Non-volatile EPROM based RAM based Programmable AND array Fixed AND array Programmable AND array O 3 O 2 O 1 O 0 O 3 O 2 O 1 O 0 O 3 O 2 O 1 O 0 PLA PROM PAL Indicates programmable connection Indicates fixed connection Programming a PROM Field-Programmable Gate Arrays Fuse-based 1 X 2 X 1 X 0 FPGA Features Configurable I/O Configurable Logic Programmable Interconnect/routing I/O Buffers Program/Test/Diagnostics Vertical routes I/O Buffers I/O Buffers Rows of logic modules Routing channels : programmed node NA NA f 1 f 0 I/O Buffers 3

4 Field-Programmable Gate Arrays RAM-based Standard-Cells Based Design Horizontal routing channel CLB CLB switching matrix Interconnect point Predominant custom design style Standardization is achieved at the logic or function level Specific designs for each gate are developed and stored in a software database of cell library Bahavioural, structural, and physical domain descriptions per cell CLB Vertical routing channel CLB Layout is usually automatically placed and routed using CAD software 20 Standard Cell Library Contents Cell-based Design (or standard cells) SSI logic nand, nor, xor, inv, buffers, latches, registers each gate can have multiple implementations to provide proper drive for different fan-outs, eg. standard size, 2x, 4x MSI logic decoders, encoders, adders, comparators Datapath ALUs, register files, shifters Memories RAM, ROM System level multipliers, microcontrollers Rows of Cells Feedthrough Cell Logic Cell Functional Module (RAM, multiplier, ) Routing Channel Routing channel requirements are reduced by presence of more interconnect layers 21 Standard Cell - Example Automatic Cell Generation 3-input NAND cell (from Mississippi State Library) characterized for fanout of 4 and for three different technologies Random-logic layout generated by CLEO cell compiler (Digital) 4

5 Design Quality Variation Types Achieve specifications (static and dynamic) Die Size Power dissipation Many reasons why variation occurs and shows up in different ways Scales of variation Testability Yield and Manufacturability Reliability Kenneth R. Laker, University of Pennsylvania, updated 6Apr15 Random dopant fluctuation Local oxide variation Line edge roughness Etch and growth rates Transistors differ from each other in random ways 27 Impact Changes parameters Change transistor behavior 26 Random Transistor-to-Transistor Source: Noel Menezes, Intel ISPD2007 Systematic, spatial, random (uncorrelated) Correlations of variation 25 Wafer-to-wafer, die-to-die, transistor-to-transistor 28 Vth 65nm W, L, tox, Vth W? L? tox? W %) V2, IDS = µn COX $ '+(VGS VT )VDS DS. # L &* 2 29 [Bernstein et al, IBM JRD 2006] 30 5

6 Impact of V th Variation? Higher V th? Not drive as strongly I d,vsat (V gs -V th ) Performance? Impact Performance V th # I ds # Delay (R on * C load ) Impact of V th Variation? Lower V th? Not turn off as well # leaks more Variation See a range of parameters L: L min L max V th : V th,min V th,max # I DS = I S W & % ( e $ L ' # V GS V T & % $ nkt / q ' (# 1 e % $ # V DS & % ( $ kt / q ' & ( 1+ λv DS ' ( ) Variation Margin for expected variation Must ase V th can be any value in range Speed # ase V th slowest value Variation See a range of parameters L: L min L max V th : V th,min V th,max Probability Distribution I on,min =I on (V th,max ) I d,vsat (V gs -V th ) Validate design at extremes Work for both V th,min and V th,max? Design for worst-case scenario V TH

7 Margining Also margin for Temperature Voltage supply Aging: end-of-life Process Corners Many effects independent Many parameters With N parameters, Look only at extreme ends (low, high) How many cases? Try to identify the {worst,best} set of parameters Slow corner of design space, fast corner Use corners to bracket behavior Simple Corner Example Process Corners 350mV What happens at various corners? Many effects independent Many parameters Try to identify the {worst,best} set of parameters E.g. Lump together things that make slow Vthp Vthn, Vthp, temperature, Voltage Try to reduce number of unique corners Slow corner of design space 150mV Use corners to bracket behavior 150mV Vthn 350mV Range of Behavior Speed Binning Still get range of performances Any way to exploit the fact some are faster? Probability Distribution Delay Probability Distribution Sell Premium Delay Sell nominal Sell cheap Discard

8 Design Quality Packaging Technology Testability generation of good test vectors design of testable chip Yield and Manufacturability functional yield parametric yield Reliability threshold variation premature aging power and ground bouncing ESD/EOS -> can compensate in padframe noise and crosstalk Package Bonding Techniques Parasitics in an Electronic Package PCB Transmission Line Wire Bond Package Body Die Paddle PCB Ground Plane PCB Vias Summary of Package Types Admin HW 7 and 8 graded by Friday EC graded by Monday Final Project Design memory (SRAM) EC for best figure of merits (FOM = Area*Power*Delay 2 ) # of points depends on teams reported Can propose extra work for extra credit Due 4/26 (last day of class) Everyone gets an extension until 5/6 (day of final exam) Keep an eye on Piazza for useful information and updates on project handout for clarity

9 Final Project Schedule Posted now April 11 th report teams to instructor April 14 th extra credit proposals due to instructor April 26 th final report due Must be submitted via Canvas May 6 th extension for reports (also day of final) All deadline times are midnight that day 49 9