Directed Self-Assembly for the Semiconductor Industry

Transcription

1 Directed Self-Assembly for the Semiconductor Industry H.-S. Philip Wong, Chris Bencher # Linda He Yi, Xin-Yu Bao, Li-Wen Chang Stanford University, # Applied Materials

2 Stanford University J.W. Jeong...C.A. Ross., Nano Lett. 2011, 11, [MIT] J. Y. Cheng et al., Adv. Mater. 2008, 20, [IBM] 2 C. Tang C. Hawker, Science, p. 429 (2008). [UCSB] R. Ruiz P. Nealey, Science 321, 936 (2008) [Hitachi, Wisconsin] July 9, 2012

3 Nangate cell library: Device Fabrication Does not require long range order J. Stork, TI (2007), Stanford seminar 3 H.-S. Philip Wong Department of Electrical Engineering

4 Device Fabrication Requires Multiple-pitch Nangate cell library: Multiple-ordering Multiple-size One layer process Single material system Industrial compatible process Transparent to circuit designers J. Stork, TI (2007), Stanford seminar Technical requirement Practicality (i.e. cost) 4 H.-S. Philip Wong Department of Electrical Engineering

5 Why don t we place the shapes where we want them to be? Adapted from: ucsusa.org 5

6 Directed Self-Assembly by Physical Confinement Guiding Template: Physical Confinement PS-b-PMMA PMMA PS 120 nm 230 nm 2 rows of holes 200nm L.-W. Chang H.-S. P. Wong, IEDM, p. 879, July 9, 2012

7 Control of DSA with Small Guiding Templates Size Comparable to self-assembly dimensions 200nm Flexible and precise control knobs: Thickness, size, density A B A B C 75nm 60x110nm 70x145nm 200nm 92nm 104 nm 108 nm 126 nm 136 nm 200nm scale bar Square lattice 7 July 9, 2012 Rhombic lattice

8 Small Templates hole patterns Canonical templates Contact hole layout Design A Design B Canonical templates: Simplest template set to form desired patterns Manufacturable with current litho tech. Design Rules: The standards to disassemble a layout to canonical templates and reassemble canonical templates to pattern devices Alphabet table 8 July 9, 2012

9 Square Template DSA Pattern Size Analysis Mean: 15.2 nm 4 75 nm SD: 2.3 nm ±2.3nm 3 1 Mean = 28.6 nm SD = 5.2 nm 92 nm 28.6±5.2nm Hole Size (nm) Hole Size (nm) Mean: 30.3 nm SD: 2.1 nm 126 nm ±2.1nm 1 Mean: 31.7 nm SD: 9.0 nm 136 nm 31.7±9nm Hole Size (nm) Hole Size (nm) H. Yi H.-S. P. Wong, Adv. Mater., 2012 July 9, 2012

10 2-Hole Pattern Analysis A B 5 Mean: 15.0 nm 4 SD: 1.8 nm 3 60nmx110 nm 4 3 Mean: 39.7nm Std: 1.9nm 2-hole pattern 15±1.8 nm 40±2nm 4 3 Mean: 37.7nm Std: 1.0nm y x hole centroid Average centroid Hole edge Overlay accuracy: Average absolute deviation Hole Size (nm) AveDev-x =1.1 nm AveDev-y =1.3 nm 2-hole: A Centroid Deviation (nm) Hole Pitch (nm) AveDev-x =0.9 nm AveDev-y =1.5 nm 2-hole: B Centroid Deviation (nm) Hole Pitc x ~1nm y ~1.5 nm 10 July 9, 2012 H. Yi H.-S. P. Wong, Adv. Mater., 2012

11 3-Hole Pattern Analysis A B C 4 Mean: 39.7nm Std: 1.9nm 4 Mean: 14.8 nm SD: 2.4 nm hole pattern 70nmx145nm ±2.4 nm 38±1nm Mean: 37.7nm Std: 1.0nm 3-hole pattern Hole Size (nm) Hole Pitch (nm) Hole Pitch (nm) 4 3 AveDev-x=1.1 nm AveDev-y=1.8 nm 3-hole: A AveDev-x=1.5 nm AveDev-y=1.8 nm 3-hole: B AveDev-x=1.3 nm AveDev-y=1.9 nm 3-hole: C x ~1.5 nm y ~1.9 nm Centroid Deviation (nm) H. Yi H.-S. P. Wong, Adv. Mater., July 9, 2012

12 Design Space for 2-3 Hole Guiding Templates Parameters: template size template shape thickness pattern density 12 July 9, 2012 H. Yi H.-S. P. Wong, Adv. Mater., 2012

13 IBM 22-nm SRAM Contact Holes Layout connection 110 nm 90nm C1 1 st exposure C2 2 nd exposure 6T-SRAM Cell *Double pattern and double etch process were used to achieve these 26 nm size contact holes. Haran, B. S. Proc. IEDM (2008). 13 July 9, 2012

14 DSA-Aware Contact Holes for SRAM Active region Polysilicon gate Contact hole Connection round hole elliptical hole Template mask layout Size: 56nm (contacts) 56 x 70 nm (connection) Pitch: x-axis=90nm y-axis=110nm round hole 14 July 9, 2012

15 DSA Patterned Contact Holes for SRAM Template SEM DSA SEM 200 nm 200 nm 300mm wafer 193 nm immersion Litho Industrial compatible sol. a 3 1 Mean: 24.8 nm SD: 3.0 nm Mean: 66.4 nm SD: 6.9 nm Hole Size (nm) b AveDev-x= 0.9 nm AveDev-y= 1.2 nm Template ~ 66.4±7nm Contact hole ~ 25±3nm Centroid x ~0.9 nm Centroid y ~1.2 nm Centroid Deviation (nm) X.-Y. Bao, H. Yi H.-S. P. Wong, IEDM, p. 167, July 9, 2012

16 Contact Holes for NAND (strategy) 2-hole templates for NAND A B 60x110nm 15 nm hole size 40 nm pitch (source: UBM Techinsights) Rotate to fit 30nm pitch 40 nm 30 nm 48.6 Extend to 15-nm NAND X.-Y. Bao, H. Yi H.-S. P. Wong, IEDM, p. 167, July 9, 2012

17 Contact holes for DRAM (strategy) 3-hole templates for DRAM 70nm space 90nm pitch Storage Node Contact Bit-line Contact 145nm space 165nm pitch 3 contacts per active island (2 storage and one bitline) Example of 3x-nm DRAM (Source: Chipworks) 20nm wide eye-guiding grids Shrink to 2x-nm DRAM 3-hole templates (70x145nm) 17 July 9, 2012 X.-Y. Bao, H. Yi H.-S. P. Wong, IEDM, p. 167, 2011

18 Nangate cell library: J. Stork, TI (2007), Stanford seminar

19 Contacts for Random Logic Circuit Example: Conventional 45nm HA-X1 Layout Contact hole layout Design 1 Design 2 Source: Nangate 45nm Open Cell Library Challenges for DSA patterning Overcome resolution limits Irregular contact distribution Guiding template design Optimal template size and shape Courtesy of Jason Sweis, Cadence Design Systems 19 July 9, 2012

20 DSA-Aware Layout: Simplifying Template Design Starting Point: Gridded Design Rule (GDR) Scan-D Flip Flop designed with Gridded Design Rules Lines: parallel, single width & pitch Contacts: positioned only at predetermined grid points Source: Transistor sizes and connections (pin-out) unchanged No area penalty Conventional HA-X1 Layout DSA-Aware HA-X1 Layout Metal 1 Poly Active Region Contact M2 vertical direction routing not shown for the sake of clarity 20 July 9, 2012

21 Random Logic Circuit Patterning: 1-bit Half Adder DSA-aware HA-X1 Contact Hole Layout Template defects DSA heal defects Template (SEM) DSA results (SEM) Scale bar: 200nm 21 July 9, 2012

22 Random Logic Circuit Patterning: 1-bit Half Adder Template defects Scale bar: 200nm 22 July 9, 2012

23 Random Logic Circuit Patterning: 1-bit Half Adder DSA heals defects Scale bar: 200nm 23 July 9, 2012

24 Random Logic Circuit Patterning: 1-bit Full Adder Conventional FA-X1 (Nangate 45nm Open Cell Library) DSA-aware FA-X1 Contact Hole Layout Merged templates don t affect DSA holes overlay accuracy and size variation strongly 4 Mean: 15.0nm Std: 1.4nm 4 3 Mean: 51.1nm Std: 1.3nm 8 6 Mean Deviation-X: 0.7nm 4 Mean Deviation-Y: 0.8nm Hole Size (nm) Template Size (nm) Centroid Deviation (nm) Green histogram: represent holes in merged templates Centroid Deviation (nm) 24 July 9, 2012

25 Random Logic Circuit Patterning: 1-bit Full Adder Merged templates don t affect DSA holes overlay accuracy and size variation Green histogram: represent holes in merged templates 4 3 Mean: 15.0nm Std: 1.4nm 4 3 Mean: 51.1nm Std: 1.3nm Hole Size (nm) Template Size (nm) 8 6 Mean Deviation-X: 0.7nm 4 Mean Deviation-Y: 0.8nm 4 Scale bar: 200nm Centroid Deviation (nm) Centroid Deviation (nm) 25 July 9, 2012

26 DSA for Contact Hole Patterning DSA Evolution Infinite periodic Boundary periodic nm immersion + DSA = Extension of double-patterning 26 July 9, 2012

27 Looking Forward Defectivity 300 mm wafer, statistical data EDA tool Think OPC, DFM Application of DSA must be transparent to designers Develop DSA-aware template design rules Experiments, modeling 27 July 9, 2012

28 Graduated Student and Post-Doc Li-Wen Chang PhD 2010 Currently with Xilinx Xinyu Bao Post-doc ( ) Currently with AMAT 28 July 9, 2012

29 Collaborators Applied Materials (Chris Bencher and team) Prof. Subhasish Mitra (Stanford, EE & CS Dept.) 29 July 9, 2012

30 Sponsors and Collaborators 30 July 9, 2012