Chapter 4. Combinational Logic

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1 Chapter 4. Combinational Logic Tong In Oh 1

2 4.1 Introduction Combinational logic: Logic gates Output determined from only the present combination of inputs Specified by a set of Boolean functions Sequential logic: Employ storage elements in addition to logic gates Output determined by present inputs and the state of the storage elements Specified by a time sequence of inputs and internal states 2

3 4.2 Combinational Circuits Interconnection of logic gates React to the input signals and produce the output signal Transforming binary information For n input variables, m Boolean functions (one for each output variable) FIGURE 4.1 Block diagram of combinational circuit 3

4 Goals To formulate systematic analysis Design procedures for combinational circuits Provide a useful catalog of elementary functions Two tasks Analyze the behavior of a given logic circuit Synthesize a circuit for a given behavior The most important standard combinational circuits Adders, subtractors, comparators, decoders, encoders, and multiplexers 4

5 4.3 Analysis Procedure Determine the function implemented in the circuit Boolean functions, a truth table, explanation of the circuit operation from the given logic diagram 1. Combinational and not sequential? No feedback paths or memory elements 2. To obtain the output Boolean functions 1. Label all gate outputs that are a function of input variables with arbitrary symbols but with meaningful names. Determine the Boolean functions for each gate output. 2. Label the gates that are a function of input variables and previously labeled gates with other arbitrary symbols. Find the Boolean functions for these gates. 3. Repeat the process outlined in step 2 until the outputs of the circuit are obtained. 4. By repeated substitution of previously defined functions, obtain the output Boolean functions in terms of input variables. 5

6 Determine the function from a given logic diagram to a set of Boolean functions or a truth table FIGURE 4.2 Logic diagram for analysis example 6

7 Truth Table To obtain truth table 1. Determine the number of input variables in the circuit. List the binary numbers from 0 to (2 n - 1) in a table. 2. Label the outputs of selected gates with arbitrary symbols. 3. Obtain the truth table for the outputs of those gates which are a function of the input variables only. 4. Proceed to obtain the truth table for the outputs of those gates which are a function of previously defined values until the columns for all outputs are determined Identical to the truth table of the full adder 7

8 4.4 Design Procedure Start from the specification of the design objective Culminate in a logic circuit diagram or a set of Boolean functions 1. From the specifications of the circuit, determine the required number of inputs and outputs and assign a symbol to each. 2. Derive the truth table that defines the required relationship between inputs and outputs. 3. Obtain the simplified Boolean functions for each output as a function of the input variables. 4. Draw the logic diagram and verify the correctness of the design (manually or by simulation). Interpret verbal specifications correctly in the truth table Constraints Number of gates, number of inputs to a gate, propagation time of the signal through the gates, number of interconnections, limitations of the driving capability of each gate, various other criteria 8

9 Code Conversion Example Code converter: transformation Ex. Convert BCD to the excess-3 code for decimal digits Four inputs, four outputs 10 combinations except of 6 don t care combinations 9 FIGURE 4.3 Maps for BCD-to-excess-3 code converter

10 FIGURE 4.4 Logic diagram for BCD-to-excess- 3 code converter 10

12 Half Adder Need two binary inputs (augend, addend) and two binary outputs (sum, carry) FIGURE 4.5 Implementation of half adder 12

13 Full Adder Process of addition: Bit-by-bit basis, right to left, beginning with the least significant bit Consider the addition at each position and possible carry bit from the previous position Three inputs and two outputs 13

14 FIGURE 4.7 Implementation of full adder in sum-of-products form FIGURE 4.8 Implementation of full adder with two half adders and an OR gate 14

16 Carry Propagation For N-bit adder, 2n gate levels for carry to propagate from input to output Reducing the carry propagation delay time Employ faster gates with reduced delays To increase the complexity of the equipment (in a parallel adder) Principle of carry lookahead logic FIGURE 4.10 Full adder with P and G shown 16

17 Speed of operation Expense of additional complexity FIGURE 4.11 Logic diagram of carry lookahead generator + 17

19 Binary Subtractor A-B: Adding A to 2 s complement of B 2 s complement: inverters and sum through the input carry 19 FIGURE 4.13 Four-bit adder subtractor (with overflow detection)

20 Overflow Detect from the end carry out of the most significant position When unsigned numbers Consider with the last two carries together When signed numbers (Considering the leftmost sign bit and negative numbers as 2 s complement form) = If not equal, overflow has occurred 20

22 Block diagram of a BCD adder 22

23 4.7 Binary Multiplier J multiplier bits K multiplicand bits (JXK) AND gates (J-1) K-bit adders Result: product of (J+K) bits FIGURE 4.15 Two-bit by two-bit binary multiplier 23

24 FIGURE 4.16 Four-bit by three-bit binary multiplier 24

25 4.8 Magnitude Comparator Regularity Algorithm FIGURE 4.17 Four-bit magnitude comparator 25

26 4.9 Decoders Convert binary information from n input lines to a maximum of 2 n unique output lines 2 n (or fewer) minterms of n input variables Generate a unique output N-to-M line decoder Code converter FIGURE 4.18 Three-to-eight-line decoder 26

27 Decoder-Demultiplexer 0 A decoder with enable input can function as a demultiplexer Ex) one to four line demultiplexer (E: data input line, A and B: selection inputs) FIGURE 4.19 Two-to-four-line decoder with enable input 27

28 Larger Decoder Circuit FIGURE decoder constructed with two 3 8 decoders 28

29 Combinational Logic Implementation FIGURE 4.21 Implementation of a full adder with a decoder 29

30 Encoders 2 n (or fewer) input lines and n output lines Assume only one input has a value of 1 at any given time Must establish an input priority Ambiguities of all 0 s inputs 30

31 Priority Encoder V: valid bit indicator FIGURE 4.23 Four-input priority encoder FIGURE 4.22 Maps for a priority encoder 31

32 Multiplexers (MUX) Select binary information from one of many input lines and directs it to a single output line 2 n input lines and n selection lines, a common destination Electronic switch that selects one of two sources Data selector (providing a path from the selected input to the output) FIGURE 4.24 Two-to-one-line multiplexer 32

33 Decoder FIGURE 4.25 Four-to-one-line multiplexer 33

34 Multiple-bit Selection Logic FIGURE 4.26 multiplexer Quadruple two-to-one-line 34

35 Boolean Function Implementation Bolean function of n variables with a multiplexer with n-1 selection inputs and 2 n-1 data inputs FIGURE 4.27 Implementing a Boolean function with a multiplexer 35

36 FIGURE 4.28 Implementing a four-input function with a multiplexer 36

37 Three-State Gates A multiplexer constructed with three-state gates The third state: high impedance state Behave like an open circuit No logic significance Not affected by the inputs to the gate Buffer gate FIGURE 4.29 Graphic symbol for a three-state buffer Multiplexers with three- FIGURE 4.30 state gates 37

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