ENGR 303 Introduction to Logic Design Lecture 7. Dr. Chuck Brown Engineering and Computer Information Science Folsom Lake College

Size: px
Start display at page:

Download "ENGR 303 Introduction to Logic Design Lecture 7. Dr. Chuck Brown Engineering and Computer Information Science Folsom Lake College"

Transcription

1 Introduction to Logic Design Lecture 7 Dr. Chuck Brown Engineering and Computer Information Science Folsom Lake College

2 Outline for Todays Lecture Shifter Multiplier / Divider Memory <2>

3 Shifters Logical shifter: shifts value to left or right and fills empty spaces with 0 s Ex: >> 2 = Ex: << 2 = Arithmetic shifter: same as logical shifter, but on right shift, fills empty spaces with the old most significant bit (msb). Ex: >>> 2 = Ex: <<< 2 = Rotator: rotates bits in a circle, such that bits shifted off one end are shifted into the other end Ex: ROR 2 = Ex: ROL 2 = <3> 5-<3>

4 Shifters Logical shifter: Ex: >> 2 = Ex: << 2 = Arithmetic shifter: Ex: >>> 2 = Ex: <<< 2 = Rotator: Ex: ROR 2 = Ex: ROL 2 = <4>

5 Shifter Design A 3 A 2 A 1 A 0 shamt 1: S 1: Y 3 shamt 1:0 A 3:0 >> Y 3: S 1:0 Y S 1:0 10 Y S 1:0 10 Y 0 11 <5>

6 Shifters as Multipliers, Dividers A << N = A 2 N Example: << 2 = (1 2 2 = 4) Example: << 2 = ( = -12) A >>> N = A 2 N Example: >>> 2 = (8 2 2 = 2) Example: >>> 2 = ( = -4) <6>

7 Multipliers Partial products formed by multiplying a single digit of the multiplier with multiplicand Shifted partial products summed to form result Decimal 230 x multiplicand multiplier partial products result + Binary 0101 x x 42 = x 7 = 35 <7>

8 4 x 4 Multiplier A B 4 x 4 P 8 A 3 A 2 A 1 A 0 B 0 B 1 0 A 3 A 2 A 1 A 0 0 x B 3 B 2 B 1 B 0 B 2 A 3 B 0 A 2 B 0 A 1 B 0 A 0 B 0 A 3 B 1 A 2 B 1 A 1 B 1 A 0 B 1 0 A 3 B 2 A 2 B 2 A 1 B 2 A 0 B 2 B 3 + A 3 B 3 A 2 B 3 A 1 B 3 A 0 B 3 P 7 P 6 P 5 P 4 P 3 P 2 P 1 P 0 0 P 7 P 6 P 5 P 4 P 3 P 2 P 1 P 0 <8>

9 0 1 4 x 4 Divider 0 B 3 0 B 2 0 B 1 A 3 B 0 Legend R B Q 3 1 R B C out C in D N R' C out + D C in A 2 N Q 2 Q 1 Q 0 R 3 R 2 R 1 A 1 A 0 R R' A/B = Q + R/B Algorithm: R = 0 for i = N-1 to 0 R = {R << 1. A i } D = R - B if D < 0, Q i =0, R =R else Q i =1, R =D R =R <9>

10 Memory Arrays Efficiently store large amounts of data 3 common types: Dynamic random access memory (DRAM) Static random access memory (SRAM) Read only memory (ROM) M-bit data value read/ written at each unique N-bit address Address N Array M Data <10>

11 Memory Arrays 2-dimensional array of bit cells Each bit cell stores one bit N address bits and M data bits: 2 N rows and M columns Depth: number of rows (number of words) Width: number of columns (size of word) Array size: depth width = 2 N M Address N Array M Data Address Data Address 2 Array depth Data width <11>

12 Memory Array Example bit array Number of words: 4 Word size: 3-bits For example, the 3-bit word at address 10 is 100 Address Data Address 2 Array depth Data width <12>

13 Memory Arrays Address word x 32-bit Array 32 Data <13>

14 Memory Array Bit Cells wordline bit bitline bitline = bitline = wordline = 1 wordline = 0 bitline = bitline = wordline = 1 wordline = 0 (a) (b) <14>

15 Memory Array Bit Cells bitline wordline bit bitline = 0 bitline = Z wordline = 1 wordline = 0 bitline = 1 bitline = Z wordline = 1 wordline = 0 (a) (b) <15>

16 Memory Array Wordline: like an enable single row in memory array read/written corresponds to unique address only one wordline HIGH at once 2:4 Decoder bitline 2 bitline 1 bitline 0 11 wordline 3 Address 2 10 wordline 2 01 wordline 1 00 wordline 0 Data 2 Data 1 Data 0 <16>

17 Types of Memory Random access memory (RAM): volatile Read only memory (ROM): nonvolatile <17>

18 RAM: Random Access Memory Volatile: loses its data when power off Read and written quickly Main memory in your computer is RAM (DRAM) Historically called random access memory because any data word accessed as easily as any other (in contrast to sequential access memories such as a tape recorder) <18>

19 ROM: Read Only Memory Nonvolatile: retains data when power off Read quickly, but writing is impossible or slow Flash memory in cameras, thumb drives, and digital cameras are all ROMs Historically called read only memory because ROMs were written at manufacturing time or by burning fuses. Once ROM was configured, it could not be written again. This is no longer the case for Flash memory and other types of ROMs. <19>

20 Types of RAM DRAM (Dynamic random access memory) SRAM (Static random access memory) Differ in how they store data: DRAM uses a capacitor SRAM uses cross-coupled inverters <20>

21 Memory Arrays Review 2:4 Decoder bitline 2 bitline 1 bitline 0 11 wordline 3 Address wordline 2 wordline 1 wordline 0 Data 2 Data 1 Data 0 DRAM bit cell: SRAM bit cell: bitline bitline bitline wordline wordline <21>

Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1>

Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1> Chapter 5 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 5 Chapter 5 :: Topics Introduction Arithmetic Circuits umber Systems Sequential Building

More information

Digital Logic & Computer Design CS Professor Dan Moldovan Spring 2010

Digital Logic & Computer Design CS Professor Dan Moldovan Spring 2010 Digital Logic & Computer Design CS 434 Professor Dan Moldovan Spring 2 Copyright 27 Elsevier 5- Chapter 5 :: Digital Building Blocks Digital Design and Computer Architecture David Money Harris and Sarah

More information

Chapter 5 - Memory. Sarah L. Harris and David Money Harris. Digital Design and Computer Architecture: ARM Edi>on 2015

Chapter 5 - Memory. Sarah L. Harris and David Money Harris. Digital Design and Computer Architecture: ARM Edi>on 2015 Chapter 5 - Memory Digital Design and Computer Architecture: ARM Edi*on Sarah L. Harris and David Money Harris Chapter 5 Chapter 5 :: Topics Introduc*on Arithme*c Circuits Number Systems Sequen*al

More information

Memories. Design of Digital Circuits 2017 Srdjan Capkun Onur Mutlu.

Memories. Design of Digital Circuits 2017 Srdjan Capkun Onur Mutlu. Memories Design of Digital Circuits 2017 Srdjan Capkun Onur Mutlu http://www.syssec.ethz.ch/education/digitaltechnik_17 Adapted from Digital Design and Computer Architecture, David Money Harris & Sarah

More information

CSEE 3827: Fundamentals of Computer Systems. Storage

CSEE 3827: Fundamentals of Computer Systems. Storage CSEE 387: Fundamentals of Computer Systems Storage The big picture General purpose processor (e.g., Power PC, Pentium, MIPS) Internet router (intrusion detection, pacet routing, etc.) WIreless transceiver

More information

Arithmetic Logic Unit. Digital Computer Design

Arithmetic Logic Unit. Digital Computer Design Arithmetic Logic Unit Digital Computer Design Arithmetic Circuits Arithmetic circuits are the central building blocks of computers. Computers and digital logic perform many arithmetic functions: addition,

More information

Arithmetic Circuits. Design of Digital Circuits 2014 Srdjan Capkun Frank K. Gürkaynak.

Arithmetic Circuits. Design of Digital Circuits 2014 Srdjan Capkun Frank K. Gürkaynak. Arithmetic Circuits Design of Digital Circuits 2014 Srdjan Capkun Frank K. Gürkaynak http://www.syssec.ethz.ch/education/digitaltechnik_14 Adapted from Digital Design and Computer Architecture, David Money

More information

Chapter 3. SEQUENTIAL Logic Design. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris.

Chapter 3. SEQUENTIAL Logic Design. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. SEQUENTIAL Logic Design Chapter 3 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 3 Chapter 3 :: Topics Introduction Latches and Flip-Flops Synchronous

More information

ECE 2300 Digital Logic & Computer Organization

ECE 2300 Digital Logic & Computer Organization ECE 2300 Digital Logic & Computer Organization Spring 201 Memories Lecture 14: 1 Announcements HW6 will be posted tonight Lab 4b next week: Debug your design before the in-lab exercise Lecture 14: 2 Review:

More information

Memory & Logic Array. Lecture # 23 & 24 By : Ali Mustafa

Memory & Logic Array. Lecture # 23 & 24 By : Ali Mustafa Memory & Logic Array Lecture # 23 & 24 By : Ali Mustafa Memory Memory unit is a device to which a binary information is transferred for storage. From which information is retrieved when needed. Types of

More information

+1 (479)

+1 (479) Memory Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Memory Arrays Memory Arrays Random Access Memory Serial

More information

! Memory Overview. ! ROM Memories. ! RAM Memory " SRAM " DRAM. ! This is done because we can build. " large, slow memories OR

! Memory Overview. ! ROM Memories. ! RAM Memory  SRAM  DRAM. ! This is done because we can build.  large, slow memories OR ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 2: April 5, 26 Memory Overview, Memory Core Cells Lecture Outline! Memory Overview! ROM Memories! RAM Memory " SRAM " DRAM 2 Memory Overview

More information

Introduction to SRAM. Jasur Hanbaba

Introduction to SRAM. Jasur Hanbaba Introduction to SRAM Jasur Hanbaba Outline Memory Arrays SRAM Architecture SRAM Cell Decoders Column Circuitry Non-volatile Memory Manufacturing Flow Memory Arrays Memory Arrays Random Access Memory Serial

More information

Digital Design, Kyung Hee Univ. Chapter 7. Memory and Programmable Logic

Digital Design, Kyung Hee Univ. Chapter 7. Memory and Programmable Logic Chapter 7. Memory and Programmable Logic 1 7.1 Introduction Memory unit: A device to which binary information is transferred for storage and from which information is retrieved when needed for processing

More information

Introduction to Semiconductor Memory Dr. Lynn Fuller Webpage:

Introduction to Semiconductor Memory Dr. Lynn Fuller Webpage: ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Introduction to Semiconductor Memory Webpage: http://people.rit.edu/lffeee 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585) 475-2035

More information

Lecture 11 SRAM Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010

Lecture 11 SRAM Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010 EE4800 CMOS Digital IC Design & Analysis Lecture 11 SRAM Zhuo Feng 11.1 Memory Arrays SRAM Architecture SRAM Cell Decoders Column Circuitryit Multiple Ports Outline Serial Access Memories 11.2 Memory Arrays

More information

Lecture Topics. Announcements. Today: Integer Arithmetic (P&H ) Next: continued. Consulting hours. Introduction to Sim. Milestone #1 (due 1/26)

Lecture Topics. Announcements. Today: Integer Arithmetic (P&H ) Next: continued. Consulting hours. Introduction to Sim. Milestone #1 (due 1/26) Lecture Topics Today: Integer Arithmetic (P&H 3.1-3.4) Next: continued 1 Announcements Consulting hours Introduction to Sim Milestone #1 (due 1/26) 2 1 Overview: Integer Operations Internal representation

More information

The CPU and Memory. How does a computer work? How does a computer interact with data? How are instructions performed? Recall schematic diagram:

The CPU and Memory. How does a computer work? How does a computer interact with data? How are instructions performed? Recall schematic diagram: The CPU and Memory How does a computer work? How does a computer interact with data? How are instructions performed? Recall schematic diagram: 1 Registers A register is a permanent storage location within

More information

Memory and Programmable Logic

Memory and Programmable Logic Memory and Programmable Logic Mano & Ciletti Chapter 7 By Suleyman TOSUN Ankara University Outline RAM Memory decoding Error detection and correction ROM Programmable Logic Array (PLA) Programmable Array

More information

Memory. Outline. ECEN454 Digital Integrated Circuit Design. Memory Arrays. SRAM Architecture DRAM. Serial Access Memories ROM

Memory. Outline. ECEN454 Digital Integrated Circuit Design. Memory Arrays. SRAM Architecture DRAM. Serial Access Memories ROM ECEN454 Digital Integrated Circuit Design Memory ECEN 454 Memory Arrays SRAM Architecture SRAM Cell Decoders Column Circuitry Multiple Ports DRAM Outline Serial Access Memories ROM ECEN 454 12.2 1 Memory

More information

CENG 4480 L09 Memory 3

CENG 4480 L09 Memory 3 CENG 4480 L09 Memory 3 Bei Yu Chapter 11 Memories Reference: CMOS VLSI Design A Circuits and Systems Perspective by H.E.Weste and D.M.Harris 1 Memory Arrays Memory Arrays Random Access Memory Serial Access

More information

Semiconductor Memories: RAMs and ROMs

Semiconductor Memories: RAMs and ROMs Semiconductor Memories: RAMs and ROMs Lesson Objectives: In this lesson you will be introduced to: Different memory devices like, RAM, ROM, PROM, EPROM, EEPROM, etc. Different terms like: read, write,

More information

Chapter 6 (Lect 3) Counters Continued. Unused States Ring counter. Implementing with Registers Implementing with Counter and Decoder

Chapter 6 (Lect 3) Counters Continued. Unused States Ring counter. Implementing with Registers Implementing with Counter and Decoder Chapter 6 (Lect 3) Counters Continued Unused States Ring counter Implementing with Registers Implementing with Counter and Decoder Sequential Logic and Unused States Not all states need to be used Can

More information

Introduction to CMOS VLSI Design Lecture 13: SRAM

Introduction to CMOS VLSI Design Lecture 13: SRAM Introduction to CMOS VLSI Design Lecture 13: SRAM David Harris Harvey Mudd College Spring 2004 1 Outline Memory Arrays SRAM Architecture SRAM Cell Decoders Column Circuitry Multiple Ports Serial Access

More information

Lecture 14: CAMs, ROMs, and PLAs

Lecture 14: CAMs, ROMs, and PLAs Introduction to CMOS VLSI Design Lecture 4: CAMs, ROMs, and PLAs David Harris Harvey Mudd College Spring 24 Outline Content-Addressable Memories Read-Only Memories Programmable Logic Arrays 4: CAMs, ROMs,

More information

Very Large Scale Integration (VLSI)

Very Large Scale Integration (VLSI) Very Large Scale Integration (VLSI) Lecture 8 Dr. Ahmed H. Madian ah_madian@hotmail.com Content Array Subsystems Introduction General memory array architecture SRAM (6-T cell) CAM Read only memory Introduction

More information

Computer Organization and Assembly Language (CS-506)

Computer Organization and Assembly Language (CS-506) Computer Organization and Assembly Language (CS-506) Muhammad Zeeshan Haider Ali Lecturer ISP. Multan ali.zeeshan04@gmail.com https://zeeshanaliatisp.wordpress.com/ Lecture 2 Memory Organization and Structure

More information

Semiconductor Memory Classification

Semiconductor Memory Classification ESE37: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec 6: November, 7 Memory Overview Today! Memory " Classification " Architecture " Memory core " Periphery (time permitting)!

More information

ELCT 912: Advanced Embedded Systems

ELCT 912: Advanced Embedded Systems Advanced Embedded Systems Lecture 2: Memory and Programmable Logic Dr. Mohamed Abd El Ghany, Memory Random Access Memory (RAM) Can be read and written Static Random Access Memory (SRAM) Data stored so

More information

Lecture 13: SRAM. Slides courtesy of Deming Chen. Slides based on the initial set from David Harris. 4th Ed.

Lecture 13: SRAM. Slides courtesy of Deming Chen. Slides based on the initial set from David Harris. 4th Ed. Lecture 13: SRAM Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Memory Arrays SRAM Architecture SRAM Cell Decoders Column Circuitry Multiple Ports

More information

Digital Integrated Circuits Lecture 13: SRAM

Digital Integrated Circuits Lecture 13: SRAM Digital Integrated Circuits Lecture 13: SRAM Chih-Wei Liu VLSI Signal Processing LAB National Chiao Tung University cwliu@twins.ee.nctu.edu.tw DIC-Lec13 cwliu@twins.ee.nctu.edu.tw 1 Outline Memory Arrays

More information

Slide Set 10. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary

Slide Set 10. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary Slide Set 10 for ENEL 353 Fall 2017 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Fall Term, 2017 SN s ENEL 353 Fall 2017 Slide Set 10 slide

More information

Semiconductor Memory Classification. Today. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. CPU Memory Hierarchy.

Semiconductor Memory Classification. Today. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. CPU Memory Hierarchy. ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec : April 4, 7 Memory Overview, Memory Core Cells Today! Memory " Classification " ROM Memories " RAM Memory " Architecture " Memory core " SRAM

More information

EECS 3201: Digital Logic Design Lecture 7. Ihab Amer, PhD, SMIEEE, P.Eng.

EECS 3201: Digital Logic Design Lecture 7. Ihab Amer, PhD, SMIEEE, P.Eng. EECS 3201: Digital Logic Design Lecture 7 Ihab Amer, PhD, SMIEEE, P.Eng. 2x2 binary multiplier 2 4x4 Array Multiplier 3 Multiplexer (MUX) 4 MUX Implementations 5 Wider MUXes 6 Logic with MUXes 7 Reducing

More information

SRAM. Introduction. Digital IC

SRAM. Introduction. Digital IC SRAM Introduction Outline Memory Arrays SRAM Architecture SRAM Cell Decoders Column Circuitry Multiple Ports Serial Access Memories Memory Arrays Memory Arrays Random Access Memory Serial Access Memory

More information

CENG 4480 L09 Memory 2

CENG 4480 L09 Memory 2 CENG 4480 L09 Memory 2 Bei Yu Reference: Chapter 11 Memories CMOS VLSI Design A Circuits and Systems Perspective by H.E.Weste and D.M.Harris 1 v.s. CENG3420 CENG3420: architecture perspective memory coherent

More information

Logic and Computer Design Fundamentals. Chapter 8 Memory Basics

Logic and Computer Design Fundamentals. Chapter 8 Memory Basics Logic and Computer Design Fundamentals Memory Basics Overview Memory definitions Random Access Memory (RAM) Static RAM (SRAM) integrated circuits Arrays of SRAM integrated circuits Dynamic RAM (DRAM) Read

More information

Unit 6 1.Random Access Memory (RAM) Chapter 3 Combinational Logic Design 2.Programmable Logic

Unit 6 1.Random Access Memory (RAM) Chapter 3 Combinational Logic Design 2.Programmable Logic EE 200: Digital Logic Circuit Design Dr Radwan E Abdel-Aal, COE Unit 6.Random Access Memory (RAM) Chapter 3 Combinational Logic Design 2. Logic Logic and Computer Design Fundamentals Part Implementation

More information

Chapter 7. Storage Components

Chapter 7. Storage Components 7. Storage Components 7- Chapter 7. Storage Components ntroduction Storage components store data and perform simple data transformations, such as counting and shifting. Registers, counters, register files,

More information

Microcontroller Systems. ELET 3232 Topic 11: General Memory Interfacing

Microcontroller Systems. ELET 3232 Topic 11: General Memory Interfacing Microcontroller Systems ELET 3232 Topic 11: General Memory Interfacing 1 Objectives To become familiar with the concepts of memory expansion and the data and address bus To design embedded systems circuits

More information

Random Access Memory (RAM)

Random Access Memory (RAM) Random Access Memory (RAM) EED2003 Digital Design Dr. Ahmet ÖZKURT Dr. Hakkı YALAZAN 1 Overview Memory is a collection of storage cells with associated input and output circuitry Possible to read and write

More information

2000 N + N <100N. When is: Find m to minimize: (N) m. N log 2 C 1. m + C 3 + C 2. ESE534: Computer Organization. Previously. Today.

2000 N + N <100N. When is: Find m to minimize: (N) m. N log 2 C 1. m + C 3 + C 2. ESE534: Computer Organization. Previously. Today. ESE534: Computer Organization Previously Day 5: February 1, 2010 Memories Arithmetic: addition, subtraction Reuse: pipelining bit-serial (vectorization) shared datapath elements FSMDs Area/Time Tradeoffs

More information

Memory Basics. Course Outline. Introduction to Digital Logic. Copyright 2000 N. AYDIN. All rights reserved. 1. Introduction to Digital Logic.

Memory Basics. Course Outline. Introduction to Digital Logic. Copyright 2000 N. AYDIN. All rights reserved. 1. Introduction to Digital Logic. Introduction to Digital Logic Prof. Nizamettin AYDIN naydin@yildiz.edu.tr naydin@ieee.org ourse Outline. Digital omputers, Number Systems, Arithmetic Operations, Decimal, Alphanumeric, and Gray odes. inary

More information

Basic Organization Memory Cell Operation. CSCI 4717 Computer Architecture. ROM Uses. Random Access Memory. Semiconductor Memory Types

Basic Organization Memory Cell Operation. CSCI 4717 Computer Architecture. ROM Uses. Random Access Memory. Semiconductor Memory Types CSCI 4717/5717 Computer Architecture Topic: Internal Memory Details Reading: Stallings, Sections 5.1 & 5.3 Basic Organization Memory Cell Operation Represent two stable/semi-stable states representing

More information

Lecture 20: CAMs, ROMs, PLAs

Lecture 20: CAMs, ROMs, PLAs Lecture 2: CAMs, ROMs, PLAs Outline Content-Addressable Memories Read-Only Memories Programmable Logic Arrays 2: CAMs, ROMs, and PLAs CMOS VLSI Design 4th Ed. 2 CAMs Extension of ordinary memory (e.g.

More information

ELCT 501: Digital System Design

ELCT 501: Digital System Design ELCT 501: Digital System Lecture 4: CAD tools (Continued) Dr. Mohamed Abd El Ghany, Basic VHDL Concept Via an Example Problem: write VHDL code for 1-bit adder 4-bit adder 2 1-bit adder Inputs: A (1 bit)

More information

Lecture Topics. Announcements. Today: Integer Arithmetic (P&H ) Next: The MIPS ISA (P&H ) Consulting hours. Milestone #1 (due 1/26)

Lecture Topics. Announcements. Today: Integer Arithmetic (P&H ) Next: The MIPS ISA (P&H ) Consulting hours. Milestone #1 (due 1/26) Lecture Topics Today: Integer Arithmetic (P&H 3.1-3.4) Next: The MIPS ISA (P&H 2.1-2.14) 1 Announcements Consulting hours Milestone #1 (due 1/26) Milestone #2 (due 2/2) 2 1 Review: Integer Operations Internal

More information

ECE 485/585 Microprocessor System Design

ECE 485/585 Microprocessor System Design Microprocessor System Design Lecture 4: Memory Hierarchy Memory Taxonomy SRAM Basics Memory Organization DRAM Basics Zeshan Chishti Electrical and Computer Engineering Dept Maseeh College of Engineering

More information

CS 261 Fall Mike Lam, Professor. Memory

CS 261 Fall Mike Lam, Professor. Memory CS 261 Fall 2016 Mike Lam, Professor Memory Topics Memory hierarchy overview Storage technologies SRAM DRAM PROM / flash Disk storage Tape and network storage I/O architecture Storage trends Latency comparisons

More information

ECE 2300 Digital Logic & Computer Organization. Caches

ECE 2300 Digital Logic & Computer Organization. Caches ECE 23 Digital Logic & Computer Organization Spring 217 s Lecture 2: 1 Announcements HW7 will be posted tonight Lab sessions resume next week Lecture 2: 2 Course Content Binary numbers and logic gates

More information

CS24: INTRODUCTION TO COMPUTING SYSTEMS. Spring 2017 Lecture 13

CS24: INTRODUCTION TO COMPUTING SYSTEMS. Spring 2017 Lecture 13 CS24: INTRODUCTION TO COMPUTING SYSTEMS Spring 2017 Lecture 13 COMPUTER MEMORY So far, have viewed computer memory in a very simple way Two memory areas in our computer: The register file Small number

More information

Memory and Programmable Logic

Memory and Programmable Logic Memory and Programmable Logic Memory units allow us to store and/or retrieve information Essentially look-up tables Good for storing data, not for function implementation Programmable logic device (PLD),

More information

2000 N + N <100N. When is: Find m to minimize: (N) m. N log 2 C 1. m + C 3 + C 2. ESE534: Computer Organization. Previously. Today.

2000 N + N <100N. When is: Find m to minimize: (N) m. N log 2 C 1. m + C 3 + C 2. ESE534: Computer Organization. Previously. Today. ESE534: Computer Organization Previously Day 7: February 6, 2012 Memories Arithmetic: addition, subtraction Reuse: pipelining bit-serial (vectorization) Area/Time Tradeoffs Latency and Throughput 1 2 Today

More information

Introduction read-only memory random access memory

Introduction read-only memory random access memory Memory Interface Introduction Simple or complex, every microprocessorbased system has a memory system. Almost all systems contain two main types of memory: read-only memory (ROM) and random access memory

More information

Clocked Sequential System Design. Multiply Example

Clocked Sequential System Design. Multiply Example Clocked Sequential System Design Example 1 Multipliers (Gradeschool, Modified Gradeschool) Multiply Example (185) (215) 00000000 00000000 ------ 1001101101011111 (39775) 1 0000000000000000

More information

Lecture Objectives. Introduction to Computing Chapter 0. Topics. Numbering Systems 04/09/2017

Lecture Objectives. Introduction to Computing Chapter 0. Topics. Numbering Systems 04/09/2017 Lecture Objectives Introduction to Computing Chapter The AVR microcontroller and embedded systems using assembly and c Students should be able to: Convert between base and. Explain the difference between

More information

Silicon Memories. Why store things in silicon? It s fast!!! Compatible with logic devices (mostly)

Silicon Memories. Why store things in silicon? It s fast!!! Compatible with logic devices (mostly) Memories and SRAM 1 Silicon Memories Why store things in silicon? It s fast!!! Compatible with logic devices (mostly) The main goal is to be cheap Dense -- The smaller the bits, the less area you need,

More information

Computer Arithmetic Multiplication & Shift Chapter 3.4 EEC170 FQ 2005

Computer Arithmetic Multiplication & Shift Chapter 3.4 EEC170 FQ 2005 Computer Arithmetic Multiplication & Shift Chapter 3.4 EEC170 FQ 200 Multiply We will start with unsigned multiply and contrast how humans and computers multiply Layout 8-bit 8 Pipelined Multiplier 1 2

More information

Memory classification:- Topics covered:- types,organization and working

Memory classification:- Topics covered:- types,organization and working Memory classification:- Topics covered:- types,organization and working 1 Contents What is Memory? Cache Memory PC Memory Organisation Types 2 Memory what is it? Usually we consider this to be RAM, ROM

More information

Internal Memory. Computer Architecture. Outline. Memory Hierarchy. Semiconductor Memory Types. Copyright 2000 N. AYDIN. All rights reserved.

Internal Memory. Computer Architecture. Outline. Memory Hierarchy. Semiconductor Memory Types. Copyright 2000 N. AYDIN. All rights reserved. Computer Architecture Prof. Dr. Nizamettin AYDIN naydin@yildiz.edu.tr nizamettinaydin@gmail.com Internal Memory http://www.yildiz.edu.tr/~naydin 1 2 Outline Semiconductor main memory Random Access Memory

More information

Module 6 : Semiconductor Memories Lecture 30 : SRAM and DRAM Peripherals

Module 6 : Semiconductor Memories Lecture 30 : SRAM and DRAM Peripherals Module 6 : Semiconductor Memories Lecture 30 : SRAM and DRAM Peripherals Objectives In this lecture you will learn the following Introduction SRAM and its Peripherals DRAM and its Peripherals 30.1 Introduction

More information

Lecture 13: Memory and Programmable Logic

Lecture 13: Memory and Programmable Logic Lecture 13: Memory and Programmable Logic Syed M. Mahmud, Ph.D ECE Department Wayne State University Aby K George, ECE Department, Wayne State University Contents Introduction Random Access Memory Memory

More information

CENG4480 Lecture 09: Memory 1

CENG4480 Lecture 09: Memory 1 CENG4480 Lecture 09: Memory 1 Bei Yu byu@cse.cuhk.edu.hk (Latest update: November 8, 2017) Fall 2017 1 / 37 Overview Introduction Memory Principle Random Access Memory (RAM) Non-Volatile Memory Conclusion

More information

ECE 341. Lecture # 16

ECE 341. Lecture # 16 ECE 341 Lecture # 16 Instructor: Zeshan Chishti zeshan@ece.pdx.edu November 24, 2014 Portland State University Lecture Topics The Memory System Basic Concepts Semiconductor RAM Memories Organization of

More information

Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks

Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks Charles Eckert Xiaowei Wang Jingcheng Wang Arun Subramaniyan Ravi Iyer Dennis Sylvester David Blaauw Reetuparna Das M-Bits Research

More information

Arithmetic Operations

Arithmetic Operations Arithmetic Operations Arithmetic Operations addition subtraction multiplication division Each of these operations on the integer representations: unsigned two's complement 1 Addition One bit of binary

More information

Let s put together a Manual Processor

Let s put together a Manual Processor Lecture 14 Let s put together a Manual Processor Hardware Lecture 14 Slide 1 The processor Inside every computer there is at least one processor which can take an instruction, some operands and produce

More information

COMPUTER SYSTEM. COMPUTER SYSTEM IB DP Computer science Standard Level ICS3U. COMPUTER SYSTEM IB DP Computer science Standard Level ICS3U

COMPUTER SYSTEM. COMPUTER SYSTEM IB DP Computer science Standard Level ICS3U. COMPUTER SYSTEM IB DP Computer science Standard Level ICS3U C A N A D I A N I N T E R N A T I O N A L S C H O O L O F H O N G K O N G 5.1 Introduction 5.2 Components of a Computer System Algorithm The Von Neumann architecture is based on the following three characteristics:

More information

Design with Microprocessors

Design with Microprocessors Design with Microprocessors Year III Computer Sci. English 1-st Semester Lecture 12: Memory interfacing Typical Memory Hierarchy [1] On-Chip Components Control edram Datapath RegFile ITLB DTLB Instr Data

More information

ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems

ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec 26: November 9, 2018 Memory Overview Dynamic OR4! Precharge time?! Driving input " With R 0 /2 inverter! Driving inverter

More information

Chapter 8 Memory Basics

Chapter 8 Memory Basics Logic and Computer Design Fundamentals Chapter 8 Memory Basics Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Overview Memory definitions Random Access

More information

INSTITUTO SUPERIOR TÉCNICO. Architectures for Embedded Computing

INSTITUTO SUPERIOR TÉCNICO. Architectures for Embedded Computing UNIVERSIDADE TÉCNICA DE LISBOA INSTITUTO SUPERIOR TÉCNICO Departamento de Engenharia Informática Architectures for Embedded Computing MEIC-A, MEIC-T, MERC Lecture Slides Version 3.0 - English Lecture 16

More information

A Review of Chapter 5 and. CSc 2010 Spring 2012 Instructor: Qian Hu

A Review of Chapter 5 and. CSc 2010 Spring 2012 Instructor: Qian Hu A Review of Chapter 5 and Chapter 6 Chapter 5 Computer Systems Organization Von Neumann Architecture 4 Components Memory Input/output ALU Control Unit Two major features Stored program concept Sequential

More information

CMOS Logic Circuit Design Link( リンク ): センター教官講義ノートの下 CMOS 論理回路設計

CMOS Logic Circuit Design   Link( リンク ): センター教官講義ノートの下 CMOS 論理回路設計 CMOS Logic Circuit Design http://www.rcns.hiroshima-u.ac.jp Link( リンク ): センター教官講義ノートの下 CMOS 論理回路設計 Memory Circuits (Part 1) Overview of Memory Types Memory with Address-Based Access Principle of Data Access

More information

Memory Overview. Overview - Memory Types 2/17/16. Curtis Nelson Walla Walla University

Memory Overview. Overview - Memory Types 2/17/16. Curtis Nelson Walla Walla University Memory Overview Curtis Nelson Walla Walla University Overview - Memory Types n n n Magnetic tape (used primarily for long term archive) Magnetic disk n Hard disk (File, Directory, Folder) n Floppy disks

More information

Logical Design of Digital Systems

Logical Design of Digital Systems .5.27 Lecture 3 Summer Semester 27 Table of Content. Combinational circuit design 2. Elementary combinatorial circuits for data transmission 3. Memories 3. Semiconductor memory classification s 3.2. General

More information

Module 5a: Introduction To Memory System (MAIN MEMORY)

Module 5a: Introduction To Memory System (MAIN MEMORY) Module 5a: Introduction To Memory System (MAIN MEMORY) R E F E R E N C E S : S T A L L I N G S, C O M P U T E R O R G A N I Z A T I O N A N D A R C H I T E C T U R E M O R R I S M A N O, C O M P U T E

More information

machine cycle, the CPU: (a) Fetches an instruction, (b) Decodes the instruction, (c) Executes the instruction, and (d) Stores the result.

machine cycle, the CPU: (a) Fetches an instruction, (b) Decodes the instruction, (c) Executes the instruction, and (d) Stores the result. Central Processing Unit (CPU) A processor is also called the CPU, and it works hand in hand with other circuits known as main memory to carry out processing. The CPU is the "brain" of the computer; it

More information

Main Memory (RAM) Organisation

Main Memory (RAM) Organisation Main Memory (RAM) Organisation Computers employ many different types of memory (semi-conductor, magnetic disks, USB sticks, DVDs etc.) to hold data and programs. Each type has its own characteristics and

More information

CS 265. Computer Architecture. Wei Lu, Ph.D., P.Eng.

CS 265. Computer Architecture. Wei Lu, Ph.D., P.Eng. CS 265 Computer Architecture Wei Lu, Ph.D., P.Eng. Part 4: Memory Organization Our goal: understand the basic types of memory in computer understand memory hierarchy and the general process to access memory

More information

Views of Memory. Real machines have limited amounts of memory. Programmer doesn t want to be bothered. 640KB? A few GB? (This laptop = 2GB)

Views of Memory. Real machines have limited amounts of memory. Programmer doesn t want to be bothered. 640KB? A few GB? (This laptop = 2GB) CS6290 Memory Views of Memory Real machines have limited amounts of memory 640KB? A few GB? (This laptop = 2GB) Programmer doesn t want to be bothered Do you think, oh, this computer only has 128MB so

More information

Lecture-14 (Memory Hierarchy) CS422-Spring

Lecture-14 (Memory Hierarchy) CS422-Spring Lecture-14 (Memory Hierarchy) CS422-Spring 2018 Biswa@CSE-IITK The Ideal World Instruction Supply Pipeline (Instruction execution) Data Supply - Zero-cycle latency - Infinite capacity - Zero cost - Perfect

More information

CENG3420 Lecture 08: Memory Organization

CENG3420 Lecture 08: Memory Organization CENG3420 Lecture 08: Memory Organization Bei Yu byu@cse.cuhk.edu.hk (Latest update: February 22, 2018) Spring 2018 1 / 48 Overview Introduction Random Access Memory (RAM) Interleaving Secondary Memory

More information

Design with Microprocessors

Design with Microprocessors Design with Microprocessors Year III Computer Sci. English 1-st Semester Lecture 12: Memory interfacing Typical Memory Hierarchy [1] On-Chip Components Control edram Datapath RegFile ITLB DTLB Instr Data

More information

DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422)

DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) COURSE / CODE DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) Memory In computing, memory refers to the computer hardware devices used to store information for immediate use

More information

Chapter 1 Microprocessor architecture ECE 3120 Dr. Mohamed Mahmoud http://iweb.tntech.edu/mmahmoud/ mmahmoud@tntech.edu Outline 1.1 Computer hardware organization 1.1.1 Number System 1.1.2 Computer hardware

More information

RTL Design (2) Memory Components (RAMs & ROMs)

RTL Design (2) Memory Components (RAMs & ROMs) RTL Design (2) Memory Components (RAMs & ROMs) Memory Components All sequential circuit have a form of memory Register, latches, etc However, the term memory is generally reserved for bits that are stored

More information

Embedded Systems Design: A Unified Hardware/Software Introduction. Outline. Chapter 5 Memory. Introduction. Memory: basic concepts

Embedded Systems Design: A Unified Hardware/Software Introduction. Outline. Chapter 5 Memory. Introduction. Memory: basic concepts Hardware/Software Introduction Chapter 5 Memory Outline Memory Write Ability and Storage Permanence Common Memory Types Composing Memory Memory Hierarchy and Cache Advanced RAM 1 2 Introduction Memory:

More information

Embedded Systems Design: A Unified Hardware/Software Introduction. Chapter 5 Memory. Outline. Introduction

Embedded Systems Design: A Unified Hardware/Software Introduction. Chapter 5 Memory. Outline. Introduction Hardware/Software Introduction Chapter 5 Memory 1 Outline Memory Write Ability and Storage Permanence Common Memory Types Composing Memory Memory Hierarchy and Cache Advanced RAM 2 Introduction Embedded

More information

CS 261 Fall Mike Lam, Professor. Memory

CS 261 Fall Mike Lam, Professor. Memory CS 261 Fall 2017 Mike Lam, Professor Memory Topics Memory hierarchy overview Storage technologies I/O architecture Storage trends Latency comparisons Locality Memory Until now, we've referred to memory

More information

Show how to connect three Full Adders to implement a 3-bit ripple-carry adder

Show how to connect three Full Adders to implement a 3-bit ripple-carry adder Show how to connect three Full Adders to implement a 3-bit ripple-carry adder 1 Reg. A Reg. B Reg. Sum 2 Chapter 5 Computing Components Yet another layer of abstraction! Components Circuits Gates Transistors

More information

M. Sc (CS) (II Semester) Examination, Subject: Computer System Architecture Paper Code: M.Sc-CS-203. Time: Three Hours] [Maximum Marks: 60

M. Sc (CS) (II Semester) Examination, Subject: Computer System Architecture Paper Code: M.Sc-CS-203. Time: Three Hours] [Maximum Marks: 60 M. Sc (CS) (II Semester) Examination, 2012-13 Subject: Computer System Architecture Paper Code: M.Sc-CS-203 Time: Three Hours] [Maximum Marks: 60 Note: Question Number 1 is compulsory. Answer any four

More information

Marching Memory マーチングメモリ. UCAS-6 6 > Stanford > Imperial > Verify 中村維男 Based on Patent Application by Tadao Nakamura and Michael J.

Marching Memory マーチングメモリ. UCAS-6 6 > Stanford > Imperial > Verify 中村維男 Based on Patent Application by Tadao Nakamura and Michael J. UCAS-6 6 > Stanford > Imperial > Verify 2011 Marching Memory マーチングメモリ Tadao Nakamura 中村維男 Based on Patent Application by Tadao Nakamura and Michael J. Flynn 1 Copyright 2010 Tadao Nakamura C-M-C Computer

More information

Memory Technology. (ROM) (Nonvolatile) (Nonvolatile) SerialInIn (SIPO) Erasable Erasable. Erasable Erasable Programmable

Memory Technology. (ROM) (Nonvolatile) (Nonvolatile) SerialInIn (SIPO) Erasable Erasable. Erasable Erasable Programmable M2 Systems M2 line Hierarchy Cache Blocking Cache Aware Programming S, D Virtual Virtual Machines Non-volatile, Persistent NVM Technology Arrays Arrays Random RandomAccess Access Read/Write Read/Write

More information

SAE5C Computer Organization and Architecture. Unit : I - V

SAE5C Computer Organization and Architecture. Unit : I - V SAE5C Computer Organization and Architecture Unit : I - V UNIT-I Evolution of Pentium and Power PC Evolution of Computer Components functions Interconnection Bus Basics of PCI Memory:Characteristics,Hierarchy

More information

Read-only memory Implementing logic with ROM Programmable logic devices Implementing logic with PLDs Static hazards

Read-only memory Implementing logic with ROM Programmable logic devices Implementing logic with PLDs Static hazards Points Addressed in this Lecture Lecture 7: ROM Programmable Logic Devices Professor Peter Cheung Department of EEE, Imperial College London Read-only memory Implementing logic with ROM Programmable logic

More information

EE260: Logic Design, Spring n Integer multiplication. n Booth s algorithm. n Integer division. n Restoring, non-restoring

EE260: Logic Design, Spring n Integer multiplication. n Booth s algorithm. n Integer division. n Restoring, non-restoring EE 260: Introduction to Digital Design Arithmetic II Yao Zheng Department of Electrical Engineering University of Hawaiʻi at Mānoa Overview n Integer multiplication n Booth s algorithm n Integer division

More information

CS429: Computer Organization and Architecture

CS429: Computer Organization and Architecture CS429: Computer Organization and Architecture Dr. Bill Young Department of Computer Sciences University of Texas at Austin Last updated: November 28, 2017 at 14:31 CS429 Slideset 18: 1 Random-Access Memory

More information

CS429: Computer Organization and Architecture

CS429: Computer Organization and Architecture CS429: Computer Organization and Architecture Dr. Bill Young Department of Computer Sciences University of Texas at Austin Last updated: April 9, 2018 at 12:16 CS429 Slideset 17: 1 Random-Access Memory

More information

Digital System Construction

Digital System Construction Digital System Construction FYSIKUM Lecture 4: More VHDL, memory, PRNG Arithmetic Memories Pipelines and buffers Pseudorandom numbers IP core generation in Vivado Introduction to Lab 3 Digital Systemkonstruktion

More information