ECE 3401 Lecture 20. Microprogramming (III) Overview. Single-Cycle Computer Issues. Multiple-Cycle Computer. Single-Cycle SC

Transcription

1 Overview ECE 34 Lecture 2 icroprogramming (III) Part Datapaths Introduction Datapath Example Datapath Representation and Control Word Part 2 A Simple Computer Set Architecture (ISA) Single-Cycle Hardwired Control PC Function Decoder Example Execution Part 3 ultiple Cycle Hardwired Control Single Cycle Computer Issues Sequential Control Design 2 Single-Cycle Computer Issues Shortcoming of Single Cycle Design Complexity of instructions executable in a single cycle is limited Accessing both an instruction and data from a simple single memory impossible A long worst case delay path limits clock frequency and the rate of performing instructions ultiple-cycle Computer Converting the single-cycle computer into a multiple-cycle computer involves: odifications to the datapath/memory odification to the control unit Design of a multiple-cycle hardwired control Handling of Shortcomings The first two shortcomings can be handled by the multiplecycle computer The third shortcoming is dealt with by using a technique called pipelining described in later lectures 3 4 V C ranch Control PC IR(8:6) IR(2:) Extend Datapath odifications ew Path P J L C D A A A A Address memory Single-Cycle SC decoder ero fill IR(2:) F R P J S D W W L C COTROL RW DA AA Constant in FS V C us A D file A A UX us Function unit F A Address out Data out W Data in Address Data in Data memory Data out Use a single memory for both instructions and data Requires new UX with control signal to select between the instruction address from the PC and the data address Requires path from emory Data Out to the instruction register in the control unit Inst. & Data Address ux D us D UX D DATAPATH 5 Inst. & Data emory 6

2 Datapath odifications (Continued) Address 6 x 6 Logic File Additional registers needed to hold operands between cycles Add 8 temporary storage registers to the File File becomes 6 x 6 Addresses to File increase from 3 to 4 bits File addresses come from: The instruction for the Storage Resource registers ( to 7) The control word for the Temporary Storage registers (8 to 5) Add Address Logic to the File to select the register address sources Three new control fields for register address source selection and temporary storage addressing: DX, AX, X 7 8 Control Unit odifications ust hold instruction over the multiple cycles to draw on instruction information throughout instruction execution Requires an (IR) to hold the instruction Load control signal IL Add "hold" operation IR Requires the addition of a "hold" operation to the PC since it only counts up to obtain a new instruction ew encoding for the PC operations uses 2 bits 9 Sequential Control Design To control microoperations over multiple cycles, a Sequential Control replaces the Decoder Input:, Status its, Control State Output: Control Word (odified Datapath Control part) ext State: Control Word (ew Sequencing Control part) Consists of: to store the Control State Combinational Logic to generate the Control Word (both sequencing and datapath control parts) The Combinational Logic is quite complex so we assume that it is implemented by using a PLA or synthesized logic and focus on AS level design Control State Combinational Control Logic ew/ odified Control Word 2 2

3 Control Word S PS Sequencing I L DX AX X FS Datapath Datapath part: field added, and fields DX, AX, and X replace DA, AA, and A, respectively If the S of a field is, e.g., AX = XXX, then AA is concatenated with SA (3bits) field in the IR If the S of a field is, e. g. AX =, then AA = Sequencing part: IL controls the loading of the IR PS controls the operations of the PC S gives the next state of the Control State register E.g., S is 4 bits, the length of the Control State register - 6 states are viewed as adequate for this design D R W W Encoding for Datapath Control DX AX X Code Code FS Code D R W W Code R [DR] R [SA] R [S] XXX F A FnUt o Address o write Out write R 8 R 8 R 8 Constant F A + Data In Write PC Write R 9 R 9 R 9 F A + R R R Unused R R R Unused R 2 R 2 R 2 F A + + R 3 R 3 R 3 F A R 4 R 4 R 4 Unused R 5 R 5 R 5 F A ^ F A v F A + F A F F sr F sl Unused 3 4 Encoding for Sequencing Control S PS IL e xt State Action Code Action Code Gives next state of Control State Hold PC o load Inc PC Load instr. ranch J ump AS Charts for Sequential Control An instruction requires two steps: fetch obtaining an instruction from memory execution the execution of a sequence of microoperations to perform instruction processing Due to the use of the IR, these two steps require a minimum of two clock cycles ISA: Specifications and AS charts for the instructions (that all require two clock cycles) A vector decision box is used for the opcode Scalar decision boxes are used for the status bits 5 6 ISA: Specifications (for reference) AS Chart for Two-Cycle s - Part P C P C + I F I R [ P C ] E X I n st ruction Speci fications for the Simple Comput er - Part Instr u ctio n O pc ode nem on ic Form a t D escrip tion St a t u s its ove A O V A RD,RA R [DR] R[SA ], Increment IC R D, RA R[DR] R [ SA] +, Add ADD R D, RA,R R [DR] R[SA ] + R[ S], Subtr a ct SU R D, RA,R R [DR] R[SA ] - R [ S], D e crement DEC R D, RA R[DR] R[SA ] -, AD AD R D, RA,R R [DR] R[SA ] R[S ], O R OR RD,RA,R R[DR] R[SA ] R[S ], Exclusive OR XOR R D, RA,R R [DR] R[SA ] R[S], O T O T R D, RA R[DR] R[SA ], + R [ S ] R [ D R ] R [ v R [ S A ] S ] + R [ D R ] + R [ R [ S ] S A ] + R [ D R ] R [ R [ S A ] S ] R [ D R ] R [ R [ S A ] + S ] 7 8 3

4 ISA: Specifications (for reference) I n st ruction Speci fications for the Simple Comput er - Part 2 Instr u ctio n O pc ode nem on ic Form a t D escrip tion ove O V RD,R R [DR] R[S] Shift Right SHR R D, R R[DR] sr R[S] Shift Left SHL R D, R R[DR] sl R[S] Load Imm e diate LDI R D, O P R[DR] zf OP Add Immediate ADI R D, RA,OP R [DR] R[SA] + zf OP Load LD RD,RA R [DR] [ SA ] Store ST RA,R [SA] R[S] ranch on ero R R A,AD if (R[ S A] = ) PC PC + s e A D ranch on egative R R A,AD if (R[ S A] < ) PC PC + s e A D J u mp JP R A P C R[SA ] St a t u s its 9 AS Chart for 2-Cycle s - Part 2 Portion in Red duplicated from previous AS chart I F IR [PC] E X P C P C + R [ D R ] [ R [ S A ] ] R [ D R ] zf OP R [ D R ] R [ S ] [ R [ S A ] ] R [ S ] + zf OP PC PC + se AD PC R [ S A ] To IF 2 Chapter Part 2 State Table for 2-Cycle s 3-Process AS VHDL Code I n p u t s O u t p u t s e x t S t a t e s t a t e I P R V C L S D X A X X F S D W W C o m m e n t s I F X X X X X X EX X X X X X X X X X X I R [ PC ] E X X X IF X X X X X X X X O V A R [DR] R [SA]* E X X X IF X X X X X X X X I C R [DR] R [S A ] + * E X X X IF X X X X X X X A D D R [DR] R [S A ] + R [S ]* E X X X IF X X X X X X X S U R [DR} R [S A ] + R [ S ] + * E X X X IF X X X X X X X X D E C R [DR] R [S A ] + (- ) * E X X X IF X X X X X X X A D R [DR] R [SA] ^ R [S ]* E X X X IF X X X X X X X O R R [DR] R [SA] v R [S ]* E X X X IF X X X X X X X X O R R [DR] R [SA] + R [S ]* E X X X IF X X X X X X X X O T R [DR] R [ S A ] * E X X X IF X X X X X X X O V R [DR] R [S ]* E X X X IF X X X X X X X X X L D R [DR] [ R [SA]]* E X X X IF X X X X X X X X X S T [ R [SA]] R [S ]* E X X X IF X X X X X X LDI R [DR] z f OP * E X X X IF X X X X X X ADI R [DR] R [S A ] + z f OP * E X X X I F X X X X X X X X R PC PC + s e A D E X X X I F X X X X X X X X R PC PC + E X X X IF X X X X X X X X R PC PC + s e A D E X X X IF X X X X X X X X R PC PC + E X X X IF X X X X X X X X J P PC R [S A ] * For this state and input combinations, PC PC+ also occurs 2 entity controller is Port ( opcode : in std_logic_vector(6 downto ); reset, clk : in std_logic; zero, negative : in std_logic; IL,, D,, RW, W : out std_logic; PS : out std_logic_vector( downto ); DX, AX, X, FS : out std_logic_vector(3 downto ); ); end controller; architecture ehavioral of controller is type state_type is (RES, FTH, EX); signal cur_state, next_state : state_type; state_register:process(clk, reset) if(reset='') then cur_state<=res; elsif (clk'event and clk='') then cur_state<=next_state; end if; end process; 22 3-Process AS VHDL Code AS Chart for ultiple its Right Shift EX out_func: process (cur_state, opcode, zero, negative) (IL,PS,, FS, D, RW, W, ) <= std_logic_vector'(x""); FS<=""; case cur_state is when RES => next_state <= FTH; when FTH => -- set the control vector values next_state <= EXE; when EXE => case opcde is: when +> R8 used to perform shifts R9 used to store and decrement shift count ero test in EX is to determine if the shift amount is ; if so, goes to state IF EX2 R8 R[SA] EX R9 zf OP R8 sr R8 EX3 R9 R9 - end process; EX4 End ehavioral; PC PC + R[DR] R8 23 To IF 24 4

5 State Table For ultiple its Right Shift S t a t e I n p u t s V C O u t p u t s e x t s t a t e I L P S D X A X X F S D R W W C o m m e n t s EX X X E X X X X X X X S R R 8 R [S A ], : EX EX X X I F X X X X X X S R R 8 R [S A ], : I F * EX X X E X 2 X X X X X S R R 9 z f OP, : EX2 EX X X I F X X X X X S R R 9 z f OP, : I F * EX2 X X X EX3 X X X S R R 8 s r R 8, EX3 EX3 X X E X2 X X X X S R R 9 R 9 -, : E X 2 EX3 X X E X4 X X X X S R R 9 R 9 -, : E X 4 EX4 X X IF X X X X X X S R R [D R ] R 8, I F * * For this state and input combinations, PC PC+ also occurs 25 5