ENEE 359a Digital VLSI Design

Transcription

1 SLIDE 1 ENEE 359a Digital VLSI Design Course : Transistors to Systems Prof. blj@eng.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay s CSE477 slides (PSU), Schmit & Strojwas s slides (CMU), Wolf s slides for Modern VLSI Design, and/or Rabaey s slides (UCB).

2 SLIDE 2 Why Digital? Assume noise in your electronics (lights flicker for no apparent reason, speakers pop when refrigerator turns on, cable station comes in fuzzy, etc.) and you want to eliminate/reduce problem f() g() h() h(g(31.4)) not h(g(29.6)) Noise turns 29.6 into 31.4 g(31.4) further noise? Analog: noise-induced errors propagate and accumulate (e.g., further noise?); hard to distinguish noisy signal from true signal

3 SLIDE 3 Why Digital? How would YOU solve the problem? f() g() h() INTERPRET INTERPRET RANGE OF OUTPUT PRODUCED RANGE OF OUTPUT PRODUCED () g() h( NOISE VALID VALUES VALID VALUES Problem arises because the entire range of output values is fair game as input Thus, it is hard to distinguish corrupted or noisy signal from true signal

4 SLIDE 4 Why Digital? How would YOU solve the problem? f() g() h() INTERPRET INTERPRET RANGE OF OUTPUT PRODUCED RANGE OF OUTPUT PRODUCED () g() h( NOISE VALID VALUES VALID VALUES ECC-protect all transmissions? (can t, literally, but can do an analogy ) Use a smaller valid-data range so that small errors don t matter

5 SLIDE 5 Why Digital? How would YOU solve the problem? f() g() h() INVALID DATA VALID DATUM () RANGE OF OUTPUT PRODUCED INTERPRET g() INVALID DATA each value gravitates to nearest valid datum VALID DATUM NOISE VALID VALUES INVALID DATA ECC does this numerically; here, we re talking about interpreting voltage levels Relatively straight-forward to do this with various types of amplifiers

6 SLIDE 6 Why Digital? Take this to the extreme: ENTIRE RANGE OF POSSIBLE*** VALUES (voltages) 1 TWO VALID VALUES 0 GRAVITATE to 1 GRAVITATE to 0 BINARY (two values) Very robust in the face of noise Well-suited to BOOLEAN LOGIC *** Dramatic oversimplification

7 SLIDE 7 Why Is This Robust? OUT OUT 1 1 g(x) = x 0 IN g(x) = x 0 IN These curves are said to be regenerative Noise neither propagates nor accumulates This is exactly what digital logic does, e.g. chain of inverters: Noise on wire changes this: Output: to this:

8 How Is It Done? (devices) SLIDE 8??? Implementation: Transistors (switches) Inverter Function: Do I connect my output to 1 or 0? Each is effectively a signal repeater

9 How Is It Done? (devices) MOS Transistors: Gate Gate SLIDE 9 Source Drain Source Drain n channel n VSS p channel p VDD p-doped semiconductor substrate NMOS Gate n-doped semiconductor substrate PMOS Gate Source Drain Source Drain Substrate Substrate What s a C MOS?

10 How Is It Done? (devices) MOS Transistor: SLIDE 10 PN Junction N-Doped Region [donor electrons] n p-doped semiconductor substrate

11 How Is It Done? (devices) MOS Transistor: SLIDE 11 VDD P-Doped Region [acceptor holes] VDD N-Doped Regions [donor electrons] n n VSS p-doped semiconductor substrate

12 How Is It Done? (devices) MOS Transistor: SLIDE 12 VDD Insulator (gate oxide) VDD n n VSS p-doped semiconductor substrate

13 SLIDE 13 How Is It Done? (devices) NMOS Transistor with gate: Conductor Insulator (gate oxide) n n 0 p-doped semiconductor substrate

14 SLIDE 14 How Is It Done? (devices) NMOS Transistor with bias voltages: Conductor Insulator (gate oxide) n n 0 p-doped semiconductor substrate

15 SLIDE 15 How Is It Done? (devices) NMOS Transistor with bias voltages: Conductor Insulator (gate oxide) n CURRENT n 0 p-doped semiconductor substrate

16 SLIDE 16 How Is It Done? (devices) NMOS Transistor with bias voltages: Gate Source Drain n channel n VSS p-doped semiconductor substrate Gate Gate Source 0 0 (Vss) Drain V > 0 Source 0 V > 0 (Vss) Drain V > 0 Electron Flow

17 SLIDE 17 How Is It Done? (devices) PMOS Transistor with bias voltages: Gate Drain Source p channel p VDD n-doped semiconductor substrate Drain Gate 0 VDD Source V > 0 (Vdd) Drain Gate 0 V<VDD Source V > 0 (Vdd) Electron Flow

18 How Is It Done? (devices) MOS Transistors: Gate Gate SLIDE 18 Source Drain Drain Source n channel n VSS p channel p VDD p-doped semiconductor substrate NMOS Gate n-doped semiconductor substrate PMOS Gate Source Drain Drain Source Substrate Substrate CMOS Inverter = one of each

19 How Is It Done? (devices) MOS Transistors: Gate Gate SLIDE 19 Source Drain Drain Source n channel n VSS p channel p VDD p-doped semiconductor substrate NMOS Gate Input n-doped semiconductor substrate PMOS Gate Source Drain Drain Source Substrate Output Substrate CMOS Inverter = one of each

20 SLIDE 20 How? (manufacturing) Wafer (up to 30cm) Individual die Wafer is a thin slice off a silicon log; Each wafer produces many identical chips

21 SLIDE 21 How? (manufacturing) Si-substrate Silicon base material Si-substrate Photoresist SiO 2 Si-substrate Chemical or plasma etch Hardened resist SiO 2 4. After development and etching of resist, chemical or plasma etch of SiO 2 1&2. After oxidation and deposition of negative photoresist Si-substrate UV-light Patterned optical mask Exposed resist Si-substrate 5. After etching Si-substrate Hardened resist SiO 2 SiO 2 3. Stepper exposure 8. Final result after removal of resist

22 SLIDE 22 How? (manufacturing) 1. Create thin oxide in the active regions, thick elsewhere 2. Deposit polysilicon 3. Etch thin oxide from active region (poly acts as a mask for the diffusion) 4. Implant dopant

23 How? (manufacturing) CMOS Inverter Cut line SLIDE 23 N-Well

24 How? (manufacturing) SLIDE 24 N-regions for source, drain Gate (poly) P-regions and gate for NMOS device N-Well ( n-well process ) P-type wafer CMOS Inverter N-Well Cut line

25 How? (manufacturing) SLIDE 25 N-regions for source, drain Gate (poly) input P-regions and gate for PMOS device GND NMOS output PMOS VDD N-Well Cut line

26 How? (manufacturing) SLIDE 26 + VDD a tub ties out transistors a out GND Another view (note: wells/tubs not shown)

27 SLIDE 27 How Is It Done? (logic) CMOS Inverter VDD ( 1 ) VDD ( 1 ) s=0 p s=1 p out = VDD ( 1 ) out = GND ( 0 ) s=0 n s=1 n GND ( 0 ) VDD GND ( 0 ) in out s s

28 How Is It Done? (logic) SLIDE 28 CMOS NAND-gate VDD VDD VDD s1 pmos s2 pmos A B output output s1 nmos A B s2 nmos GND s2 s

29 How Is It Done? (logic) SLIDE 29 CMOS NOR-gate VDD s2 s VDD s2 pmos B s1 pmos A output s1 nmos s2 nmos output A B GND GND

30 How Is It Done? (logic) SLIDE 30 CMOS AND--gate? VDD s2 s VDD s2 nmos B s1 nmos A output s1 pmos s2 pmos output A B GND GND TEMPTING, BUT BAD IDEA (why?)

31 SLIDE 31 How Is It Done? (design) Divide & Conquer: Modular, hierarchical design Well-defined interfaces Multiple levels of abstraction EXTENSIVE use of CAD tools Back-end integration Increasing clock rates, increasing densities, increasing design complexity, 1000s of I/O, decreasing design times

32 SLIDE 32 How Is It Done? (design) Big change in industry, late 1970 s: Mead & Conway introduced design rules Previous to this, all IC work was by hand, and integration of components was at the chip level (CPU = tons of connected chips) Design rules enabled CAD tools Popular (and powerful) tools today: Cadence tools (behavioral-to-layout) Synopsys tools (synthesis) HSPICE (circuit simulation)

33 SLIDE 33 How? (tools: verilog) The Many Faces of NOT (inverter) VDD Structural Verilog: wire s; wire sbar; NOT not1(s, sbar); in out Behavioral Verilog: wire s, sbar; sbar = ~s; s s

34 SLIDE 34 How? (tools: verilog) The Many Faces of NAND A VDD B Structural Verilog: wire a, b; wire out; NAND nand1(a, b, out); A B output Behavioral Verilog: wire a, b, out; out = ~(a & b); A B output

35 SLIDE 35 How? (tools: synopsys) Logic synthesis: Behavioral -> Structural wire a, b, out; out = ~(a & b); Logic Synthesis VDD wire a, b; A wire out; B NAND nand1(a, b, out); out A A B B output Library Instantiation VDD + out b a out tub ties b GND a

36 SLIDE 36 How? (tools: synopsys) Logic synthesis: Behavioral -> Structural wire a, b, c, out; out = ~((a & b) c); Logic Synthesis wire a,b,c,out; wire t1,t2; AND and1(a,b,t1); OR or1(c,t1,t2); NOT not1(t2,out); out = [ab+c] : symbol invert or circuit and Library Instantiation LAYOUT

37 SLIDE 37 How? (tools: synopsys) The tool will provide design options wire a, b, out; out = a + b; Four Adders: Ripple Brent-Kung Carry- Lookahead Fast Carry- Lookahead

38 SLIDE 38 How? (tools: HSPICE) CLK Din Q D1 D2 Very accurate simulation of circuits

39 How? (tools: cadence) SLIDE 39 full custom, die photo semi-custom, die photo fully synthesized, layout mostly custom, layout

40 SLIDE 40 How Is It Done? (design flow) Begin with a Behavioral Description: module testcounter(clk2, rst_l, out_w); input clk2, rst_l; output[7:0] out_w; reg [7:0] src1, out; wire [7:0] out_w = out; clk2) begin if(!rst_l) begin src1 <= 1'd0; out <= 1'd1; end else begin src1 <= out_w; out <= src1 + out_w; end end endmodule

41 How Is It Done? (design flow) Logic synthesis produces gate-level netlist: SLIDE 41

42 SLIDE 42 How Is It Done? (design flow) Instantiation of physical design libraries & place+route yields Physical Layout: (two views shown: one with black boxes for high-level structures like flip-flops/adders/muxes, the other showing all transistors and wires)

43 How Is It Done? (design flow) Send to fabrication facility, receive Chip: SLIDE 43 testcounter

44 SLIDE 44 How Is It Done? (system) f() g() h() Next input not until h() completes Simplest possible system-building scheme: Sequential Do One Thing At a Time Advantages: Simple, predictable, easy to debug Disadvantages: Slow, wastes hardware (g & h blocks idle while f computes, f & h blocks idle while g computes, etc.)

45 SLIDE 45 How Is It Done? (system) f() g() h() Next input not until h() completes VERSUS f() g() h() Next input as soon as f() completes Called a PIPELINE: extremely common Hardware used as fully as possible Throughput increases n-fold (n blocks) Question: How to control this?

46 SLIDE 46 How Is It Done? (system) f() g() h() Next input not until h() completes VERSUS f() g() h() Next input as soon as f() completes Control: Think traffic in a city (stop lights) f() g() h() Next input as soon as f() completes Clock synchronizes movement of data

47 SLIDE 47 What Are The Gotcha s? High-speed digital design, in contrast to digital design at low speeds, emphasizes the behavior of passive circuit elements. These passive elements may include the wires, circuit boards, and integrated-circuit packages that make up a digital product. At low speeds, passive circuit elements are just part of a product s packaging. At higher speeds the directly affect electrical performance. opening par. of Johnson & Graham, High-Speed Digital Design The bottom line: At high speeds, digital systems (which diverged from analog: simpler, remember?) start to behave just like analog systems.

48 SLIDE 48 What Are The Gotcha s? HIGH-SPEED DESIGN exposes problems: Even small amounts of NOISE Even small amounts of DELAY Even small amounts of CURRENT can cause a circuit to misbehave. At high speeds, signal levels are small (small noise levels become significant) At high speeds, event timing is tight (small errors in time become significant) At high speeds, current changes quickly (even if di is small, Ldi/dt can be large)

49 Gotcha s? (noise) Typical noise sources: SLIDE 49 Inductive coupling Capacitive coupling VDD VDD VDD Groundplane noise Implicit/explicit circuits (current return) make great radiators and antennae

50 SLIDE 50 Gotcha s? (delay) Though we like to imagine that it is, signal propagation is not instantaneous Clk SRC

51 Gotcha s? (delay) Argument for source-synchronous clocking: SLIDE 51 CLOCK NET 20ps 40ps 60ps 80ps A B C D DATA BUS if CLK is used to sample data*, this adds 0.14ns to uncertainty (*def n: tell A when to look at data bus) CLOCK NET 20ps A 160ps B C logic delay 20ps D DATA BUS 140ps 120ps drive t=100ps

52 SLIDE 52 Gotcha s? (current) Ideal Scenario vs. Reality (ground bounce): VDD Current flow changes direction when input (thus output) values change VDD L ( 0) IDEAL Magnitude of current change is di The time to switch directions is dt The voltage-drop induced on this wire at time of switching is L di/dt L ( 0) REALISTIC

53 Gotcha s? (current) Simultaneous Switching Noise: FCRAM side VDDQ(Pad) SLIDE 53 DQS (Pin) DQ0-15 (Pin) VSSQ(Pad) Controller side DQS (Pin) DQ0-15 (Pin) skew=158psec skew=102psec

54 SLIDE 54 What Are Some Solutions? IN GENERAL: Prevent the Problem Design as if the problem doesn t exist (continue using same old techniques as you did with low-speed designs) Use mechanism to counteract problem Design Around the Problem Re-think the way you design systems: assume the problem happens; ensure that it doesn t affect design (design makes no assumptions re: problem) Don t need to counteract problem

55 SLIDE 55 What Are Some Solutions? One solution to delay problem: heroic routing Path #2 Controller Path #1 A Path #3 B Bus Signal 2 Bus Signal 1 Intermodule Connectors

56 What Are Some Solutions? Another solution to the delay problem SLIDE 56 Sliding Time 0 th N th Clk SRC H Tree 0 th N th Clk SRC

57 What Are Some Solutions? (clock trees work, but may be better sol ns?) SLIDE 57

58 What Are Some Solutions? One solution to noise problem (shielding): SLIDE 58

59 What Are Some Solutions? Another solution to the noise problem: SLIDE 59 Single Ended Transmission Line Differential Pair Transmission Line

60 What Are Some Solutions? (differential signaling works quite well) SLIDE 60

61 What Are Some Solutions? Another type of shielding: SLIDE 61 Couples extremely well with previous sol n (less effective if used for single-ended transmission)

62 SLIDE 62 What Are Some Solutions? IN GENERAL: Prevent the Problem Requires no change in design practice; no learning curve, no increase in NRE design costs The mechanism might be expensive or skittish, or both Design Around the Problem Requires engineering creativity, willingness to be unconventional First attempt might not succeed Cost/reliability might be better (long run)

63 SLIDE 63 Historical Digital design has been an enormously successful paradigm, driven largely by the ability to use CAD tools to verify designs Result: exponential increases in design complexity that were predicted in 1965* and have continued for FOUR DECADES # transistors integrated circuit invented memory CPU year * Moore s Law. 1965: transistors on chip doubles every year. Revised in 1975: number of transistors doubles every two years.

64 Historical Intel 4004 SLIDE transistors 800 KHz operation

65 Historical Intel 8086 SLIDE K trans. 10 MHz

66 Historical Intel SLIDE K trans. 12 MHz

67 Historical Intel SLIDE /89 275K trans. 16/33 MHz

68 Historical Intel SLIDE M trans. 100 MHz

69 Historical Intel Pentium SLIDE /99 3.1/4.5M trans. 60/300 MHz

70 Historical Intel Pentium Pro SLIDE 70

71 Historical Intel Pentium IV SLIDE /04 42/178M trans. 1.4/3.6 GHz

72 SLIDE 72 Big Picture Digital vs. Analog: simple vs. complex robust vs. fragile BUT: This is Only True at Low Speeds (And Nothing is Low-Speed Any More) Analogy of Architect and the Carpenter: Architect does a better job if he knows carpentry Digital systems design can t be done without using analog concepts