SH-MobileG1: A Single-Chip Application and Dual-mode Baseband Processor

Transcription

1 SH-MobileG1: A Single-Chip Application and Dual-mode Baseband Processor Masayuki Ito 1, Takahiro Irita 1, Eiji Yamamoto 1, Kunihiko Nishiyama 1, Takao Koike 1, Yoshihiko Tsuchihashi 1, Hiroyuki Asano 1, Hiroshi Yagi 1, Saneaki Tamaki 1, Ken Tatezawa 1, Toshihiro Hattori 1, Shinichi Yoshioka 1, Koji Ohno 2 *. * : Currently with Renesas Technology 1 Renesas Technology 2 NTT DoCoMo 1

2 Overview Outline SH-MobileG1 Architecture - 3 CPU Configuration - Communication Architecture - Interrupt Control - System Control - Power Control and Leakage Current Summary 2

3 3G Multi-Media Cellular Phone System HPA High Power Amplifier RFIC Radio Frequency IC Baseband Processor Application Processor Multi-Media Accelerator Previous System HPA High Power Amplifier RFIC Radio Frequency IC One Chip SH-MobileG1 New System Using G1 3

4 A Sample of System Architecture using G1 Video M/W Camera M/W Camera Application Audio M/W Realtime OS (ITRON, etc.) Mail Application File System Video Phone Browser Application Application API JAVA Device Driver General Purpose OS (Symbian, Linux, etc.) Telephone Application GSM/WCDMA Protocol Stack Realtime OS (ITRON, etc.) Application-Realtime domain AP-RT CPU (SH) SuperHyway Bus Multi-Media Accelalators SDRAM Bridge Application-System domain APSYS CPU(ARM) SuperHyway Bus System Peripherals Bridge Baseband domain BB-CPU (ARM) W-CDMA IP GSM/GPRS IP SDRAM 4

5 Motivation for One Chip Integration - Chip-set cost will be down W-CDMA CPG DDR Sound - Mount area will be decreased by sharing common peripherals AP-Misc AP-SYS CPU - Performance will be up by wide data throughput BB- 3D G MPEG Misc JPEG inter-domain Camera signals BB- CPU LCDCMedia APL-RT RAM GSM CPU SRAM - Dynamic power will be saved by low-load - Static power will be saved by leakage current shut-off for unused domain 5

6 Chip Overview CPG DDR Sound Die size 11.15mm x 11.15mm W-CDMA AP-Misc AP-SYS CPU BB- 3D G MPEG Misc JPEG Camera BB- CPU LCDCMedia APL-RT RAM GSM CPU SRAM Process Supply voltage # of TRs, gate, memory 90nm LP 8M(7Cu+1Al) CMOS dual-vth 1.2V(internal), 1.8/2.5/3.3V(I/O) 181M TRs, 13.5M Gate 20.2 Mbit mem 6

7 G1 Module Diagram AHB Bus BB Core Block I- D- Cache Cache DMAC INTRAM CPU MMU AP-SYS Block CPU I- D- Cache Cache MMU APB Bus WCDMA Block MODEM DSP Peripherals BB Main Bus BBSC GSM Block DSP MODEM Peripherals SYSC WUC AP-RT Block DSP CPG BB CPU XYRAM I- D- Cache Cache URAM MMU INTC BB Media Bus LCDC VIO VPU JPU ABB LCD Camera APBB SuperHyway (SYS) S2S SuperHyway (RT) INTC SYS MFI CPG AP HP Bus (SYS) DMAC Peripherals (SYS) BSC SBSC 3DG DMAC Peripherals (RT) HP Bus (RT) INTC RT MFI 7

8 AP-Realtime Domain Configuration SHX2 runs on RT-OS - 2-way superscalar up to 312MHz - 32KB-I$ and 32KB-D$ - 512KB onchipram Media IPs - VPU encodes MPEG4 and H VIO handles up to 5M pixel camera. - 3D graphic accelerator S2S S2S: SBSC: LCDC: VIO: VPU: AP-RT Block (SHX2) DSP CPU XYRAM I- D- Cache Cache URAM MMU SBSC SDRAM (AP) JPU: 3DG: INTC: MFI: SuperHyway (RT) 3DG DMAC Peripherals (RT) Media Bus HP Bus (RT) LCDC VIO VPU JPU INTC RT MFI SHwy-SHwy bridge SDR/DDR-SDRAM Controller LCD Controller Camera I/F with Image- Processing Engine Video Processing Unit (MPEG-4 Accelerator) JPEG Codec Unit 3D Graphics Accelerator Interrupt Controller Multi-Functional Interface 8

9 AP-System Domain Configuration ARM926EJ-S runs on general-purpose OS - Up to 208MHz - 32KB-I$ and 16KB-D$ Peripherals - Sound handling - SDcard, IIC - Flash Control -USB - BB communication serial APBB INTC SYS MFI CPG AP S2S: APBB: BSC:: CPG: INTC: MFI: AP-SYS Block SuperHyway (SYS) HP Bus (SYS) CPU I- D- Cache Cache MMU DMAC Peripherals (SYS) BSC SRAM/ FLASH S2S SHwy-SHwy bridge AP-BB bridge SRAM/FLASH Controller Clock Pulse Generator Interrupt Controller Multi-Functional Interface 9

10 Baseband Domain Configuration ARM926EJ-S runs on RT-OS - Up to 104MHz - 16KB-I$ and 4KB-D$ with TCM W-CDMA and GSM/GPRS - DSP accelerates the modem protocol handling - One can be cut-off where only the other is available - Only small logic is awake for tracing the timing of each radio AHB Bus BB Core Block APBB CPU I- D- Cache Cache DMAC RAM APBB: BBSC: CPG: INTC: MMU INTC CPG BB BB APB Bus BB Main Bus WCDMA Block DSP MODEM Peripherals GSM Block DSP MODEM Peripherals BBSC SDRAM (BB) AP-BB bridge Baseband Bus Controller Clock Pulse Generator Interrupt Controller 10

11 Communication Architecture - G1 keeps the communication paths (MFI and Serials) used in the previous system for software reuse APBB S2S 11

12 Communication Architecture (Cont d) - AP-SYS and AP-RT share SDRAM and memory map - AP and BB have different SDRAM and memory map - APBB bridge supports access window scheme to access the resource in the other memory map Flash BB SDRAM AP Access Window Using AP-BB bridge BB Periphral Regs Flash SYS Periphral Regs AP SDRAM BB Access Window Using AP-BB bridge RT Periphral Regs 12

13 Interrupt Control - Each CPU has its INT controller - MFI can generate inter-domain interruptions - Some external pins generate interrupts for each CPU 13

14 System Control Reset Clock Reset Clock Reset Clock S:Semaphore Register P:Power Down Register W:Wake-up Register B: Boot Control Register Boot Address S P W B S P W B S P W B Control Power Control PLLs Reset Semaphore Free:00 RT:01 SYS:10 BB:11 Boot Address PLLs Reset Control Boot Control (Master CPU, Boot Address for each CPU) Boot Address Boot Mode RESET WakeUp 14

15 System Control (Cont d) Boot Control - One CPG master CPU DDRdefined by pin settings boots first and Sound specifies the other CPUs boot addresses W-CDMA- Various boot AP-Misc modes are AP-SYS supported for system configurability and debuggability CPU (1) BB Master External Memory Boot (2) BB Master Internal ROM Boot BB- MPEG (3) BB-Alone Misc Mode (for Test) JPEG Camera BB- CPU LCDCMedia (6) AP-RT Master Boot (7) AP-Alone APL-RT Mode (for Test) RAM GSM CPU SRAM (4) AP-SYS Master External Memory Boot (5) AP-SYS Master Internal ROM Boot 15

16 System Control (Cont d) Power Control - Each CPG CPU can DDR read and write SYSC registers from each Sound domain, which are reflected into the common SYSC W-CDMA - Power up/down AP-Misc can be AP-SYS controlled by each CPU that gets the semaphore CPU Clock Control BB- 3D G MPEG - AP Misc and BB have separate JPEGClock Pulse Generator - Many Camera BB- variations of clock configuration and gear changes are CPU supported for LCDC dynamic Media power reduction APL-RT RAM - Clock for some IPs GSM CPU SRAM remains the fixed frequency 16

17 Power Domain 20 hierarchical domains for partial power-off Application part Baseband part C5 (System controller, PAD controller) C4 (Repeaters, CK buffers, BKUP FFs) A4U1 A4U2 A4 LCDC VRAM Reg Mem Control. RAM, DMA PLL for Application part Mobile Video Interface Mem control. Serial I/Os A1A SYS-CPU AC A3 A2 A1R RT-CPU PLL for Baseband part BA3 BB-CPU WCDMA BA2 BW3 BW2 GSM DFT WCDMA GSM BW1 WCDMA BA4 BC BG3 BG2 BG1 GSM 17

18 Power Domain (Cont d) Chip Floorplan Power Domains W-CDMA AP-Misc Sound AP-SYS CPU BW2 BC BA2 AC A2 C5 A4 A1A GSM GSM BB- CPU BB- Misc MPEG 3DG APL-RTJPEG Camera CPU Media SRAM RAM APL-RT CPU BW1 BW3 BA4 BA3 BG1 BG3 BG2 C4 A1R A4U2 A4U1 A3 18

19 Implementation Results of Power Domains # of Power domains # of Islands for C4 (Repeaters,CK buffers, BKUP FFs) # of Repeaters in C4 domain # of Clock buffers in C4 domain # of Backup FFs in C4 domain # of mios (isolation cell) Total area of power switch 20 domains 19 islands 3100 cells 1600 cells 2300 cells cells 4.2 mm 2 19

20 Leakage Current in Usage Scenes (1) Video telephony BW2 BW3 BC BA2 BA4 AC A2 C4 C5 A4 A1A Baseband part Control W-CDMA GSM ON ON ON / OFF BW1 BG1 BA3 BG2BG3 A1R A4U2 A4U1 A3 Application part System-domain Realtime-domain ON ON Power on Power off Measured Leakage Current (@ Room Temp, 1.2V) 849 µa 20

21 Leakage Current in Usage Scenes (2)Telephony (W-CDMA) BW2 BW3 BC AC BA2 BA4 A2 C4 C5 A4 A1A Baseband part Control W-CDMA GSM ON ON ON / OFF BW1 BG1 BA3 BG2BG3 A1R A4U2 A4U1 A3 Application part System-domain Realtime-domain ON OFF Power on Power off Measured Leakage Current (@ Room Temp, 1.2V) 407 µa 21

22 Leakage Current in Usage Scenes (3)Waiting for Calling BW2 BW3 BC BA2 BA4 AC A2 C4 C5 A4 A1A Baseband part Control W-CDMA GSM ON OFF * OFF BW1 BG1 BA3 BG2BG3 A1R A4U2 A4U1 A3 Application part System-domain Realtime-domain OFF OFF Power on Power off Measured Leakage Current (@ Room Temp, 1.2V) *: Intermittent Operation 299 µa 22

23 Leakage Current in Usage Scenes (4) Power off ( I/O fixed) BW2 BW3 BC AC BA2 BA4 A2 C4 C5 A4 A1A Baseband part Control W-CDMA GSM OFF OFF OFF BW1 BG1 BA3 BG2BG3 A1R A4U2 A4U1 A3 Application part System-domain Realtime-domain OFF OFF Power on Power off Measured Leakage Current (@ Room Temp, 1.2V) 7 µa 23

24 Summary We have developed SH-MobileG1 - Application and dual-baseband single-chip processor for 3G multimedia cellular phone system - Key features of its architecture have been presented - One chip integration contributes not only to dynamic but also to leakage current reduction by careful partial power-off control 24