Agenda: Day One 3-1 DAY. Welcome. Introduction to Static Timing Analysis. Writing Basic Tcl Constructs in PT. Constraining Internal Reg-Reg paths

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1 Agenda: Day One 3-1 DAY 1 Unit Register Register Paths Lab 0i Welcome 1 Introduction Static Timing Analysis 2 Writing Basic Tcl Constructs in PT 3 4 Constraining Internal Reg-Reg paths 3-1 Unit 3:

2 Unit Objectives 3-2 After completing this unit, you should be able : Use a 3 step flow read design(s) in PT memory Resolve errors and warnings associated with reading and linking a design Access design objects after a design has been read in PT memory 3-2 Unit 3:

3 The Inputs and Outputs of PrimeTime 3-3 Gate-Level Netlist Constraints Exceptions Setup File read_db read_verilog read_vhdl source source Technology Libraries Read at PT invocation Loaded at linking PrimeTime Reports Constraint Script Log File The PrimeTime setup file is.synopsys_pt.setup. Constraints and Exceptions are usually placed in script(s). 3-3 Unit 3:

4 Five Step Static Timing Analysis Flow 3-4 READ CONSTRAIN EXCEPTIONS CHECK ANALYZE Our Focus 3-4 Unit 3:

5 PRIMETIME Interfaces 3-5 Two ways interface PrimeTime (PT) primetime PT GUI Command line shell PRIMETIME (PT) Engine pt_shell Primetime only accepts Tcl mode. 3-5 Unit 3:

6 Three Steps Read Your Data in PT 3-6 Three steps read in the required design(s): Set Variables: search_path link_path Read Design Resolve References (Link design) 3-6 Unit 3:

7 1: Set the search_path Variable 3-7 Synonymous with UNIX path variable ProjectX/ tech_lib.db projectx.log db/ vlog/ Tom/ scripts/ blocka.db blockb.db blockc.db p.v blockd.v blocke.v uart.db p.pt proc1.pt proc2.pt set search_path $search_path db vlog scripts printvar search_path What is a search_path? search_path contains a list of paths used locate the designs, libraries and other files needed perform STA. search_path variable usually includes paths : Design Database(s) Timing Model(s) Technology Library Constraint files These two commands have the same effect: set search_path $search_path db vlog scripts. # lappend search_path db vlog scripts lappend search_path db vlog scripts The default value of search_path is empty string. 3-7 Unit 3:

8 1: Set the link_path variable 3-8 The Link Path specifies where PT searches for designs and library files when linking the design: set link_path {* tech_lib.db rams.db} Link Path PT Memory Technology Cusm = * Library Conditions IP Cores During linking, PT will search (in sequence) the: PT Memory (*) Library file tech_lib.db IP core rams.db printvar link_path link_library = link_path. Design Compiler uses link_library, PrimeTime uses link_path. These two commands are equivalent: set link_path {* core_slow.db rams.db} lappend link_path core_slow.db rams.db 3-8 Unit 3:

9 2: Manually Read Design(s) in PT 3-9 U33 p blocka U21 INV U4 blockb pt_shell> read_db p.db pt_shell> read_db blocka.db pt_shell> read_db blockb.db OR pt_shell> read_db blocka.db blockb.db p.db What is the current_design in each case? The last design read is the current design by default. You can make another design current with the current_design command. In the above example of 2 cases, the current designs are blockb and p respectively. 3-9 Unit 3:

10 2: Read Sub Designs Aumatically 3-10 ProjectX/ tech_lib.db projectx.log db/ vlog/ Tom/ scripts/ blocka.db blockb.db p.v blockd.v uart.db p.pt proc1.pt blockc.db blocke.v proc2.pt pt_shell> read_verilog p.v pt_shell> link_design TOP What should the search_path be? Top.v is in the vlog direcry, search_path should have this direcry. Designs blocka.db AND blockb.db are in the DB direcry; search_path should also have this direcry. set search_path./vlog./db 3-10 Unit 3:

11 2: Read Designs in Different Formats 3-11 U33 p blocka INV U21 U4 blockb pt_shell> read_verilog p.v pt_shell> read_db blocka.db pt_shell> read_vhd blockb.vhd Can you mix netlist formats? How does it work? 3-11 Unit 3:

12 Example 1: Read Problem 3-12 set search_path $search_path db vlog scripts set link_path * tech_lib.db ProjectX/ tech_lib.db projectx.log db/ vlog/ Tom/ scripts/ blocka.db blockb.db blockc.db p.v blockd.v blocke.v uart.db p.pt proc1.pt proc2.pt pt_shell> read_db uart.db Error! Error: Cannot read file uart.db Error: Problem in read_db: No designs were read. How would you fix this read problem? 3-12 Unit 3:

13 Example 2: Read Problem 3-13 set search_path $search_path db vlog scripts set link_path * tech_lib.db ProjectX/ tech_lib.db projectx.log db/ vlog/ Tom/ scripts/ blocka.db blockb.db p.v blockd.v uart.db p.pt proc1.pt blockc.db blocke.v proc2.pt pt_shell> pwd /../ISTA/ProjectX pt_shell> cd scripts pt_shell> read_db blocka.db Error: Cannot read file blocka.db Error! How would you fix this read problem? 3-13 Unit 3:

14 3: What is Resolving References? 3-14 What is INV? U33 BLOCKA RISC_CORE Where is BLOCKB? U21 INV U4 BLOCKB How will PrimeTime know what each instance in RISC_CORE design netlist refers? Resolving references (aka link) means finding and replacing the space holders with the actual library cells or sub designs referenced Unit 3:

15 3: Link the Design Resolve References 3-15 The link_design command: Resolves all references in a design using the link_path variable: If it fails, it will use the search_path variable resolve references Reads the technology library if not already read in What are blocka, blockb, and INV? U33 blocka p INV U21 U4 blockb link = link_design. Design Compiler (DC) uses link while PrimeTime (PT) uses link_design command link a design. For convenience, PT has built-in alias link for link_design. Q: What happens if you accidentally try link the same design that has been previously linked? A: If you originally used -remove_sub_designs then, black boxes will be resulted since sub design references could not be found in the memory (*). Solution: - Use the link -incr option (OR) - Remove the (corrupted) design in memory and start over from read again (Recommended) Unit 3:

16 Example: Linking a Design 3-16 set search_path $search_path db vlog scripts set link_path * tech_lib.db ProjectX/ tech_lib.db projectx.log db/ vlog/ Tom/ scripts/ blocka.db blockb.db p.v blockd.v uart.db p.pt proc1.pt blockc.db blocke.v proc2.pt p U33 blocka U21 INV U4 blockb pt_shell> read_db blocka.db blockb.db pt_shell> read_verilog p.v pt_shell> current_design p pt_shell> link_design Where are the references found during linking? PT found blocka.db and blockb.db in its memory and INV in the library. After linking, if current_design is set a different design, all the previously established link information will be gone. PT aumatically reads in Library file(s) when link_design is executed Unit 3:

17 Example: Link Warning 3-17 pt_shell> read_db CLOCK_GEN.db pt_shell> link_design pt_shell> link Linking Linking design design CLOCK_GEN... CLOCK_GEN... Warning: Warning: Unable Unable resolve resolve reference reference 'MUX21L' 'MUX21L' in in 'CLOCK_GEN'. 'CLOCK_GEN'. (LNK-005) (LNK-005) Warning: Warning: Unable Unable resolve resolve reference reference 'IVI' 'IVI' in in 'CLOCK_GEN'. 'CLOCK_GEN'. (LNK-005) (LNK-005) Warning: Warning: Unable Unable resolve resolve reference reference 'FD2' 'FD2' in in 'CLOCK_GEN'. 'CLOCK_GEN'. (LNK-005) (LNK-005) Creating Creating black black box box for for U31/MUX21L... U31/MUX21L... Creating Creating black black box box for for U32/MUX21L... U32/MUX21L... Creating Creating black black box box for for U34/IVI... U34/IVI... Creating Creating black black box box for for U35/IVI... U35/IVI... Creating Creating black black box box for for CLK_BY_2_reg/FD2... CLK_BY_2_reg/FD2... Designs Designs used used link link CLOCK_GEN: CLOCK_GEN: <None> <None> Libraries Libraries used used link link CLOCK_GEN: CLOCK_GEN: <None> <None> WHAT! Design Design 'CLOCK_GEN' 'CLOCK_GEN' was was successfully successfully linked. linked. 1 1 Verify link_path and search_path Primetime create black boxes for unresolved references. This is because the link_create_black_boxes variable is set true by default Unit 3:

18 Black Boxes with link_design 3-18 If link_design could not resolve a particular reference, PT will create black boxes A black box is an empty cell with no timing arcs The variable link_create_black_boxes is true by default: Substitute unresolved references with black boxes Design is linked and timing analysis can be performed Set the variable link_create_black_boxes false: Unresolved references, cause a design remain unlinked Most timing analysis commands will not function Fix any problems and re-link the design What command would you use set this variable false? set link_create_black_boxes false 3-18 Unit 3:

19 Test For Understanding 3-19 Name three design netlist formats that PrimeTime accept? Linking a design involves the use of: a) and b) variables What is the purpose of linking a design? What does * in the link_path mean? 3-19 Unit 3:

20 Do You need Set Variables Every Time? 3-20 Can you have search_path and link_path variables set aumatically when you invoke PT? 3-20 Unit 3:

21 Create a.synopsys_pt.setup File 3-21 set search_path $search_path db vlog scripts set link_path * tech_lib.db set sh_enable_page_mode true set sh_command_log_file projectx.log alias h hisry alias rc report_constraint -all_violars hisry keep 200 Within the setup file, you can: Create commands you want execute every time PrimeTime is invoked, i.e. set search_path or set link_path Define aliases for interactive use Change log file name from its default pt_shell_command.log hisry keep 200 specifies: the number of commands (200) be retained in the hisry list. By default, only 20 commands are retained. You can control the naming of the Log file (default: pt_shell_command.log) via the variable: sh_command_log_file, but, it should appear inside the setup file (.synopsys_pt.setup) Example: set sh_command_log_file./projectx.log. Do not source any script file in the setup file since it will increase invocation time and will make debugging difficult Unit 3:

22 PrimeTime Setup Files User s General Setup ~user $SYNOPSYS/admin/setup ~/.synopsys_pt.setup.synopsys_pt.setup 3 User s Specific Project Setup Project_Direcry 1 Standard Setup./.synopsys_pt.setup PrimeTime will read the.synopsys_pt.setup files from three direcries (in the following order): 1. The primetime root direcry, which contains the PrimeTime files. For example, if PrimeTime was installed under /ols/synopsys/pt, standard installation would include a setup file under /ols/synopsys/pt/admin/setup. 2. Once the standard setup file has been read in and executed, PrimeTime then searches for a setup file in the user s login direcry. If a setup file exists in this direcry, it will be read in and executed. -- Warning: During project archiving (using tar -cvf) you need think about it! 3. Last, PrimeTime will read in and execute the.synopsys_pt.setup file from the direcry under which it was invoked. -- It makes life easier if this project specific setup file contains everything including the contents of your home direcry setup file, if you have one -- recall the Warning above Unit 3:

23 Read/Link Problem Debug Check List 3-23 Is PT invoked in the correct direcry? Correct setup file? Is the design fully mapped gate level instances? No high level HDL constructs (such as if, case,...) Are search_path and link_path variables set correctly? printvar *_path Are Black Boxes created for unresolved references? set link_create_black_boxes false Check Libraries in Memory & Library used: list_libraries list_libraries -used There can be only one linked design in PT memory Q: What happens if you accidentally try link the same design that has been previously linked? A: If you originally used -remove_sub_designs, the result will be black boxes since sub design references could not be found in the memory (*). Solution: - Use the link -incr option (OR) - Remove the (corrupted) design in memory and start over from read again (Recommended) Unit 3:

24 How does PT Sre My Design Netlist? 3-24 Vocabulary of Design Objects Design Cell Net TOP Port A B C D Clock CLK U1 A AIN B Q0 BIN C D CIN Q1 DIN ENCODER CLK U2 BUS0 INV U3 BUS1 INV U4 INV0 D0 Q[1:0] INV1 D1 CLK REGFILE Pin OUT[1:0] Reference and Design Here are some commands access your design sred in PT memory: get_cells # Create a collection of cells get_clocks # Create a collection of clocks get_nets # Create a collection of nets get_pins # Create a collection of pins... all_clocks # Create a collection of all clocks in design all_inputs # Create a collection of all input ports in design all_outputs # Create a collection of all output ports in design all_registers # Create a collection of register cells or pins Unit 3:

25 What Information Is Found in the Library? 3-25 Units for time, capacitance, resistance List of library cells Cell Timing (propagation delay, setup, hold...) Operating conditions Wire load model Design rules (max_capacitance, max_fanout...) list_libraries report_lib LIB_NAME pt_shell> list_libraries Library Registry: * ssc_core_slow./core_slow.db::ssc_core_slow pt_shell> report_lib ssc_core_slow **************************************** Report : library Library: ssc_core_slow Version: **************************************** Time Unit : 1 ns Capacitance Unit : 1 pf Usually, library file is read in during link_design. You can also explicitly read in a library file using the read_db command: Example: read_db ssc_core_slow.db To remove all the designs and libraries from the memory: remove_design all remove_lib all NOTE: PT cannot remove a library if it is used by a design residing in memory Unit 3:

26 Lab Overview 3-26 LAB 45 min Given a set of design and library files, you will need successfully read them in PrimeTime memory and access the design objects You will set the search_path and link_path variables correctly such that you can read: A Top level Verilog/VHDL netlist and link using Verilog/VHDL sub blocks and the library A p level Verilog/VHDL netlist and link using DB sub blocks and the library A complete netlist in VHDL/Verilog/DB and library, link efficiently and access sevaral objects within the design 3-26 Unit 3:

27 Review 3-27 Write 3 variable names that are used read and link a design in PT: Write 3 command names that are used read and link a design in Verilog format in PT: 3-27 Unit 3:

Reading the Design into PT

Reading the Design into PT Learning Objectives Given a set of design and library files, you will read them into PrimeTime memory and access the design objects. After completing this lab, you should be