ASIC Development. ASIC Classes. What s an ASIC, Anyhow? ASIC Methodology. Abstract Representations 2/16/2018

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1 ASIC Development ECE 527: Application Specific Integrated Circuit Development Logic Synthesis and Analysis Objective is to produce a physical design. ASIC development is considered done when a layout file (GDSII* format, or maybe OASIS**) is produced. Fabrication (foundry work) remains to be done, not covered here. 1 *Graphic Data Systems II **Open Artwork System Interchange Standard 2 What s an ASIC, Anyhow? Application Specific Integrated Circuit Processors are generally NOT considered ASIC though design methodology is essentially identical. Processors (including DSP s) are multi-purpose devices. Pretty much all integrated circuits are developed using ASIC methodology. Many times more ASIC s are designed every year than GP Processors. ASIC Classes Custom Mask FPGA Full Custom Standard Cell Gate Array Structured Unstructured 3 4 ASIC Methodology Abstract Representations Whatever the target technology, the methodology is pretty much the same. Mostly it means pointing the synthesizer to the right library. Designer still must be cognizant of target technology performance parameters. No amount of synthesis tricks will make a 50 MHz design run at 200. Design Specification HDL code Schematic/netlist Floor plan Placed & Routed design Silicon More abstract Not abstract at all 5 6 1

2 Where Synthesis Fits In Idea Back of envelope sketch Functional Graphical or textual description Behavioral HDL and simulation language Register Transfer Architectural HDL Synthesis Gate-Level Netlist Physical Device HDL to Gates Circuit descriptions are written in HDL programming type constructs. Eventually we need a silicon circuit. Gate level is an intermediate format. Logic synthesizers transform HDL to a gate level netlist. This course uses Synopsys Design Compiler. Silicon 7 8 HDL Design Flow Design Specification HDL Coding Logic Synthesis Simulation Vectors HDL Simulation RTL Code Constraints Component Library Simulation Passed? No Design Compiler Yes Logic Synthesis 9 Netlist Reports 10 Logic Synthesis Design Flow Logic synthesis is 1. translation of HDL to internal data base format 2. logic optimization (redundancies, De Morgan, etc.) 3. gate mapping (technology specific)

3 Concept & Market Research Static Timing Analysis Detailed Routing Back to Salt Mine Passed? Design Specification No Timing OK? Post-layout STA Yes Tapeout RTL Coding & Simulation Logic Synthesis Scan Insertion Yes Floorplanning, CT Insertion, Global P&R Static Timing Analysis Go to P&R 13 Back to Salt Mine Timing OK? Yes Design Rule Check Collect Bonus, Vacation 14 Design Compiler Flow Write RTL code and simulate Create start-up file Create constraints file Select appropriate compile flow Load designs and libraries Apply design constraints Synthesize the design Constraints Circuits usually have performance goals Area Speed Power Synthesizer produces different circuits depending on the constraints Write out design data Area vs. Operating Frequency Synopsys Propaganda Curve One HDL encoding can produce many designs through logic synthesis. Image John Cooley The Great ESDA Shootout

4 More Realistic Curve Combinational Logic Optimization Sequential Cell Optimization Synthesis The synthesizer can take advantage of complex flipflops to reduce glue logic. The optimization moves are technologydependent. The synthesizer can only use cells that are in the target library. 21 Depending on the size and complexity of the RTL, logic synthesis may be a quick procedure on a single file or an iterative process with many files. Synthesis is multi-level logic optimization (think K-maps, De Morgan, etc. but way more sophisticated) and technology mapping (picking the right components). 22 What s Wrong? One Unsigned, All Unsigned module incrementer_with_overflow( input logic CLK, RST, input logic signed [7:0] IN, output logic signed [8:0] OUT); CLK or negedge RST) if (!RST) OUT <= 0; else OUT <= IN + 1 b1; endmodule 23 All the variables were correctly declared as signed. But the increment value was not. 1 b1 is an unsigned number. So the result is unsigned. Simulation proof: if IN = -5, result is stored as 2 s compliment, which is 251 unsigned

5 Weirder Still So make the increment value 1 sb1. Looks good, explicitly declared a one bit signed value. Unfortunately, it does not work right either. Now the culprit is operand size coercion. Increment value will be sign extended to match other variable. So it becomes , or -1. Incrementer becomes a decrementer. 25 What Does Work Skip all explicit sizing. module incrementer_with_overflow( input logic CLK, RST, input logic signed [7:0] IN, output logic signed [8:0] OUT); CLK or negedge RST) if (!RST) OUT <= 0; else OUT <= IN + 1; endmodule A number without a specific base, such as "1", defaults to a signed decimal expression. 26 Synthesis Output Logic synthesizer produces a netlist: similar data to a schematic. It also produces reports. Analysis of reports tells if design constraints have been met. Meeting constraints may be a long and iterative process. It may be totally impossible, too. Synthesis Source Code module counter(clk, RST, COUNT); input CLK, RST; output [3:0] COUNT; reg [3:0] COUNT; CLK or negedge RST) begin if (!RST) COUNT <= 0; else COUNT <= COUNT + 1; end endmodule Always Verify Before Synthesis Mentor Graphics Modelsim output: use only VCS in class. module tb_counter(); wire [3:0] COUNT; reg CLK, RST; counter C1(CLK, RST, COUNT); initial begin CLK = 1'b0; forever #10 CLK <= ~CLK; end initial begin RST <= 1'b1; #15 RST <= 1'b0; #40 RST <= 1'b1; end endmodule

6 module counter ( CLK, RST, COUNT ); output [3:0] COUNT; input CLK, RST; wire N2, N3, N4, n5, n9, n10; Hierarchical Design FD2 \COUNT_reg[3] (.D(N3),.CP(CLK),.CD(RST),.Q(COUNT[3]) ); FD2 \COUNT_reg[1] (.D(N2),.CP(CLK),.CD(RST),.Q(COUNT[1]) ); FD2 \COUNT_reg[2] (.D(N4),.CP(CLK),.CD(RST),.Q(COUNT[2]),.QN(n5) ); FT2 \COUNT_reg[0] (.CP(CLK),.CD(RST),.Q(COUNT[0]) ); EO U3 (.A(n9),.B(n5),.Z(N4) ); EO U4 (.A(COUNT[3]),.B(n10),.Z(N3) ); NR2 U5 (.A(n9),.B(n5),.Z(n10) ); ND2 U6 (.A(COUNT[1]),.B(COUNT[0]),.Z(n9) ); EO U7 (.A(COUNT[1]),.B(COUNT[0]),.Z(N2) ); endmodule Design A Instance 1 Top Level Design Design B Design A Instance 2 Design C Handling Hierarchy Top-down logic design start at the system level, work down to leaf cells. Turn it into gates Read the whole hierarchy at once into the synthesizer? Start with the top level? Work from the bottom up? Other? A combination? Either? Top-Down Synthesis Works if entire design can fit into memory. Read in the whole design hierarchy. Apply system-level constraints at the top. Let tools handle it from there Synthesize Bottom Up Design Example Proper strategy depends on design size. Synthesis block size grows all the time. Usually synthesis, unlike design, goes from the bottom up: synthesize and optimize leaf designs, then build up hierarchy. Flattening the whole design can produce better results, if the tools can handle it. 35 tap_controller.v tap_bypass.v tap_instruction.v tap_state.v Constraints 30 MHz clock Need 10 ns setup time for all inputs 10 ns output delay on all outputs 36 6

7 Synopsys Setup File TCL Syntax Setup file has hard and soft variables. Variables set in curly braces { } do not use variable substitutions. Strings must match. Variables set in quotes * $target_library do substitute variable values for names. $ is used for variable references TCL Variable Examples Stringing Variables Together Command Result set b set a b b set a $b 66 set a $b+$b+$b set a $b set a ${b}4 664 Curly braces are hard quotes in tcl. Non-variable character. delineates the variable, result is concatenation. 39 Synopsys setup files frequently reference multiple values set link_library * $target_library Means use all values (*) already part of the link_library list and add the value of variable target_library, too. So many different libraries may be searched if the tool is so instructed. 40 Synopsys Design Compiler Flow 41 Invoking Synopsys Design Compiler Design Compiler may be invoked with a graphical user interface (GUI). > design_vision No professionals use graphical mode. All professionals use text interface: dc_shell-xg-t XG mode uses new memory-management techniques, recommended for all new designs. DB is now obsolete. 42 7

8 New Version: XG is Implicit With current tools, xg mode is the default. Will not see xg-t at the prompt anymore. Do not need to explicitly ask for it when starting up. dc_shell, not dc_shell-xg-t Design Compiler Commands Synopsys Design Compiler has two user command languages. Traditional Synopsys scripting language TCL One or the other is selected upon invoking the tool. The default is now tcl mode. Must use tcl when using xg mode Command Details Not every nuance of every command will be elaborated in class. All details are available from on-line manual. To read all about a command, from the prompt (within the tool) type man <command_name> This will also return related commands: SEE ALSO Command a Command b 45 Scripting Virtually all synthesis operations are done with scripting: a command file is executed. Same concept as f files used in ECE526 Operating manually from the command line is not easily repeatable: won t be sure what you ve done. No audit trail. Makefiles are often used to call synthesis scripts. 46 Make Managing Projects with GNU Make, Andrew Oram & Steve Talbott O Reilly & Associates, Inc., $ More on Make when we deal with hierarchical compilation. Synthesis Scripts Commanding the synthesizer is another art. Many variations, many commands. Synthesis scripts have conditional clauses, loops, etc. Synopsys proprietary dcsh format is being phased out. New projects should all tcl

9 Synthesis Read in the design. Check it. Set operating conditions, constraints. Compile. Save Read in Design Start with Verilog/SV file(s). Simple files can be read in with a read command. Any parameterized designs need to be done in two steps analyze elaborate Reading a design with parameters will result in only the default values being used, no parameter over ride. Read Source code is usually best read in with analyze/elaborate. Net lists (previously compiled designs) must be read in with the read command. Using design compiler tcl mode (the new way, becoming the only way) reading in a file uses read_file. Simple read is reserved for channel input (UNIX system) acs_read_hdl New design compiler has an automatic hierarchical hdl read command that will search directories in path for Verilog and VHDL files. Unexpected/unwanted results are likely. Will not be discussed further in class

10 Read In a Netlist Read_file Netlist (binary file format, Verilog or VHDL) is the output of a previouslycompiled design. Why read one in to the synthesizer? Commonly done in hierarchical design: break synthesis into manageable chunks. Also may get IP from an outside source as a netlist. 55 Reading in a netlist: read_file f sverilog../syn/tap_controller.v Alternate version: read_sverilog../syn/tap_controller.v Designs not containing any new SystemVerilog constructs can use read_verilog read_file f verilog 56 Fab Article Key Points Technology shrinks leads to More masks More difficult mask fab Higher costs Lower yields 90 nm (our 2 nd library) is about the oldest still in common use, but also the highest yield and least expensive. 57 TAT (turn around time) is longer due to write times, inspection times and verification times, said Naoya Hayashi, a research fellow at Dai Nippon Printing (DNP). 58 Analyze & Elaborate HDL designs are normally read in to Design Compiler with two sequential commands Analyze to read in HDL source code Elaborate to further process Verilog module or VHDL entity Note that analyze operates on a file name and elaborate on a module name. Analyze Once the design environment is set, a file can be analyzed. Analysis includes syntax checking dc_shell-xg-t> analyze format sverilog \ tap_state.v If that step works, on to elaborate. If not, fix syntax and try again

11 Analyze This module counter(cnt, RST, COUNT); input CLK, RST; output [3:0] COUNT; reg [4:0] COUNT; CLK or negedge RST) begin if (!RST) COUNT <= 4 b0; else COUNT <= COUNT + 1; end Analyze Error Running PRESTO HDLC Searching for./counter.v Compiling source file./counter.v Error:./counter.v:4: Vector or memory size mismatch on port COUNT using last declaration. (VER-152) *** Presto compilation terminated with 1 errors. *** Loading db file '/usr/synopsys/y /libraries/syn/lsi_10k.db' 0 endmodule Simulation/Synthesis Error Checking Previous example had a size mismatch: internal register vector size differed from port size. Design Compiler caught the error and quit. How would it simulate in Verilog? Would it even compile? Verilog Doesn t Care Compiling source file "counter.v" Highest level modules: counter 0 simulation events (use +profile or +listcounts option to count) CPU time: 0.0 secs to compile secs to link secs in simulation End of Tool: VERILOG-XL p Sep 5, :26: Simulation/Synthesis Dichotomy Why doesn t the Verilog simulator care about the mismatch that causes synthesis to fail? The simulator has no concept of hardware. It does not infer flipflops. Thus it does not care if it would take four or five flipflops to implement. It isn t going to implement anything. Anaylze OK Running PRESTO HDLC Searching for./counter.v Compiling source file./counter.v Presto compilation completed successfully. Loading db file '/usr/synopsys/y /libraries/syn/lsi_10k.db'

12 Elaborate Elaborate Translates the design to a technology-independent generic logic format. Sets parameter values. Links design units (resolves hierarchical references). May replace operators with Synopsys DesignWare components. VHDL: selects architecture. No Verilog significance. 67 #Module name, not file name, is elaborated. #Synopsys comments follow #, not Verilog style dc_shell-xg-t> elaborate tap_state 68 Loading db file '/usr/synopsys/y /libraries/syn/gtech.db' Loading db file '/usr/synopsys/y /libraries/syn/standard.sldb' Loading link library 'lsi_10k' Loading link library 'gtech' Running PRESTO HDLC Memory Type Cell Type: Flipflop Width: 4 Bus: Yes Inferred memory devices in process in routine counter line 6 in file './counter.v'. Multibit Attribute: No ========================================================== multibit are cells (hard macros) that are more than one bit. Will never have ===================== them when elaborating HDL behavioral source code Register Name Type Width Bus MB AR AS SR SS ST ========================================================== ===================== Asynchronous Reset: Yes COUNT_reg Flip-flop 4 Y N Y N N N N ========================================================== Asynchronous Set: No ===================== Presto compilation completed successfully. Synchronous Reset: No Elaborated 1 design. Current design is now 'counter'. Synchronous Set: No Synchronous Toggle: No 12