ELE432. ADVANCED DIGITAL DESIGN HACETTEPE UNIVERSITY Designing with VHDL

Transcription

1 ELE432 ADVANCED DIGITAL DESIGN HACETTEPE UNIVERSITY Designing with VHDL

2 Organization of the Week Quartus II and simple I/O Combinational Sequential

3 References Required P. Chu, FPGA Prototyping by VHDL Examples Chapter 4, Regular Sequential Circuit Recommended S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design Chapter 7, Flip-Flops, Registers, Counters, and a Simple Processor ECE 448 FPGA and ASIC

4 DE1-SOC

5 DE1-SOC Altera Cyclone V SE 5CSEMA5F31C6Ndevice Altera Serial Configuration device EPCQ256 USB Blaster II(on board) for programming; JTAG Mode 64MB SDRAM(16-bit data bus) 4 Push-buttons 10 Slide switches 10 Red user LEDs Six 7-segment displays Four 50MHz clock sourcesfrom clock generator 24-bit CD-quality audio CODEC with line-in, line-out, and microphone-in jacks VGA DAC (8-bit high-speed triple DACs) with VGA-out connector TV Decoder (NTSC/PAL/SECAM) and TV-in connector PS/2 mouse/keyboard connector IR receiver and IR emitter Two 40-pin Expansion Header with diode protection A/D Converter, 4-pin SPI interface with FPGA

6 Quartus II Standard Compilation Design Flow

7

8 Some types that we need to know: *.sdc timing *.qsf signal *.sof outputfile

9 Simulation

10 How does a *.qsf file look like? #============================================================ # Y #============================================================ set_location_assignment PIN_V16 -to Y[0] set_location_assignment PIN_W16 -to Y[1] set_location_assignment PIN_V17 -to Y[2] set_location_assignment PIN_V18 -to Y[3] set_location_assignment PIN_W17 -to Y[4] set_location_assignment PIN_W19 -to Y[5] set_location_assignment PIN_Y19 -to Y[6] set_location_assignment PIN_W20 -to Y[7] set_location_assignment PIN_W21 -to Y[8] set_location_assignment PIN_Y21 -to Y[9]

11 Pin Planner We need to connect the Node Names to their actual locations

12 Simple Inputs and Outputs

13 Push Button Switch inputs

14 7 Segment LED s

15 J-TAG Chain on board High-Speed USB Peripheral Controller

16 Compilation and Programmer

17 VHDL Description Styles VHDL Description Styles dataflow structural behavioral ECE 448 FPGA and ASIC Concurrent statements synthesizable Components and Sequential statements interconnects Registers Shift registers Counters State machines and more if you are careful

18 Combinational-Circuit Building Blocks ECE 448 FPGA and ASIC

19 ECE 448 FPGA and ASIC Gates

20 Basic Gates AND, OR, NOT x 1 x 2 x 1 x x 1 x 2 x 1 x 2 x n 2 x n (a) AND gates x 1 x x 1 + x 2 2 x 1 x 2 x n x 1 + x x n (b) OR gates x x ECE 448 FPGA and ASIC (c) NOT gate

21 Basic Gates NAND, NOR x 2 x 1 x x 1 x x 2 1 x 2 x n 2 x 1 x n (a) NAND gates x 1 x 1 x x 1 + x 2 2 x 2 x 1 + x x n x n (b) NOR gates ECE 448 FPGA and ASIC

22 DeMorgan s Theorem and other symbols for NAND, NOR x 1 x 2 x 1 x 2 x 1 x 2 (a) x 1 x 2 = x 1 + x 2 x 1 x 2 x 1 x 2 x 1 x 2 (b) x 1 + x 2 = x 1 x 2 ECE 448 FPGA and ASIC

23 Basic Gates XOR x 1 x 2 f = x 1 x x 1 x 2 f = x 1 x 2 (a) Truth table (b) Graphical symbol x 1 x 2 f = x 1 x 2 ECE 448 FPGA and ASIC (c) Sum-of-products implementation

24 Basic Gates XNOR x 1 x 2 f = x 1 x x 1 x 2 f = x 1 x 2 = x. 1 x 2 (a) Truth table (b) Graphical symbol x 1 x 2 f = x 1 x 2 ECE 448 FPGA and ASIC (c) Sum-of-products implementation

25 Data-flow VHDL: Example x y cin s cout ECE 448 FPGA and ASIC

26 Data-flow VHDL: Example (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY fulladd IS PORT ( x : IN STD_LOGIC ; y : IN STD_LOGIC ; cin : IN STD_LOGIC ; s : OUT STD_LOGIC ; cout : OUT STD_LOGIC ) ; END fulladd ; ECE 448 FPGA and ASIC

27 Data-flow VHDL: Example (2) ARCHITECTURE dataflow OF fulladd IS BEGIN s <= x XOR y XOR cin ; cout <= (x AND y) OR (cin AND x) OR (cin AND y) ; END dataflow ; ECE 448 FPGA and ASIC

28 Logic Operators Logic operators and or nand nor xor not xnor Logic operators precedence only in VHDL-93 Highest not and or nand nor xor xnor Lowest ECE 448 FPGA and ASIC

29 No Implied Precedence Wanted: y = ab + cd Incorrect y <= a and b or c and d ; equivalent to y <= ((a and b) or c) and d ; equivalent to y = (ab + c)d Correct y <= (a and b) or (c and d) ; ECE 448 FPGA and ASIC

30 ECE 448 FPGA and ASIC Fixed Shifters & Rotators

31 FUNCTION shl(s1:std_logic_vector) return std_logic_vector is variable r : std_logic_vector(s1'high downto s1'low); begin r(r'low) := '0'; r(r'high downto 1) := s1(s1'high-1 downto 0); return r; end shl;

32 Fixed Logical Shift Right in VHDL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO 0); 4 A >>1 C 4 L A(3) A(2) A(1) A(0) 0 A(3) A(2) A(1) A C ECE 448 FPGA and ASIC C = '0' & A(3 downto 1);

33 Fixed Arithmetic Shift Right in VHDL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO 0); 4 A >>1 C 4 A A(3) A(2) A(1) A(0) A C A(3) A(3) A(2) A(1) C = A(3) & A(3 downto 1); ECE 448 FPGA and ASIC

34 Fixed Logical Shift Left in VHDL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO 0); 4 A <<1 C 4 L A(3) A(2) A(1) A(0) A(2) A(1) A(0) 0 C = A(2 downto 0) & '0'; A C ECE 448 FPGA and ASIC

35 Fixed Rotation Left in VHDL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO 0); 4 A <<< 1 C 4 A(3) A(2) A(1) A(0) A(2) A(1) A(0) A(3) C = A(2 downto 0) & A(3); A C ECE 448 FPGA and ASIC

36 Types of VHDL Description (Modeling Styles) ECE 448 FPGA and ASIC

37 Types of VHDL Description VHDL Descriptions dataflow structural Testbenches behavioral Concurrent statements Components and interconnects Sequential statements Registers State machines Instruction decoders Subset most suitable for synthesis ECE 448 FPGA and ASIC

38 Data-Flow VHDL Concurrent Statements concurrent signal assignment ( ) conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) ECE 448 FPGA and ASIC

39 Concurrent signal assignment <= target_signal <= expression; ECE 448 FPGA and ASIC

40 Conditional concurrent signal assignment When - Else target_signal <= value1 when condition1 else value2 when condition2 else... valuen-1 when conditionn-1 else valuen; ECE 448 FPGA and ASIC

41 Selected concurrent signal assignment With Select-When with choice_expression select target_signal <= expression1 when choices_1, expression2 when choices_2,... expressionn when choices_n; ECE 448 FPGA and ASIC

42 Logic Implied Most Often by Conditional and Selected Concurrent Signal Assignments ECE 448 FPGA and ASIC

43 Data-flow VHDL Major instructions Concurrent statements concurrent signal assignment ( ) conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) ECE 448 FPGA and ASIC

44 Conditional concurrent signal assignment When - Else target_signal <= value1 when condition1 else value2 when condition2 else... valuen-1 when conditionn-1 else valuen; ECE 448 FPGA and ASIC

45 Most often implied structure When - Else target_signal <= value1 when condition1 else value2 when condition2 else... valuen-1 when conditionn-1 else valuen; Value N Value N Condition N-1. Value Value Target Signal ECE 448 FPGA and ASIC Condition 2 Condition 1

46 Data-flow VHDL Major instructions Concurrent statements concurrent signal assignment ( ) conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) ECE 448 FPGA and ASIC

47 Selected concurrent signal assignment With Select-When with choice_expression select target_signal <= expression1 when choices_1, expression2 when choices_2,... expressionn when choices_n; ECE 448 FPGA and ASIC

48 Most Often Implied Structure With Select-When with choice_expression select target_signal <= expression1 when choices_1, expression2 when choices_2,... expressionn when choices_n; expression1 expression2 choices_1 choices_2 target_signal expressionn choices_n ECE 448 FPGA and ASIC choice expression

49 Allowed formats of choices_k WHEN value WHEN value_1 value_2... value N WHEN OTHERS ECE 448 FPGA and ASIC

50 Allowed formats of choice_k - example WITH sel SELECT y <= a WHEN "000", c WHEN "001" "111", d WHEN OTHERS; ECE 448 FPGA and ASIC

51 when-else vs. with-select-when (1) "when-else" should be used when: 1) there is only one condition (and thus, only one else), as in the 2-to-1 MUX 2) conditions are independent of each other (e.g., they test values of different signals) 3) conditions reflect priority (as in priority encoder); one with the highest priority need to be tested first. ECE 448 FPGA and ASIC

52 when-else vs. with-select-when (2) "with-select-when" should be used when there is 1) more than one condition 2) conditions are closely related to each other (e.g., represent different ranges of values of the same signal) 3) all conditions have the same priority (as in the 4-to- 1 MUX). ECE 448 FPGA and ASIC

53 ECE 448 FPGA and ASIC Modeling Wires and Buses

54 Signals SIGNAL a : STD_LOGIC; a 1 wire SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO 0); b 8 bus ECE 448 FPGA and ASIC

55 Merging wires and buses a b c d = a&b&c SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL b: STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL c: STD_LOGIC; SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0); d <= a & b & c; ECE 448 FPGA and ASIC

56 Splitting buses d a = d 9..6 b = d 5..1 c = d 0 SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL b: STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL c: STD_LOGIC; SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0); a <= d(9 downto 6); b <= d(5 downto 1); c <= d(0); ECE 448 FPGA and ASIC

57 ECE 448 FPGA and ASIC Constants

58 Constants Syntax: CONSTANT name : type := value; Examples: CONSTANT init_value : STD_LOGIC_VECTOR(3 downto 0) := "0100"; CONSTANT ANDA_EXT : STD_LOGIC_VECTOR(7 downto 0) := X"B4"; CONSTANT counter_width : INTEGER := 16; CONSTANT buffer_address : INTEGER := 16#FFFE#; CONSTANT clk_period : TIME := 20 ns; CONSTANT strobe_period : TIME := ms; ECE 448 FPGA and ASIC

59 Constants - features Constants can be declared in a PACKAGE, ARCHITECTURE, ENTITY When declared in a PACKAGE, the constant is truly global, for the package can be used in several entities. When declared in an ARCHITECTURE, the constant is local, i.e., it is visible only within this architecture. When declared in an ENTITY declaration, the constant can be used in all architectures associated with this entity.

60 Example of package library ieee; use ieee.std_logic_1164.all; package alu_pkg is end alu_pkg; constant OPCODE_NOR : std_logic_vector(2 downto 0) := "000"; constant OPCODE_NAND : std_logic_vector(2 downto 0) := "001"; constant OPCODE_XOR : std_logic_vector(2 downto 0) := "010"; constant OPCODE_UADD : std_logic_vector(2 downto 0) := "011"; constant OPCODE_SADD : std_logic_vector(2 downto 0) := "100"; constant OPCODE_SSUB : std_logic_vector(2 downto 0) := "101"; constant OPCODE_UMUL : std_logic_vector(2 downto 0) := "110"; constant OPCODE_SMUL : std_logic_vector(2 downto 0) := "111";

61 Using objects from a package library ieee; use ieee.std_logic_1164.all; library work; use work.alu_pkg.all; entity alu_comb is..

62 Simple Signal Assignments VHDL has built-in support for the following operators and logical AND or logical OR not logical NOT nand, nor, xor, xnor VHDL does not assume any precedence of logic operators. Use parentheses in expressions to determine precedence Exception to this is NOT logical operator In VHDL, a logic expression is called a simple assignment statement. There are other types that will be introduced that are useful for more complex circuits.

63 Signal Usage The assignment of a waveform value to a signal is referred to as signal assignment. <= The only assignment operator which can be used to assign waveforms to signals.

64 Signal Assignments VHDL provides several types of statements that can be used to assign logic values to signals Simple assignment statements Used previously, for logic or arithmetic expressions Selected signal assignments Conditional signal assignments Generate statements If-then-else statements Case statements

65 Signal Usage library ieee; use ieee.std_logic_1164.all; entity shiftcomp is port(clk, Rst, Load: in std_logic; Init: in std_logic_vector(0 to 7); Test: in std_logic_vector(0 to 7); Limit: out std_logic); end shiftcomp; architecture structure of shiftcomp is component compare port(a, B: in std_logic_vector(0 to 7); EQ: out bit); end component; component shift port(clk, Rst, Load: in std_logic; Data: in std_logic_vector(0 to 7); Q: out std_logic_vector(0 to 7)); end component; signal Q: std_logic_vector(0 to 7); begin signal X1,X2.X3,DN: std_logic; m: process (Rst, Clk) begin if Rst = `1' then Q1 <= '0'; elsif Clk = `1' and Clk'event then Q1 <= Grant; end if; end process; DN <= X1 or X3 and X2; COMP1: compare port map (Q, Test, Limit); SHIFT1: shift port map (Clk, Rst, Load, Init, Q); end structure;

66 Selected signal assignment - MUX implementation A selected signal assignment allows a signal to be assigned one of several values, based on a selection criterion Keyword WITH specifies that s is used for the selection criterion Two WHEN clauses state that f=w0 when s=0 and f=w1 otherwise The keyword OTHERS must be used architecture behavior of mux2to1 is begin with s select f <= w0 when '0', w1 when others; end behavior;

67 MUX 4-1 example library ieee; use ieee.std_logic_1164.all; entity mux4to1 is port ( w : in std_logic_vector(3 downto 0); s : in std_logic_vector(1 downto 0); f : out std_logic); end mux4to1; architecture behavior of mux4to1 is begin with s select f <= w(0) when "00", w(1) when "01", w(2) when "10", w(3) when others; end behavior;

68 ECE 448 FPGA and ASIC Decoders

69 2-to-4 Decoder (a) Truth table (b) Graphical symbol w w 1 y 3 En w 1 w 0 y 3 y 2 y 1 y 0 w 0 y 2 y En y 1 y x 0 1 x Enw <= En & w ; WITH Enw SELECT y <= "0001" WHEN "100", "0010" WHEN "101", "0100" WHEN "110", "1000" WHEN "111", "0000" WHEN OTHERS ; ECE 448 FPGA and ASIC

70 VHDL code for a 2-to-4 Decoder entity ECE 448 FPGA and ASIC LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY dec2to4 IS PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END dec2to4 ; ARCHITECTURE dataflow OF dec2to4 IS SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ; BEGIN Enw <= En & w ; WITH Enw SELECT y <= "0001" WHEN "100", "0010" WHEN "101", "0100" WHEN "110", "1000" WHEN "111", "0000" WHEN OTHERS ; END dataflow ;

71 ECE 448 FPGA and ASIC Encoders

72 Priority Encoder w w 0 w 1 w 2 w 3 y 0 y 1 z y y <= "11" WHEN w(3) = '1' ELSE "10" WHEN w(2) = '1' ELSE "01" WHEN w(1) = '1' ELSE "00" ; w 3 w 2 w 1 w 0 y 1 y 0 z z <= '0' WHEN w = "0000" ELSE '1' ; d d ECE 448 FPGA and ASIC

73 Priority Encoder library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Priority_Encoder_VHDL is port ( Sel : in std_logic_vector(3 downto 0); encoded_data : out std_logic_vector(1 downto 0); D : out std_logic); end entity Priority_Encoder_VHDL; architecture Behavioral of Priority_Encoder_VHDL is begin encoded_data <= "11" when Sel(3)='1' else "10" when Sel(2)='1' else "01" when Sel(1)='1' else "00"; D <= '0' when Sel="0000" else '1'; end architecture Behavioral;

74 ECE 448 FPGA and ASIC Multiplexers

75 Conditional Signal Assignments: Conditional Signal Assignments: C <= a xor b; -- or C <='0' when a='0' and b='0' else '1' when a='1' and b='1' else '1' when a='1' and b='0' else '0' when a='1' and b='1' else '0';

76 2-to-1 Multiplexer s s f w 0 0 f 0 w 0 w w 1 (a) Graphical symbol (b) Truth table VHDL: f <= w0 WHEN s = '0' ELSE w1 ; or f <= w1 WHEN s = 1' ELSE w0 ; ECE 448 FPGA and ASIC

77 VHDL code for a 2-to-1 Multiplexer Entity LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT ( w0, w1, s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END mux2to1 ; ARCHITECTURE dataflow OF mux2to1 IS BEGIN f <= w0 WHEN s = '0' ELSE w1 ; END dataflow ; ECE 448 FPGA and ASIC

78 Cascade of two multiplexers w 3 w y w 1 1 VHDL: s2 s1 f <= w1 WHEN s1 = 1' ELSE w2 WHEN s2 = 1 ELSE w3 ; ECE 448 FPGA and ASIC

79 VHDL design entity implementing a cascade of two multiplexers LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux_cascade IS PORT ( w1, w2, w3: IN STD_LOGIC ; s1, s2 : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END mux_cascade ; ECE 448 FPGA and ASIC ARCHITECTURE dataflow OF mux2to1 IS BEGIN f <= w1 WHEN s1 = 1' ELSE w2 WHEN s2 = 1 ELSE w3 ; END dataflow ;

80 Operators Relational operators = /= < <= > >= Logic and relational operators precedence Highest Lowest not = /= < <= > >= and or nand nor xor xnor ECE 448 FPGA and ASIC

81 Priority of logic and relational operators compare a = bc Incorrect when a = b and c else equivalent to when (a = b) and c else Correct when a = (b and c) else ECE 448 FPGA and ASIC

82 Mux 2-1 entity mux2to1 is port (w0, w1, s : in std_logic; f : out std_logic); end mux2to1; architecture behavior of mux2to1 is begin f <= w0 when s = '0' else w1; end behavior;

83 4-to-1 Multiplexer (a) Graphic symbol (b) Truth table s s 0 s 1 s 1 s 0 f w 0 00 w 1 01 w 2 10 w 3 11 f w 0 w 1 w 2 w 3 ECE 448 FPGA and ASIC WITH s SELECT f <= w0 WHEN "00", w1 WHEN "01", w2 WHEN "10", w3 WHEN OTHERS ;

84 VHDL code for a 4-to-1 Multiplexer entity LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux4to1 IS PORT ( w0, w1, w2, w3 : IN STD_LOGIC ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END mux4to1 ; ARCHITECTURE dataflow OF mux4to1 IS BEGIN WITH s SELECT f <= w0 WHEN "00", w1 WHEN "01", w2 WHEN "10", w3 WHEN OTHERS ; END dataflow ; ECE 448 FPGA and ASIC

85 1bit full adder and package decleration library ieee ; library ieee; use ieee.std_logic_1164.all ; use ieee.std_logic_1164.all; entity fulladd is package fulladd_package is port ( cin, x, y : in std_logic; component fulladd s, cout : out std_logic); port ( cin, x, y : in std_logic; end fulladd ; s, cout : out std_logic); architecture logicfunc of fulladd is end component; begin end fulladd_package; s <= x xor y xor cin; cout <= (x and y) or (cin and x) or (cin and y); end logicfunc;

86 4 bit adder library ieee; use ieee.std_logic_1164.all; use work.fulladd_package.all; entity adder4 is port ( cin : in std_logic; x, y : in std_logic_vector(3 downto 0); s : out std_logic_vector(3 downto 0); cout : out std_logic); end adder4; architecture structure of adder4 is signal c : std_logic_vector(1 to 3); begin stage0: fulladd port map ( cin, x(0), y(0), s(0), c(1) ); stage1: fulladd port map ( c(1), x(1), y(1), s(1), c(2) ); stage2: fulladd port map ( c(2), x(2), y(2), s(2), c(3) ); stage3: fulladd port map ( c(3), x(3), y(3), s(3), cout ); end structure;

87 Structural Descriptions The previous VHDL code examples are termed behavioral VHDL because they describe the behavior of a circuit without describing exactly how it is implemented in hardware. Another VHDL coding style is structural. For structural VHDL, the user typically describes the structure of a design by interconnecting several simpler designs from a library The library components may be user-defined or provided by the CAD tool vendor.

88 Component Instantiation entity design is port (a, ck, mr, din: in bit; rdy, ctrlsig: out bit); end design; architecture structure of design is component and2 port(x,y: in bit := 0 ; z: out bit); end component; component nor2 port(a,b: in bit; z: out bit); end component; component dff port(d, clock: in bit; qbar: out bit); end component; signal s1,s2: bit; begin d1:dff port map(a,ck,s1,s2); a1:and2 port map(s2,open,ctrlsig); n1:nor2 port map(a=>s1, z=>rdy, b=>mr); end structure MR A CK open Q D QBAR ctrlsig S1 S2 RDY CTRLS

89 Example for structural representation library ieee ; use ieee.std_logic_1164.all ; entity fulladd is port ( cin, x, y: in std_logic; s,cout: out std_logic); end fulladd ; architecture logicfunc of fulladd is begin s <= x xor y xor cin; cout <= (x and y) or (cin and x) or (cin and y); end logicfunc;

90 Use of package fulladd_package library ieee; use ieee.std_logic_1164.all; package fulladd_package is component fulladd port ( cin, x, y : in std_logic; s, cout : out std_logic); end component; end fulladd_package;

91 4-bit ripple carry adder library ieee; use ieee.std_logic_1164.all; use work.fulladd_package.all; entity adder4 is port ( cin : in std_logic; x, y : in std_logic_vector(3 downto 0); s : out std_logic_vector(3 downto 0); cout : out std_logic); end adder4; architecture structure of adder4 is signal c : std_logic_vector(1 to 3); begin stage0: fulladd port map ( cin, x(0), y(0), s(0), c(1) ); stage1: fulladd port map ( c(1), x(1), y(1), s(1), c(2) ); stage2: fulladd port map ( c(2), x(2), y(2), s(2), c(3) ); stage3: fulladd port map ( c(3), x(3), y(3), s(3), cout ); end structure;

92 Generate Statements Whenever we write structural VHDL code, we often create instances of a particular component A multi-stage ripple carry adder made from a number of single-bit full adders might be an example If we need to create a large number of instances of a component, a more compact form is desired VHDL provides a feature called the for generate statement This statement provides a loop structure

93 4-bit ripple carry adder library ieee; use ieee.std_logic_1164.all; use work.fulladd_package.all; entity adder4 is port ( cin : in std_logic; x, y : in std_logic_vector(3 downto 0); s : out std_logic_vector(3 downto 0); cout : out std_logic); end adder4; architecture structure of adder4 is signal c : std_logic_vector(0 to 4); begin c(0) <= cin; cout <= c(4); g1: for i in 0 to 3 generate stages: fulladd port map (c(i), x(i), y(i), s(i), c(i+1)); end generate; end structure;

94 Process statement We have introduced several types of assignment statements All have the property that the order in which they appear in VHDL code does not affect the meaning of the code Because of this property, these statements are called concurrent assignment statements VHDL provides a second category of statements, sequential assignment statements, for which the ordering of the statements may affect the meaning of the code If-then-else and case statements are sequential VHDL requires that sequential assignment statements be placed inside another statement, the process statement

95 Anatomy of a Process OPTIONAL [label:] PROCESS [(sensitivity list)] [declaration part] BEGIN statement part END PROCESS [label]; ECE 448 FPGA and ASIC

96 Process statement The process statement, or simply process, begins with the PROCESS keyword, followed by a parenthesized list of signals called the sensitivity list This list includes, at most, all the (input) signals used inside the process There may be no signals in the sensitivity list (i.e. the list may not exist) Generally the list includes all signals that can be used to activate the process Statements inside the process are evaluated in sequential order This is true from a simulation standpoint From a synthesized hardware point-of-view, multiple assignments to a single signal (variable) generally implies multiplexing of the assignments to produce a single output Assignments made inside the process are not visible outside the process until all statements in the process have been evaluated If there are multiple assignments to the same signal inside a process, only the last one has any visible effect

97 PROCESS with a SENSITIVITY LIST List of signals to which the process is sensitive. Whenever there is an event on any of the signals in the sensitivity list, the process fires. Every time the process fires, it will run in its entirety. WAIT statements are NOT ALLOWED in a processes with SENSITIVITY LIST. label: process (sensitivity list) declaration part begin statement part end process; ECE 448 FPGA and ASIC

98 Process Blocks The basic unit of behavioral descriptions. A process is considered a series of sequential statements which represents a single action during simulation. Executed once at the beginning of simulation and then each time an event occurs on any signal in its sensitivity list and executed until a wait statement or the end of the process is reached. All statements within a process are sequential, the execution time of a process can be thought of as zero T. Labels Architecture SEQ of DECODER 2x4 is begin MYPROCESS: process(a,b,enable) variable ABAR, BBAR:BIT; begin end; ABAR := not A; BBAR := not B; if (ENABLE = 1 ) then Z(3) <= not (A and B); Z(0) <= not (ABAR and BBAR); Z(2) <= not (A and BBAR); else Z<= 1111 ; end if; end process MYPROCESS; Assign values to signal drivers Sensitivity list (equivalent to wait on statements) Declarations Sequential statements Actual assignment of Signals

99 Interaction of Processes READY Serial in Process RX DATA Process MP PARALLEL OUT CLK ACK RX: process begin READ_WORD(SERIAL_IN,CLK,DATA); READY <= 1 ; wait until ACK = 1 ; READY <= 0 ; wait for 50 ns; end process RX; READY DATA ACK MP: process begin wait for 25 ns; PARALLEL_OUT <= DATA; ACK <= 1, 0 after 25 ns; wait until READY = 1 ; end process MP; READY ACK ns

100 Process Rules If a process has a sensitivity list, then it can not contain a wait statement A process with a sensitivity list is always triggered at time 0 because all signals always have an initial event placed on them. A process without a sensitivity list is triggered at time 0 initially If a proc without a sensitivity list falls out the bottom then it loops back to top until it hits a wait statement.

101 Processes in VHDL Processes Describe Sequential Behavior Processes in VHDL Are Very Powerful Statements Allow to define an arbitrary behavior that may be difficult to represent by a real circuit Not every process can be synthesized Use Processes with Caution in the Code to Be Synthesized Use Processes Freely in Testbenches ECE 448 FPGA and ASIC

102 Component Equivalent of a Process priority: PROCESS (clk) BEGIN IF w(3) = '1' THEN y <= "11" ; ELSIF w(2) = '1' THEN y <= "10" ; ELSIF w(1) = c THEN y <= a and b; ELSE z <= "00" ; END IF ; END PROCESS ; clk w a b c priority All signals which appear on the left of signal assignment statement (<=) are outputs e.g. y, z All signals which appear on the sensitivity list are inputs e.g. clk All signals which appear on the right of signal assignment statement (<=) or in logic expressions are inputs e.g. w, a, b, c Note that not all inputs need to be included on the sensitivity list y z ECE 448 FPGA and ASIC

103 Process - Priority encoder (IF-THEN-ELSE) architecture behavior of priority is begin process (D) begin if D(3) = '1' then Q <= "11"; elsif D(2) = '1' then Q <= "10"; elsif D(1) = '1' then Q <= "01"; else Q <= "00"; end if; end process; z <= '0' when D = "0000" else '1'; end behavior;

104 Process - Priority encoder (alternative) architecture behavior of priority is begin process (w) begin y <= "00"; if w(1) = '1' then y <= "01" ; end if; if w(2) = '1' then y <= "10" ; end if; if w(3) = '1' then y <= "11" ; end if; z <= '1'; if w = "0000" then z <= '0' ; end if; end process; end behavior;

105 Process mux architecture behavior of mux2to1 is begin process (A,B,sel) begin if sel = '0' then out <= A; else out <= B; end if; end process; end behavior;

106 Case Statement A case statement is similar to a selected assignment statement in that the case statement has a selection signal and includes WHEN clauses for various valuations of the selection signal Begins with a CASE keyword Each WHEN clause specifies the statements that should be evaluated when the selection signal has a specified value The case statement must include a when clause for all valuations of the selection signal Use the OTHERS keyword

107 Process mux with case architecture behavior of mux2to1 is begin process (A,B,sel) begin case sel is when '0' => out <= A; when others => out <= B; end case; end process; end behavior;

108 Process binary decoder with case architecture behavior of dec2to4 is begin process (w, en) begin if en = '1' then case w is when "00" => y <= "1000"; when "01" => y <= "0100"; when "10" => y <= "0010"; when others => y <= "0001"; end case ; else y <= "0000"; end if; end process; end behavior;

109 Small ALU Implementation using 2-1 decoder entity DE1_SoC is port ( SW : in std_logic_vector(9 downto 0); LEDR : out std_logic_vector(9 downto 0) ); end DE1_SoC; Function 10

110 Small ALU Implementation using 2-1 decoder architecture ppl_type of DE1_SoC is begin process(sw) begin LEDR(9 downto 3) <= (others => '0'); case SW(1 downto 0) is when "00" => LEDR(2 downto 0) <= ('0' & SW(9 downto 8)) + ('0' & SW(7 downto 6)); when "01" => LEDR(2 downto 0) <= ('0' & SW(9 downto 8)) + (not ('0' & SW(7 downto 6))+"001"); when "10" => LEDR(2 downto 0) <= ('0' & SW(9 downto 8)) and ('0' & SW(7 downto 6)); when "11" => LEDR(2 downto 0) <= ('0' & SW(9 downto 8)) xor ('0' & SW(7 downto 6)); when others => LEDR(2 downto 0) <= "XXX"; end case; end process; end;

111 ECE 448 FPGA and ASIC Adders

112 16-bit Unsigned Adder Cout X + S Y Cin 16 ECE 448 FPGA and ASIC

113 Operations on Unsigned Numbers For operations on unsigned numbers USE ieee.std_logic_unsigned.all and signals of the type STD_LOGIC_VECTOR OR USE ieee.numeric_std.all and signals of the type UNSIGNED and conversion functions: std_logic_vector(), unsigned() ECE 448 FPGA and ASIC

114 VHDL code for a 16-bit Unsigned Adder LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY adder16 IS PORT ( Cin : IN STD_LOGIC ; X : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ; Cout : OUT STD_LOGIC ) ; END adder16 ; ARCHITECTURE dataflow OF adder16 IS SIGNAL Sum : STD_LOGIC_VECTOR(16 DOWNTO 0) ; BEGIN Sum <= ('0' & X) + Y + Cin ; S <= Sum(15 DOWNTO 0) ; Cout <= Sum(16) ; END dataflow ;

115 Addition of Unsigned Numbers (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.numeric_std.all ; ENTITY adder16 IS PORT ( Cin : IN STD_LOGIC ; X : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ; Cout : OUT STD_LOGIC ) ; END adder16 ;

116 Addition of Unsigned Numbers (2) ARCHITECTURE dataflow OF adder16 IS SIGNAL Xu : UNSIGNED(15 DOWNTO 0); SIGNAL Yu: UNSIGNED(15 DOWNTO 0); SIGNAL Su : UNSIGNED(16 DOWNTO 0) ; BEGIN Xu <= unsigned(x); Yu <= unsigned(y); Su <= ('0' & Xu) + Yu + unsigned(std_logic_vector' ('0' & Cin)) ; S <= std_logic_vector(su(15 DOWNTO 0)) ; Cout <= Su(16) ; END dataflow ;

117 Addition of Unsigned Numbers (3) ARCHITECTURE dataflow OF adder16 IS signal Sum: STD_LOGIC_VECTOR(16 DOWNTO 0) ; BEGIN Sum <= std_logic_vector( unsigned('0' & X) + unsigned(y) + unsigned(std_logic_vector' ('0' & Cin)) ) ; S <= Sum(15 downto 0); Cout <= Sum(16) ; END dataflow ;

118 Operations on Signed Numbers For operations on signed numbers USE ieee.numeric_std.all, signals of the type SIGNED, and conversion functions: std_logic_vector(), signed() OR USE ieee.std_logic_signed.all and signals of the type STD_LOGIC_VECTOR

119 Signed and Unsigned Types Behave exactly like STD_LOGIC_VECTOR plus, they determine whether a given vector should be treated as a signed or unsigned number. Require USE ieee.numeric_std.all;

120 ECE 448 FPGA and ASIC Multipliers

121 Unsigned vs. Signed Multiplication Unsigned Signed x x x x

122 8x8-bit Unsigned Multiplier 8 8 a * c b U 16

123 Multiplication of unsigned numbers LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all ; entity multiply is port( a : in STD_LOGIC_VECTOR(7 downto 0); b : in STD_LOGIC_VECTOR(7 downto 0); c : out STD_LOGIC_VECTOR(15 downto 0) ); end multiply; architecture dataflow of multiply is begin c <= a * b; end dataflow;

124 8x8-bit Signed Multiplier 8 8 a * c b S 16 ECE 448 FPGA and ASIC

125 Multiplication of signed numbers LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all ; entity multiply is port( a : in STD_LOGIC_VECTOR(7 downto 0); b : in STD_LOGIC_VECTOR(7 downto 0); c : out STD_LOGIC_VECTOR(15 downto 0) ); end multiply; architecture dataflow of multiply is begin c <= a * b; end dataflow; ECE 448 FPGA and ASIC

126 8x8-bit Unsigned and Signed Multiplier 8 8 a cu * b cs ECE 448 FPGA and ASIC

127 LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all ; Multiplication of signed and unsigned numbers entity multiply is port( a : in STD_LOGIC_VECTOR(7 downto 0); b : in STD_LOGIC_VECTOR(7 downto 0); cu : out STD_LOGIC_VECTOR(15 downto 0); cs : out STD_LOGIC_VECTOR(15 downto 0) ); end multiply; architecture dataflow of multiply is begin -- signed multiplication cs <= STD_LOGIC_VECTOR(SIGNED(a)*SIGNED(b)); -- unsigned multiplication cu <= STD_LOGIC_VECTOR(UNSIGNED(a)*UNSIGNED(b)); end dataflow;

128 ECE 448 FPGA and ASIC Comparators

129 4-bit Number Comparator 4 4 A B A > B AgtB AgtB <= '1' WHEN A > B ELSE '0' ; ECE 448 FPGA and ASIC

130 VHDL code for a 4-bit Unsigned Number Comparator entity LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY compare IS PORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; AgtB : OUT STD_LOGIC ) ; END compare ; ARCHITECTURE dataflow OF compare IS BEGIN AgtB <= '1' WHEN A > B ELSE '0' ; END dataflow ; ECE 448 FPGA and ASIC

131 VHDL code for a 4-bit Signed Number Comparator entity LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_signed.all ; ENTITY compare IS PORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; AgtB : OUT STD_LOGIC ) ; END compare ; ARCHITECTURE dataflow OF compare IS BEGIN AgtB <= '1' WHEN A > B ELSE '0' ; END dataflow ; ECE 448 FPGA and ASIC

132 ECE 448 FPGA and ASIC Buffers

133 Tri-state Buffer e x f e = 0 (a) A tri-state buffer x f e x f Z Z 0 1 x e = 1 (b) Equivalent circuit f (c) Truth table ECE 448 FPGA and ASIC

134 Four types of Tri-state Buffers e e x f x f f <= x WHEN (e(a) = '1') ELSE 'Z'; f <= not x WHEN (b) (e = '1') ELSE 'Z'; e e x f x f ECE 448 FPGA and ASIC f <= x WHEN (e(c) = '0') ELSE 'Z'; f <= not x WHEN (d) (e = '0') ELSE 'Z';

135 Tri-state Buffer entity (1) LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY tri_state IS PORT ( e: IN STD_LOGIC; x: IN STD_LOGIC; f: OUT STD_LOGIC ); END tri_state; ECE 448 FPGA and ASIC

136 Tri-state Buffer entity (2) ARCHITECTURE dataflow OF tri_state IS BEGIN f <= x WHEN (e = 1 ) ELSE Z ; END dataflow; ECE 448 FPGA and ASIC

137 Describing Combinational Logic Using Dataflow Design Style ECE 448 FPGA and ASIC

138 ECE 448 FPGA and ASIC MLU Example

139 MLU Block Diagram A 0 1 A1 MUX_0 MUX_4_1 NEG_A MUX_1 MUX_2 IN0 IN1 IN2 OUTPUT IN3 SEL0 SEL1 Y1 0 1 Y B 0 1 B1 L1 L0 NEG_Y NEG_B MUX_3

140 MLU: Entity Declaration LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY mlu IS PORT( NEG_A : IN STD_LOGIC; NEG_B : IN STD_LOGIC; NEG_Y : IN STD_LOGIC; A : IN STD_LOGIC; B : IN STD_LOGIC; L1 : IN STD_LOGIC; L0 : IN STD_LOGIC; Y : OUT STD_LOGIC ); END mlu; ECE 448 FPGA and ASIC

141 MLU: Architecture Declarative Section ARCHITECTURE mlu_dataflow OF mlu IS SIGNAL A1 : STD_LOGIC; SIGNAL B1 : STD_LOGIC; SIGNAL Y1 : STD_LOGIC; SIGNAL MUX_0 : STD_LOGIC; SIGNAL MUX_1 : STD_LOGIC; SIGNAL MUX_2 : STD_LOGIC; SIGNAL MUX_3 : STD_LOGIC; SIGNAL L: STD_LOGIC_VECTOR(1 DOWNTO 0);

142 BEGIN MLU - Architecture Body A1<= NOT A WHEN (NEG_A='1') ELSE A; B1<= NOT B WHEN (NEG_B='1') ELSE B; Y <= NOT Y1 WHEN (NEG_Y='1') ELSE Y1; MUX_0 <= A1 AND B1; MUX_1 <= A1 OR B1; MUX_2 <= A1 XOR B1; MUX_3 <= A1 XNOR B1; L <= L1 & L0; with (L) select Y1 <= MUX_0 WHEN "00", MUX_1 WHEN "01", MUX_2 WHEN "10", MUX_3 WHEN OTHERS; END mlu_dataflow;

143 Sequential Logic Synthesis for Beginners

144 For Beginners Use processes with very simple structure only to describe - registers - shift registers - counters - state machines. Create generic entities for registers, shift registers, and counters, and instantiate the corresponding components in a higher level circuit using GENERIC MAP PORT MAP. Supplement sequential components with combinational logic described using concurrent statements.

145 Sequential Logic Synthesis for Intermediates ECE 448 FPGA and ASIC

146 For Intermediates 1. Use processes with IF and CASE statements only. LOOPS or VARIABLES are not recommended 2. Sensitivity list of the PROCESS should include only signals that can by themselves change the outputs of the sequential circuit (typically, clock and asynchronous set or reset) 3. Do not use PROCESSes without sensitivity list (they can be synthesizable, but make simulation inefficient)

147 For Intermediates (2) Given a single signal, the assignments to this signal should only be made within a single process block in order to avoid possible conflicts in assigning values to this signal. Process 1: PROCESS (a, b) BEGIN y <= a AND b; END PROCESS; Process 2: PROCESS (a, b) BEGIN y <= a OR b; END PROCESS;

148 Review of VHDL for Sequential Circuits Basic storage elements Structural design using library components Behavioral design: D latches and D flip-flops Options including Synchronous and asynchronous reset Multiplexed inputs Enable inputs Counters Shift Registers Arbitrary finite state machines (FSM) next week? Mealy and Moore model designs next week?

149 Behavioral Design Style: Registers & Counters ECE 448 FPGA and ASIC

150 ECE 448 FPGA and ASIC Registers

151 D latch Graphical symbol D Q Clock Truth table Clock D Q(t+1) Q(t) 0 1 Timing diagram Clock D Q t 1 t 2 t 3 t 4 Time ECE 448 FPGA and ASIC

152 D flip-flop Graphical symbol D Q Clock Truth table Clk D Q(t+1) Q(t) 1 Q(t) Timing diagram Clock D Q ECE 448 FPGA and ASIC t 1 t 2 t 3 t 4 Time

153 D latch LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY latch IS PORT ( D, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END latch ; ARCHITECTURE behavioral OF latch IS BEGIN PROCESS ( D, Clock ) BEGIN IF Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END behavioral; D Clock Q ECE 448 FPGA and ASIC

154 Structural VHDL Using a D flip-flop package library ieee; use ieee.std_logic_1164.all; library altera; use altera.maxplus2.all; entity flipflop is port ( d, clock : in std_logic; reset_n, preset_n : in std_logic; q : out std_logic); end flipflop; architecture structure of flipflop is begin dff_instance: dff port map (d,clock,reset_n,preset_n,q); end structure;

155 Code for a gated D latch library ieee; use ieee.std_logic_1164.all; entity latch is port ( d, clk : in std_logic;q : out std_logic); end latch; architecture behavior of latch is begin process ( d, clk ) begin if clk = '1' then q <= d; end if; -- implied memory implementation -- uses the last assigned value end process; end behavior;

156 Code for a D flip-flop library ieee; use ieee.std_logic_1164.all; entity flipflop is port ( d, clock : in std_logic;q : out std_logic); end flipflop; architecture behavior of flipflop is begin process (clock) begin if clock'event and clock = '1' then q <= d; end if; end process; end behavior; Positive edge triggered

157 Code for a D flip-flop library ieee; use ieee.std_logic_1164.all; entity flipflop is port ( d, clock : in std_logic; q : out std_logic); end flipflop; architecture behavior of flipflop is begin process (clock) begin if rising_edge(clock) then q <= d; end if; end process; falling edge for negative going edge

158 Code for a D flip-flop (alternative using wait) library ieee; use ieee.std_logic_1164.all; entity flipflop is port ( d, clock : in std_logic; q : out std_logic ); end flipflop; architecture behavior of flipflop is begin process begin wait until clock'event and clock = '1'; q <= d; end process; end behavior;

159 Asychronous vs. Synchronous In the IF loop, asynchronous items are Before the rising_edge(clock) statement In the IF loop, synchronous items are After the rising_edge(clock) statement ECE 448 FPGA and ASIC

160 D flip-flop with synchronous reset library ieee; use ieee.std_logic_1164.all; entity flipflop is port ( d, reset_n, clock : in std_logic; q : out std_logic); end flipflop; architecture behavior of flipflop is begin process begin wait until clock'event and clock = '1'; if reset_n = '0' then q <= '0'; else q <= d; end if; end process; D Q Clock Reset

161 D flip-flop with MUX input library ieee; use ieee.std_logic_1164.all; entity muxdff is port ( d0, d1, sel, clock : in std_logic; q : out std_logic); end muxdff; architecture behavior of muxdff is begin process begin wait until clock'event and clock = '1'; if sel = '0' then q <= d0; else q <= d1; end if; end process; end behavior;

162 D flip-flop with enable input library ieee; use ieee.std_logic_1164.all; entity flipflop is port ( enable, d, clk : in std_logic;q : out std_logic); end flipflop; architecture behavior of flipflop is begin process(clk) begin if enable= 0 then null; elsif rising_edge(clk) then q <= d; end if; end process; This will be our preferred method for creating a D flip-flop or a multibit register with enable.

163 D flip-flop with asynchronous reset library ieee; use ieee.std_logic_1164.all; entity flipflop is port ( reset_n, d, clk : in std_logic; q : out std_logic); end flipflop; architecture behavior of flipflop is begin process(clk,reset_n) begin if reset_n = 0 then q <= 0 ; elsif rising_edge(clk) then q <= d; end if; end process; end behavior; This will be our preferred method for creating a D flip-flop or a multibit register with reset. D Clock Q Reset

164 8-bit register with asynchronous reset LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY reg8 IS PORT ( D : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ; Reset, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ; END reg8 ; ARCHITECTURE behavioral OF reg8 IS BEGIN PROCESS ( Reset, Clock ) BEGIN IF Reset = '1' THEN Q <= " " ; ELSIF rising_edge(clock) THEN Q <= D ; END IF ; END PROCESS ; END behavioral ;` 8 Reset 8 D Q Clock reg8

165 N-bit register with asynchronous reset LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY regn IS GENERIC ( N : INTEGER := 16 ) ; PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Reset, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END regn ; ARCHITECTURE behavioral OF regn IS BEGIN PROCESS ( Reset, Clock ) BEGIN IF Reset = '1' THEN Q <= (OTHERS => '0') ; ELSIF rising_edge(clock) THEN Q <= D ; END IF ; END PROCESS ; END behavioral ; N Reset D Clock regn Q N

166 Use of OTHERS OTHERS stand for any index value that has not been previously mentioned. Q <= can be written as Q <= (0 => 1, OTHERS => 0 ) Q <= can be written as Q <= (7 => 1, 0 => 1, OTHERS => 0 ) or Q <= (7 0 => 1, OTHERS => 0 ) Q <= can be written as Q <= (4 downto 1=> 1, OTHERS => 0 )

167 N-bit register with enable LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY regne IS GENERIC ( N : INTEGER := 8 ) ; PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Enable, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END regne ; ARCHITECTURE behavioral OF regne IS BEGIN PROCESS (Clock) BEGIN IF rising_edge(clock) THEN IF Enable = '1' THEN Q <= D ; END IF ; END IF; END PROCESS ; END behavioral ; N Enable D Q Clock regn N ECE 448 FPGA and ASIC

168 Implementing two registers in a single process Enf Enf Cout_tmp D En Q Cout V_tmp D En Q V Clk Clk Reset Reset ECE 448 FPGA and ASIC

169 Implementing two registers in a single process PROCESS (Clk, Reset) BEGIN IF Reset= '1' THEN Cout <= '0'; V <= '0'; ELSIF rising_edge(clk) THEN IF Enf = '1' THEN Cout <= Cout_tmp ; V <= V_tmp; END IF ; END IF; END PROCESS ; ECE 448 FPGA and ASIC

170 Implementing two registers in a single process EnC EnV Cout_tmp D En Q Cout V_tmp D En Q V Clk Clk Reset Reset ECE 448 FPGA and ASIC

171 Implementing two registers in a single process PROCESS (Clk, Reset) BEGIN IF Reset = '1' THEN Cout <= 0 ; V <= '0'; ELSIF rising_edge(clk) THEN IF EnC = '1' THEN Cout <= Cout_tmp ; END IF ; IF EnV = '1' THEN V <= V_tmp; END IF ; END IF; END PROCESS ; ECE 448 FPGA and ASIC

172 ECE 448 FPGA and ASIC Counters

173 Counter Modeling with VHDL Counters are simple examples of sequential circuits Counters can be modeled as arbitrary FSMs, but this is not the most straightforward method of modeling these circuits But we will look at this later! Counters can be easily modeled using basic arithmetic expressions Options include: Arithmetic operations on UNSIGNED and SIGNED signals Use of the INTEGER data type

174 2-bit up-counter with synchronous reset LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY upcount IS PORT ( Reset, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ) ; END upcount ; ARCHITECTURE behavioral OF upcount IS SIGNAL Count : std_logic_vector(1 DOWNTO 0); BEGIN upcount: PROCESS ( Clock ) BEGIN IF rising_edge(clock) THEN IF Reset = '1' THEN Count <= "00" ; ELSE Count <= Count + 1 ; END IF ; END IF; END PROCESS; Q <= Count; END behavioral; ECE 448 FPGA and ASIC Reset Q upcount Clock 2

175 4-bit up-counter with asynchronous reset (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY upcount_ar IS PORT ( Clock, Reset, Enable : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)) ; END upcount_ar ; Enable Q Clock Reset 4 upcount ECE 448 FPGA and ASIC

176 4-bit up-counter with asynchronous reset (2) ARCHITECTURE behavioral OF upcount _ar IS SIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0) ; BEGIN PROCESS ( Clock, Reset ) BEGIN IF Reset = '1' THEN Count <= "0000" ; ELSIF rising_edge(clock) THEN IF Enable = '1' THEN Count <= Count + 1 ; END IF ; Enable END IF ; Q END PROCESS ; Q <= Count ; Clock END behavioral ; Resetn 4 upcount ECE 448 FPGA and ASIC

177 Four bit up counter - entity library ieee; use ieee.std_logic_1164.all; -- use numeric_std to include -- signed and unsigned data types use ieee.numeric_std.all; entity upcount is port ( clock, reset_n,e : in std_logic; q : out unsigned(3 downto 0)); end upcount;

178 Four bit up counter -architecture architecture behavior of upcount is signal count : unsigned(3 downto 0); begin process (clock,reset_n) begin if reset_n = '0' then count <= "0000"; elsif (clock'event and clock = '1') then if e = '1' then count <= count + 1; else count <= count; end if; end if; end process; q <= count; end behavior;

179 Up Counter Using INTEGER - entity library ieee; use ieee.std_logic_1164.all; entity count is port( clock : in std_logic; sload : in std_logic; -- integer data types are a default size of 32 bits -- use a range specifier to limit the number of bits -- generated for the register (5 bits in this case) data : in integer range 0 to 31; result : out integer range 0 to 31; end count;

180 Up Counter Using INTEGER - architecture architecture rtl of count is signal result_reg : integer range 0 to 31; begin process (clock) begin if (clock'event and clock = '1') then if (sload = '1') then result_reg <= data; else result_reg <= result_reg + 1; end if; end if; end process; result <= result_reg; end rtl; You can use other variations of Clock here

181 ECE 448 FPGA and ASIC Shift Registers

182 Shift register internal structure Q(3) Q(2) Q(1) Q(0) Sin D Q D Q D Q D Q Clock Enable

183 Shift Register With Parallel Load Load D(3) Sin D(2) D(1) D(0) D Q D Q D Q D Q Clock Enable Q(3) Q(2) Q(1) Q(0)

184 VHDL Shift Register Design - entity -- vhdl code for an 8-bit shift-left register with a positive- -- edge clock, asynchronous clear, serial in, and serial out. library ieee; use ieee.std_logic_1164.all; entity shift is port( -- clk is the clock for the shift operation -- si is a serial input into the lsb of the shift register -- clr is an asynchronous active high clear control signal clk, si, clr : in std_logic; -- so is a serial output from the msb of the shift register so : out std_logic); end shift;

185 VHDL Shift Register Design - architecture architecture behavior of shift is signal s_reg: std_logic_vector(7 downto 0); begin process(clk,clr) begin if(clr='1') then s_reg <= " "; elsif rising_edge(clk) then s_reg <= s_reg (6 downto 0) & si; end if; end process; so <= s_reg(7); end behavior;

186 Rotate Register Example use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity rotatereg is generic( width : integer := 8); port(clk : in std_logic; dir : in std_logic := '0'; reg_out : out std_logic_vector(width-1 downto 0)); end rotatereg; architecture behavior of rotatereg is signal reg : std_logic_vector(width-1 downto 0) := (0 => '1', others => '0'); begin process(clk) begin if rising_edge(clk) then if (dir='0') then -- Rotate right if dir='0' reg <= reg(0) & reg(width-1 downto 1); else reg <= reg(width-2 downto 0) & reg(width-1); end if; end if; end process; reg_out <= reg; end behavior;

187 4-bit shift register with parallel load (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY shift4 IS PORT ( D : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; Enable : IN STD_LOGIC ; Load : IN STD_LOGIC ; Sin : IN STD_LOGIC ; Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END shift4 ; 4 Enable D Q Load Sin Clock 4 shift4 ECE 448 FPGA and ASIC

188 4-bit shift register with parallel load (2) ARCHITECTURE behavioral OF shift4 IS SIGNAL Qt : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN 4 Enable PROCESS (Clock) D Q BEGIN Load IF rising_edge(clock) THEN Sin IF Enable = 1 THEN IF Load = '1' THEN Clock Qt <= D ; ELSE Qt <= Sin & Qt(3 downto 1); END IF ; END PROCESS ; Q <= Qt; END behavioral ; END IF; 4 shift4 ECE 448 FPGA and ASIC

189 N-bit shift register with parallel load (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY shiftn IS GENERIC ( N : INTEGER := 8 ) ; PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Enable : IN STD_LOGIC ; Load : IN STD_LOGIC ; Sin : IN STD_LOGIC ; Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END shiftn ; N Enable D Q Load Sin Clock N shiftn ECE 448 FPGA and ASIC

190 N-bit shift register with parallel load (2) ARCHITECTURE behavioral OF shiftn IS SIGNAL Qt: STD_LOGIC_VECTOR(N-1 DOWNTO 0); BEGIN N Enable PROCESS (Clock) D Q BEGIN IF rising_edge(clock) THEN Load IF Enable = 1 THEN Sin IF Load = '1' THEN Clock Qt <= D ; ELSE Qt <= Sin & Qt(N-1 downto 1); END IF ; END PROCESS ; Q <= Qt; END behavior al; END IF; N shiftn ECE 448 FPGA and ASIC

191 ECE 448 FPGA and ASIC Generic Component Instantiation

192 N-bit register with enable LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY regne IS GENERIC ( N : INTEGER := 8 ) ; PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Enable, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END regne ; ARCHITECTURE Behavior OF regne IS BEGIN PROCESS (Clock) BEGIN IF (Clock'EVENT AND Clock = '1' ) THEN IF Enable = '1' THEN Q <= D ; END IF ; END IF; END PROCESS ; END Behavior ; N Enable D Q Clock regne N ECE 448 FPGA and ASIC

193 Circuit built of medium scale components s(0) r(0) 0 p(0) En r(1) r(2) r(3) r(4) r(5) p(1) p(2) p(3) w 0 w 1 w 2 w 3 priority y 1 y 0 z q(1) q(0) ena w 1 y 3 w 0 y 2 y 1 En dec2to4 y 0 z(3) z(2) z(1) z(0) Enable t(3) D Q t(2) t(1) regne t(0) Clk Clock s(1) ECE 448 FPGA and ASIC

194 Structural description example (1) VHDL-87 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY priority_resolver IS PORT (r: IN STD_LOGIC_VECTOR(5 DOWNTO 0) ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; clk : IN STD_LOGIC; en : IN STD_LOGIC; t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END priority_resolver; ARCHITECTURE structural OF priority_resolver IS SIGNAL p : STD_LOGIC_VECTOR (3 DOWNTO 0) ; SIGNAL q : STD_LOGIC_VECTOR (1 DOWNTO 0) ; SIGNAL z : STD_LOGIC_VECTOR (3 DOWNTO 0) ; SIGNAL ena : STD_LOGIC ; ECE 448 FPGA and ASIC

195 Structural description example (2) VHDL-87 COMPONENT mux2to1 PORT (w0, w1, s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END COMPONENT ; COMPONENT priority PORT (w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ; z : OUT STD_LOGIC ) ; END COMPONENT ; COMPONENT dec2to4 PORT (w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END COMPONENT ; ECE 448 FPGA and ASIC

196 Structural description example (3) VHDL-87 COMPONENT regne GENERIC ( N : INTEGER := 8 ) ; PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Enable, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END COMPONENT ;

197 BEGIN Structural description example (4) VHDL-87 u1: mux2to1 PORT MAP (w0 => r(0), w1 => r(1), s => s(0), f => p(0)); p(1) <= r(2); p(2) <= r(3); u2: mux2to1 PORT MAP (w0 => r(4), w1 => r(5), s => s(1), f => p(3)); u3: priority PORT MAP (w => p, y => q, z => ena); u4: dec2to4 PORT MAP (w => q, En => ena, y => z);

198 Structural description example (5) VHDL-87 u5: regne GENERIC MAP (N => 4) PORT MAP (D => z, END structural; Enable => En, Clock => Clk, Q => t ); ECE 448 FPGA and ASIC

199 ECE 448 FPGA and ASIC ROM