ECEU530. Project Presentations. ECE U530 Digital Hardware Synthesis. Rest of Semester. Memory Structures

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1 ECEU53 ECE U53 igital Hardware Synthesis Prof. Miriam Leeser November 5, 26 Lecture 8: Student project presentations Memories and FPGAs Tri-state buffers and busses Student project presentations: Wednesday, Nov 5 and Monday, November 2 Project Presentations Wednesday November 5: Corey, Rishi, Oshin, John, aryl, Natalie Monday, November 2: Shuba, Paul, oug, Shao-Han, Samir You should give a 5 minute presentation about your project in class: What is your project What are the challenges What have you accomplished so far? ECE U53 F6 2 Rest of Semester Upcoming lectures: Pipelining esigning a complex multiply accumulator: Chapter 6 of Ashenden Quiz in class on ecember 4 Sign up to demo your working project code to me November 2 th or 2 st Project due dates: Nov 2: Preliminary Project Report Your report should include: A description of your project and what it does VHL code -- should be commented Simulation results Plan for the rest of the semester ec 3: Final Project Report ue at noon! Memory Structures Register Register File ROM: Read only memory RAM: Random access memory Embedded RAM in FPGAs: Select RAM 3 4

2 ECEU53 Memory Block iagram A basic memory system is shown here: k address lines are decoded to address 2 k words of memory Each word is m bits Read and Write are single bit control lines defining the simple memory operations k Address Lines k Read Write m ata Input Lines m Memory Unit 2 k Words m Bits per Word m m ata Output Lines Basic Memory Operations Read Memory Read a data value stored in memory: Place a valid address on the address lines Wait for the read data to become stable Write MemoryWrite a data value to memory: Place a valid address on the address lines and valid data on the data lines Toggle the memory write control line Sometimes the read or write enable line is defined as a clock with precise timing information (e.g. Read Clock, Write Strobe). Otherwise, it is just an interface signal Sometimes memory must acknowledge that it has completed the operation -- handshaking 5 6 Generic RAM () Generic RAM (2) LIBRARY ieee; USE ieee.std_logic_64.all; ENTITY ram IS GENERIC (bits: INTEGER := 8; -- # of bits per word words: INTEGER := 6); -- # of words in the memory PORT ( wr_ena, clk: IN ST_LOGIC; addr: IN INTEGER RANGE to words ; data_in: IN ST_LOGIC_VECTOR(bits downto ); data_out: OUT ST_LOGIC_VECTOR(bits downto ) ); EN ram; ARCHITECTURE behavioral OF ram IS TYPE vector_array IS ARRAY ( TO words-) OF ST_LOGIC_VECTOR(bits OWNTO ); SIGNAL memory: vector_array; BEGIN PROCESS(clk, wr_ena) BEGIN IF(wr_ena= ) THEN IF (clk EVENT AN clk= ) THEN memory(addr) <= data_in; EN_IF; EN IF; EN PROCESS; data_out <= memory(addr); EN ram; 7 8

3 ECEU53 Microprocessor Register File Multi-ported Memory For read operations, functionally the regfile is equivalent to a 2- array of flip-flops with tristate outputs on each MUX, but distributed Unary control Cell with added write logic: These circuits are just functional abstractions of the actual circuits used. Motivation: Consider CPU core register file: read or write per cycle limits processor performance. Complicates pipelining. ifficult for different instructions to simultaneously read or write regfile. Common arrangement in pipelined CPUs is 2 read ports and write port 2 read ports: dual ported memory data a sel a sel b sel c Regfile data b data c 9 Behavioral escription of a Register File library IEEE; use IEEE.std_logic_64.all; use IEEE.std_logic_arith.all; write_cntrl src_addr src2_addr dst_addr write_data Register File 32 words 32 bits src_data src2_data entity regfile is port(write_data: in std_logic_vector(3 downto ); dst_addr,src_addr,src2_addr: in UNSIGNE(4 downto ); write_cntrl: in std_logic; src_data,src2_data: out std_logic_vector(3 downto )); end regfile; Behavioral escription of a Register File, asynchronous architecture process_behavior of regfile is type reg_array is array( to 3) of std_logic_vector (3 downto ); begin regfile_process: process(src_addr,src2_addr,dst_addr,write_cntrl) variable data_array: reg_array := ( (X ), (X ),... (X )); variable addrofsrc, addrofsrc2, addrofdst: integer; begin addrofsrc := conv_integer(src_addr); addrofsrc2 := conv_integer(src2_addr); addrofdst := conv_integer(dst_addr); if write_cntrl = then data_array(addrofdst) := write_data; end if; src_data <= data_array(addrofsrc) after ns; src2_data <= data_array(addrofsrc2) after ns; end process regfile_process; end process_behavior; 2

4 ECEU53 Xilinx FPGA Architecture Using SRAM to Implement Logic CLB Configurable Logic Block IOB Input/Output Block PSM Programmable Switch Matrix PIP Programmable Interconnect Point 3 4 A Simplified Logic Slice Mapping a Function to a 4-input LUT 5 6

5 ECEU53 CLB Used as RAM Memory Blocks in FPGAs LUTs can double as small RAM blocks: 4-LUT is really a 6x memory. Normally we think of the contents being written from the configuration bit stream, but Virtex architecture (and others) allow bits of LUT to be written and read from the general interconnect structure. achieves 6x density advantage over using CLB flip-flops. Furthermore, the two LUTs within a slice can be combined to create a 6 x 2-bit or 32 x -bit synchronous RAM, or a 6x-bit dual-port synchronous RAM. The Virtex-E LUT can also provide a 6-bit shift register of adjustable length. Newer FPGA families include larger onchip RAM blocks (usually dual ported): Called block selectrams in Xilinx Virtex series 4k bits each 7 8 istributed RAM CLB LUT configurable as istributed RAM A LUT equals 6x RAM Implements Single and ual-ports Cascade LUTs to increase RAM size Synchronous write Synchronous/Asynchronous read Accompanying flip-flops used for synchronous read LUT LUT LUT = RAM32XS WCLK A O A A4 or = RAM6XS WCLK A A RAM6X2S WCLK O A O A or O RAM6X A A WCLK SPO PRA PO PRA PR PR Shift Register LUT 6 registers, LUT Compact & fast C CL E K A A CL K SRL6E A A SRL6 Q Pipelining Buffers Q Bytes Spartan-IIE Memory Hierarchy istributed RAM Single-port ual port Cascadable 6x SP Coefficients Small FIFOs Scratch Pad Block RAMs 4Kbit blocks True dual-port Port A 4Kx 2Kx2 Kx4 52x8 256x6 Block RAM Cache Tag memory Large FIFOs Packet buffers Video line buffers Kilobytes Port B High-Performance External Memory Interfaces R I/O SSTL, HSTL, CTT SRAM SGRAM PB SRAM R SRAM BT SRAM QR SRAM Collaboration with memory vendors IT, Cypress, Micron, NEC, Samsung, Toshiba... Megabytes 9 2

6 ECEU53 FPGA Embedded Memory Summary Fast distributed RAM ata right beside logic Memory requirements solved by Block RAM Single and True ual-port RAM implementations FIFO for buffering data ata width conversion Cache Register stacks CAM for high-speed parallel searches Many more irect connection to external high-speed memory Memories in VHL for Xilinx Look at the Language Templates in Project Manager for how to describe memories in VHL for FPGAs Synthesis Templates: istributed RAM Block RAM Component Instantiations 2 22 Tri-State Buffers Using tri-state buffers The input signal is only connected to the output signal when the enable signal is asserted Tri state buffers are used when multiple gates may need to drive a single logical signal line Care must be taken to ensure that only one output is enabled to drive the output signal at any given time E In Out Tri-state buffers are like a distributed mux E I E In Out ENABLE E I OUT IN OUT E2 I

7 ECEU53 Registers Connected by a Tri-state Bus Can make any register transfer R[i] R[j] Can t have G i = G j = for ij Violating this constraint gives low resistance path from power supply to ground 25