ECEU530. Last Few Lectures. ECE U530 Digital Hardware Synthesis. What is on Quiz 2. Projects. Today:

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1 ECE U530 Digital Hardware Synthesis Prof. Miriam Leeser November 29, 2006 Lecture 20: Review for Quiz Generics and Generate Functions and Procedures Memories Teaching Evaluations Quiz on Monday December 4 Today: Review for Quiz Teaching Evaluations December 4: Quiz Last Few Lectures December 6: Project help and code demos Final Project Reports due Wed, December 13 You must demo your project code to me along with handing in your final project report December 6 in class I will look at people s project code ECE U530 F06 2 What is on Quiz 2 Calculator in VHDL Generics and Generate statements: Ashenden Chapters 12, 14 Lecture 13 Functions and Procedures: Ashenden Chapter 7 MAC example and pipelining Lectures 19 and 20 Ashenden Chapter 6 Memories in VHDL Quiz is open book and notes. No CAD tools. Projects No more homeworks, just projects Comment your code Write a testbench You MUST synthesize your project AND simulate it Your final project report should include a copy of your simulation report, and results cut and pasted from your synthesis report. (Not the entire report.) Make an appointment to show me your working code between December 6 and December 13 This is part of your project grade! Project due date is December 13 at noon in 316 Dana 3 4

2 Final Project Report (see HO 6) Introduction: an overview of your project Design Description: details of your design. Include: Discussion of input and output signals, and what each is for A picture of a state machine, if your design is a state machine Explain what your project does Testing Methodology: A description of how you tested your design Write a testbench! How you chose the test vectors for your testbench. Discussion: Lessons learned. What was difficult. What you wished you had learned in class. Anything else that you wish to discuss. Conclusions and Future Work: What worked, what didn t. What you would do if you had more time. References! Appendix: VHDL Design Code: Your code should be well commented. VHDL Testbench Code: Your testbench should be well commented. Simulation Results: Bitmaps from your simulation. Synthesis Results: Results from your Synthesis Report In place of constants Generics As parameters to functions, entities, etc. Use a generic map to specify values when the function or component is used Allows you to specify n-bit wide components 5 6 Generics As Constants Specify constants associated with an entity as generic: Example: delay entity and_gate is generic (delay : time := 5 ns port (a, b : in std_logic; o : out std_logic end and_gate; architecture arch of and_gate is o <= a and b after delay; end arch; Using Generics architecture structural of mux21 is... component AND2 generic (delay: time port(o:out std_logic; I0,I1:in std_logic end component;... g1: AND2 generic map (delay => 2ns port map(i0=>sel_n, I1 => A, O => c 7 8

3 Generics As Parameters Allows parametrization entity adder is generic (width : positive := 4 port (a, b : in std_logic_vector(0 to width 1 o : out std_logic_vector(0 to width) end adder; Generic Map A1 : adder generic map (width => 8 port map (av, bv, o Generic Example: N-Input Gate entity generic_or is generic (n: positive:=2 port (in1 : in std_logic_vector ((n-1) downto 0 z : out std_logic end entity generic_or; architecture behavioral of generic_or is process (in1) is variable sum : std_logic:= 0 ; sum := 0 ; -- on an input signal transition sum must be reset for i in 0 to (n-1) loop sum := sum or in1(i end loop; z <= sum; end process; end architecture behavioral; Map the generics to create different size OR gates 9 10 Example: Using the Generic N-Input OR Gate N-bit Register architecture structural of full_adder is component generic_or generic (n: positive port (in1 : in std_logic_vector ((n-1) downto 0 z : out std_logic end component; remainder of the declarative region from earlier example... H1: half_adder port map (a => In1, b => In2, sum=>s1, carry=>s3 H2:half_adder port map (a => s1, b => c_in, sum =>sum, carry => s2 O1: generic_or generic map (n => 2) port map (a => s2, b => s3, c => c_out end structural; Full adder model can be modified to use the generic OR gate model via the generic map () construct Analogy with macros 11 entity REG is generic (N: integer := 4) port(clk, Reset: in std_logic; D: in std_logic_vector (N-1 downto 0 Q: out std_logic_vector (N-1 downto 0) end entity REG; architecture gdff of REG is process (CLK,Reset) if (Reset = 0 ) then Q <= (others => 0 elsif rising_edge(clk) then Q <= D; end if; end process; end architecture gdff; 12 N D Q REG EN N RST

4 Generate Statement Automatically Generates Multiple Component Instantiations Two Kinds of Statements Iteration FOR... GENERATE Conditional IF... GENERATE Use Generate Statement to Reduce Coding Effort Can Include Any Concurrent Statement Including Another Generate Statement Does Not Execute Directly, But Expands into Code Which Does Execute (Macro) The Generate Statement: Example Instantiating an register entity dregister is port ( d : in std_logic_vector(7 downto 0 q : out std_logic_vector(7 downto 0 clk : in std_logic end entity dregisters architecture behavioral of dregister is d: for i in d range generate reg: dff port map( (d=>d(i), q=>q(i), clk=>clk; end generate; end architecture register; Instantiating interconnected components Declare local signals used for the interconnect This is different from register with generics This is structural, generic description is behavioral The Generate Statement: Example library IEEE; use IEEE.std_logic_1164.all; entity multi_bit_generate is generic(gate_delay:time:= 1 ns; width:natural:=8 -- the default is a 8-bit ALU port( in1 : in std_logic_vector(width-1 downto 0 in2 : in std_logic_vector(width-1 downto 0 result : out std_logic_vector(width-1 downto 0 opcode : in std_logic_vector(1 downto 0 cin : in std_logic; cout : out std_logic end entity multi_bit_generate; architecture behavioral of multi_bit_generate is component one_bit is -- declare the single bit ALU generic (gate_delay:time port (in1, in2, cin : in std_logic; result, cout : out std_logic; opcode: in std_logic_vector (1 downto 0) end component one_bit; signal carry_vector: std_logic_vector(width-2 downto 0 -- the set of signals for the ripple carry a0: one_bit generic map (gate_delay) -- instantiate ALU for bit position 0 port map (in1=>in1(0), in2=>in2(0), result=>result(0), cin=>cin, opcode=>opcode, cout=>carry_vector(0) a2to6: for i in 1 to width-2 generate -- generate instantiations for bit positions 2-6 a1: one_bit generic map (gate_delay) port map(in1=>in1(i), in2=> in2(i), cin=>carry_vector(i-1), result=>result(i), cout=>carry_vector(i),opcode=>opcode end generate; a7: one_bit generic map (gate_delay) -- instantiate ALU for bit position 7 port map (in1=>in1(width-1), in2=>in2(width-1), result=> result(width-1), cin=>carry_vector(width-2), opcode=>opcode, cout=>cout end architecture behavioral; Using the Generate Statement Identify components with regular interconnect Declare local arrays of signals for the regular interconnections Write the generate statement Analogy with loops and multidimensional arrays Beware of unconnected signals! Instantiate remaining components of the design 15 16

5 Memory Structures Register Register File ROM: Read only memory RAM: Random access memory Embedded RAM in FPGAs: Select RAM How are registers inferred? Generic RAM - Entity LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY ram IS GENERIC (bits: INTEGER:=8; -- # of bits per word words: INTEGER := # of words in the memory PORT (wr_ena, clk: IN STD_LOGIC; addr: IN INTEGER RANGE 0 to words-1; data_in: IN STD_LOGIC_VECTOR(bits -1 downto 0 data_out: OUT STD_LOGIC_VECTOR(bits 1 downto 0) END ram; Generic RAM architecture Generic ROM - entity ARCHITECTURE LUT_based_ram OF ram IS TYPE vector_array IS ARRAY (0 TO words-1) OF STD_LOGIC_VECTOR(bits 1 DOWNTO 0 SIGNAL memory: vector_array; PROCESS(clk, addr) IF(wr_ena= 1 ) THEN IF (rising_edge(clk)) THEN memory(addr) <= data_in; END_IF; END IF; END PROCESS; data_out <= memory(addr END LUT_based_RAM; LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY rom IS GENERIC (bits: INTEGER:=8; -- # of bits per word words: INTEGER := 8 -- # of words in the memory PORT ( addr: IN INTEGER RANGE 0 TO words-1; data: OUT STD_LOGIC_VECTOR(bits 1 DOWNTO 0) END rom; 19 20

6 Generic ROM - architecture ARCHITECTURE behavioral OF rom IS TYPE vector_array IS ARRAY (0 TO words-1) OF STD_LOGIC_VECTOR(bits 1 DOWNTO 0 CONSTANT memory: vector_array := ("0000_0000", "0000_0010", "0000_0100", "0000_1000", "0001_0000", "0010_0000", "0100_0000", "1000_0000" data <= memory(addr END rom; Generic ROM hexadecimal notation ARCHITECTURE behavioral OF rom IS TYPE vector_array IS ARRAY (0 TO words-1) OF STD_LOGIC_VECTOR(bits 1 DOWNTO 0 CONSTANT memory: vector_array := (X"00", X"02", X"04", X"08", X"10", X"20", X"40", X"80" data <= memory(addr END rom; Distributed RAM CLB LUT configurable as Distributed RAM A LUT equals 16x1 RAM Implements Single and Dual-Ports Cascade LUTs to increase RAM size Synchronous write Synchronous/Asynchronous read Accompanying flip-flops used for synchronous read LUT LUT LUT = RAM32X1S D WE WCLK A0 O A1 A2 A3 A4 or = RAM16X1S D WE WCLK A0 A1 A2 A3 RAM16X2S D0 D1 WE WCLK O0 A0 O1 A1 A2 A3 or O RAM16X1D D WE A0 A1 A2 A3 WCLK SPO DPRA0 DPO DPRA1 DPRA2 DPRA3 library IEEE; use IEEE.STD_LOGIC_1164.all; library UNISIM; use UNISIM.all; RAM 16x1 (1) entity RAM_16X1_DISTRIBUTED is port( CLK : in STD_LOGIC; WE : in STD_LOGIC; ADDR : in STD_LOGIC_VECTOR(3 downto 0 DATA_IN : in STD_LOGIC; DATA_OUT : out STD_LOGIC end RAM_16X1_DISTRIBUTED; 23 24

7 RAM 16x1 (2) RAM 16x1 (3) architecture RAM_16X1_DISTRIBUTED_STRUCTURAL of RAM_16X1_DISTRIBUTED is component ram16x1s generic( INIT : BIT_VECTOR(15 downto 0) := X"0000" port( O : out std_ulogic; A0 : in std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; A3 : in std_ulogic; D : in std_ulogic; WCLK : in std_ulogic; WE : in std_ulogic end component; ram16x1s_1: ram16x1s generic map (INIT => X 0000") port map (O => DATA_OUT, A0 => ADDR(0), A1 => ADDR(1), A2 => ADDR(2), A3 => ADDR(3), D => DATA_IN, WCLK => CLK, WE => WE end RAM_16X1_DISTRIBUTED_STRUCTURAL; ROM 16x1 (1) ROM 16x1 (2) library IEEE; use IEEE.STD_LOGIC_1164.all; library UNISIM; use UNISIM.all; entity ROM_16X1_DISTRIBUTED is port( ADDR : in STD_LOGIC_VECTOR(3 downto 0 DATA_OUT : out STD_LOGIC end ROM_16X1_DISTRIBUTED; architecture ROM_16X1_DISTRIBUTED_STRUCTURAL of ROM_16X1_DISTRIBUTED is component ram16x1s generic( INIT : BIT_VECTOR(15 downto 0) := X"0000" port( O : out std_ulogic; A0 : in std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; A3 : in std_ulogic; D : in std_ulogic; WCLK : in std_ulogic; WE : in std_ulogic end component; signal Low : std_ulogic := 0 ; 27 28

8 ROM 16x1 (3) rom16x1s_1: ram16x1s generic map (INIT => X"F0C1") port map (O=>DATA_OUT, A0=>ADDR(0), A1=>ADDR(1), A2=>ADDR(2), A3=>ADDR(3), D=>Low, WCLK=>Low, WE=>Low end ROM_16X1_DISTRIBUTED_STRUCTURAL; Conversion std_logic_vector => integer LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; entity test is end test; architecture behavior of test is SIGNAL stdl_addr: STD_LOGIC_VECTOR(7 DOWNTO 0 SIGNAL i_addr : INTEGER; u_addr <= conv_integer(unsigned(stdl_addr) end behavior; LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY instruction_rom IS Instruction ROM example (1) GENERIC ( w : INTEGER := 16; n : INTEGER := 8; m : INTEGER := 3 PORT ( Instr_addr : IN STD_LOGIC_VECTOR(m-1 DOWNTO 0 Instr : out STD_LOGIC_VECTOR(w-1 DOWNTO 0) END instruction_rom; Instruction ROM example (2) ARCHITECTURE ins_rom OF insstruction_rom IS SIGNAL temp: INTEGER RANGE 0 TO 7; TYPE vector_array IS ARRAY (0 to n-1) OF STD_LOGIC_VECTOR(w-1 DOWNTO 0 CONSTANT memory : vector_array := ( "0000_0000_0000_0000", "0000_0000_0000_0000", "1101_0100_0101_1001", "1101_0100_0101_1000", temp <= conv_integer(unsigned(instr_addr) Instr <= memory(temp "0110_1000_1000_0111", "0100_1001_1001_1010", "1111_0110_0111_0101", "1111_0110_0111_0100", END instruction_rom; 31 32

9 Generic dual-ported memory (1) LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY memory_local IS PORT( wen : IN STD_LOGIC; clk : IN STD_LOGIC; data_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0 addr1 : IN STD_LOGIC_VECTOR(4 DOWNTO 0 addr2 : IN STD_LOGIC_VECTOR(4 DOWNTO 0 data_out1: OUT STD_LOGIC_VECTOR(31 DOWNTO 0 data_out2: OUT STD_LOGIC_VECTOR(31 DOWNTO 0) END memory_local; Generic dual-ported memory (2) ARCHITECTURE memory_local OF memory_local IS TYPE vector_array IS ARRAY (0 TO 31) OF STD_LOGIC_VECTOR(31 DOWNTO 0 SIGNAL memory : vector_array; SIGNAL temp1: INTEGER RANGE 0 TO 31; SIGNAL temp2: INTEGER RANGE 0 TO 31; temp1 <= conv_integer(unsigned(addr1) temp2 <= conv_integer(unsigned(addr2) PROCESS(clk, temp1, temp2) IF (wen = '1') THEN IF (clk = '1'AND clk'event) THEN memory(temp2) <= data_in; END IF; END IF; END PROCESS; data_out1 <= memory(temp1 data_out2 <= memory(temp2 END memory_local; Generate Statement FOR-Scheme All objects created are similar The GENERATE parameter must be discrete and is undefined outside the GENERATE statement Loop cannot be terminated early name name : FOR FOR N IN IN 1 TO TO 8 GENERATE concurrent-statements END END GENERATE name; name; FOR-Scheme Example -- --this uses uses the the and_gate component from from before ARCHITECTURE test_generate OF OF test_entity IS IS SIGNAL S1, S1, S2, S2, S3: S3: BIT_VECTOR(7 DOWNTO 0 0 G1 G1 : FOR FOR N IN IN 7 DOWNTO 0 GENERATE and_array : and_gate GENERIC MAP MAP (2 (2 ns, ns, 3 ns) ns) PORT PORT MAP MAP (S1(N), S2(N), S3(N) END END GENERATE G1; G1; END END test_generate; 35 36

10 Generate Statement IF-Scheme IF-Scheme Example Allows for conditional creation of components Cannot use ELSE or ELSIF clauses with the IF-scheme name name : IF IF (boolean expression) GENERATE concurrent-statements END END GENERATE name; name; 37 ARCHITECTURE test_generate OF OF test_entity SIGNAL S1, S1, S2, S2, S3: S3: BIT_VECTOR(7 DOWNTO 0 0 G1 G1 : FOR FOR N IN IN 7 DOWNTO 0 GENERATE G2 G2 : IF IF (N (N = 7) 7) GENERATE or1 or1 : or_gate GENERIC MAP MAP (3 (3 ns, ns, 3 ns) ns) PORT PORT MAP MAP (S1(N), S2(N), S3(N) END END GENERATE G2; G2; G3 G3 : IF IF (N (N < 7) 7) GENERATE and_array : and_gate GENERIC MAP MAP (2 (2 ns, ns, 3 ns) ns) PORT PORT MAP MAP (S1(N), S2(N), S3(N) END END GENERATE G3; G3; END END GENERATE G1; G1; END END test_generate; 38 Structural 8 Bit Shift Register Example (Architecture - Generate with If Scheme) Example VHDL Package ARCHITECTURE structural OF shift_reg8_str IS -- COMPONENT INSTANTIATION (GENERATE W/ IF) G1:FOR i IN 0 TO 7 GENERATE -- COMPONENT DECLARATION COMPONENT mux2 GENERIC(tprop : delay PORT(a : IN level; b : IN level; sel : IN level; c : OUT level END COMPONENT; COMPONENT dff GENERIC(tprop : delay; tsu : delay PORT(d : IN level; clk : IN level; enable : IN level; q : OUT level; qn : OUT level END COMPONENT; -- BINDING INDICATIONS FOR ALL : mux2 USE ENTITY gate_lib.mux2(behav FOR ALL : dff USE ENTITY gate_lib.dff(behav G2 : IF (i = 0) GENERATE MUX1 : mux2 GENERIC MAP(tprop => tprop/2) PORT MAP(a => scan_in, b => d(i), sel => shift, c => mux_out(i) DFF1 : dff GENERIC MAP(tprop => tprop/2, tsu => tsu) PORT MAP(d => mux_out(i), clk => clk, enable => enable, q => dff_out(i) q(i) <= dff_out(i END GENERATE G2; G3 : IF (i > 0) GENERATE MUX1 : mux2 GENERIC MAP(tprop => tprop/2) PORT MAP(a => dff_out(i-1), b => d(i), sel => shift, c => mux_out(i) DFF1 : dff GENERIC MAP(tprop => tprop/2, tsu => tsu) PORT MAP(d => mux_out(i), clk => clk, enable => enable, q => dff_out(i) q(i) <= dff_out(i SIGNAL mux_out : level_vector(7 DOWNTO 0 SIGNAL dff_out : level_vector(7 DOWNTO 0 END GENERATE G3; END GENERATE G1; scan_out <= dff_out(7 END structural; 39 40

11 BBB )) <<< <<< uuu uuu mm xxx xxx ECEU530 VHDL Functions!#"$% &('() ) *$%+ % &(''!+,-./! ' 0+ #"123*/' %+ % 8,':9',%+ %;!-0< = = = = > 5 -'? ' ;%,0- %;' &('!;-0<!@A 0 #"$ %&:'B function xor3 (a,b,c: in std_logic) return std_logic is return (a xor b xor c end xor3; CEDGFIHKJ L:M 4! ON = = 4!@M : ECE CEDGFIHKJ L:M 4! ON = = 4!@M : 44 VHDL Procedures P Q/R0STR3U V0W XXXX Y3U ZI[ \\\\ UUUU Y]TR^0_UR u#v v Ra`b cdfeghtb eeee i j#klkeam m `0kb klke3n e#bopq#n r!st vv yyyy kb pk3woeagedfokb knpcjqfx Rz0sS u q#e{he#j0npk3ofqnkn etlie#j0nqfx R0ST^a`b cdteghtb eeee i j#klke0 Example: Ripple carry adder using the xor3 function: sum(i+sum'low) := xor3 (a(i+a'low), b(i+b'low), c(i) For generality, the input parameters 'a'and 'b'as well as the output 'sum'are declared as unconstrained array types; i.e., no array bounds are given for the std_logic_vector type. Allows any width vector to be passed as a parameter. Array indices must be computed using the 'low attribute as an offset in order to achieve independence from the actual array indices which are passed in. 42 U530 F 06 Using the ripple_adder Procedure VHDL Generic lists VHDL generic lists are used in entity declarations for passing static information. Typical uses of generics are for controlling bus widths, feature inclusion, message generation, timing values. A generic will usually have a specified default value; this value can be overridden via VHDL configurations or by vendor-specific back-annotation methods. Generics offer a method for parameterizing entity declarations and architectures. Because the method of specifying generic values (other than defaults) can be vendor specific, generics will not be emphasized

12 VHDL Generics Example 45